TWI621238B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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Publication number
TWI621238B
TWI621238B TW105106350A TW105106350A TWI621238B TW I621238 B TWI621238 B TW I621238B TW 105106350 A TW105106350 A TW 105106350A TW 105106350 A TW105106350 A TW 105106350A TW I621238 B TWI621238 B TW I621238B
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Taiwan
Prior art keywords
layer
sealing resin
metal
metal compound
resin layer
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TW105106350A
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English (en)
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TW201705434A (zh
Inventor
Soichi Homma
Yuusuke Takano
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Toshiba Memory Corp
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Publication of TW201705434A publication Critical patent/TW201705434A/zh
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Publication of TWI621238B publication Critical patent/TWI621238B/zh

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    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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Abstract

本發明之實施形態提供能夠提高導電性屏蔽層與密封樹脂層之密接性之半導體裝置及其製造方法。
實施形態之半導體裝置具備：配線基板，其具有包含第1面與第2面之基體及接地配線；半導體晶片，其搭載於第1面上；外部連接端子，其設置於第2面上，且包含與接地配線電性連接之接地端子；密封樹脂層，其將半導體晶片密封；金屬化合物層，其與密封樹脂層之表面相接，且包含金屬氮化物；以及導電性屏蔽層，其以隔著金屬化合物層而覆蓋密封樹脂層之方式設置。接地配線於配線基板之側面露出，且與導電性屏蔽層電性連接。

Description

半導體裝置及其製造方法 【相關申請案】
本申請案享有以日本專利申請案2015-152646號(申請日：2015年7月31日)為基礎申請案之優先權。本申請案藉由參照該基礎申請案而包含基礎申請案之全部內容。
本發明之實施形態係關於一種半導體裝置及其製造方法。
於使用於通訊設備等之半導體裝置中，為了抑制EMI(Electro Magnetic Interference，電磁干擾)等電磁波故障，而使用將密封樹脂層之表面以導電性屏蔽層覆蓋之構造。為了利用上述構造獲得充分之屏蔽效果，較佳為將導電性屏蔽層與接地配線電性連接，而經由接地配線將電磁波雜訊釋放至外部。
為了使導電性屏蔽層與接地配線之間之電阻率較低，作為導電性屏蔽層之材料而使用例如銅等。然而，銅等之導電性屏蔽層容易自密封樹脂層剝離。如此，若導電性屏蔽層與密封樹脂層之密接性較低則存在半導體裝置之可靠性降低之情況。
本發明之實施形態提供一種導電性屏蔽層與密封樹脂層之密接性較高之半導體裝置及其製造方法。
實施形態之半導體裝置具備：配線基板，其具有包含第1面與第2面之基體及接地配線；半導體晶片，其搭載於第1面上；外部連接端 子，其設置於第2面上，且包含與接地配線電性連接之接地端子；密封樹脂層，其將半導體晶片密封；金屬化合物層，其與密封樹脂層之表面相接，且包含金屬氮化物；以及導電性屏蔽層，其以隔著金屬化合物層而覆蓋密封樹脂層之方式設置。接地配線於配線基板之側面露出，且與導電性屏蔽層電性連接。
1‧‧‧配線基板
2a‧‧‧外部連接端子
2b‧‧‧外部連接端子
3‧‧‧半導體晶片
3A‧‧‧半導體晶片
3B‧‧‧半導體晶片
4‧‧‧接合線
5‧‧‧密封樹脂層
6‧‧‧金屬化合物層
6a‧‧‧金屬化合物部
6b‧‧‧金屬化合物部
7‧‧‧導電性屏蔽層
7a‧‧‧金屬層
7b‧‧‧金屬層
8‧‧‧保護層
10‧‧‧半導體裝置
11‧‧‧絕緣基體
12a‧‧‧導電層
12b‧‧‧導電層
13a‧‧‧導電層
13b‧‧‧導電層
14a‧‧‧導通孔
14b‧‧‧導通孔
15‧‧‧絕緣層
16‧‧‧絕緣層
31‧‧‧凸塊
32‧‧‧樹脂層
圖1係表示半導體裝置之構造例之剖面模式圖。
圖2係表示半導體裝置之構造例之立體模式圖。
圖3係表示半導體裝置之其他構造例之剖面模式圖。
圖4係表示半導體裝置之其他構造例之剖面模式圖。
圖5係表示半導體裝置之其他構造例之剖面模式圖。
圖6係表示半導體裝置之其他構造例之剖面模式圖。
圖7係表示半導體裝置之製造方法例之流程圖。
圖8係用來說明半導體裝置之製造方法例之剖面模式圖。
圖9係用來說明半導體裝置之製造方法例之剖面模式圖。
以下，參照圖式對實施形態進行說明。圖式中所記載之各構成要素之厚度與平面尺寸之關係、各構成要素之厚度之比率等存在與現實不同之情況。又，於實施形態中，對實質上相同之構成要素標註相同之符號並適當省略說明。
圖1係表示半導體裝置之構造例之剖面模式圖。圖2係表示半導體裝置之構造例之立體模式圖。半導體裝置10具備配線基板1、外部連接端子2a、2b、半導體晶片3A、接合線4、密封樹脂層5、金屬化合物層6、以及導電性屏蔽層7。
配線基板1具有：絕緣基體11，其具有第1面與第2面；導電層12a，其設置於第1面上；導電層12b，其設置於第1面上；導電層 13a，其設置於第2面上，且經由導通孔14a而與導電層12a電性連接；導電層13b，其設置於第2面上，且經由導通孔14b而與導電層12b電性連接；阻焊劑等絕緣層15，其具有使導電層12a之一部分露出之開口部；以及阻焊劑等絕緣層16，其具有使導電層13a之一部分及導電層13b之一部分露出之開口部。配線基板1亦可具有與半導體晶片3A之至少一部分重疊之導電層。與半導體晶片3A之至少一部分重疊之導電層與導通孔14a電性連接，且與導通孔14b電性分離。藉由設置上述導電層，能夠抑制經由配線基板1之不必要之電磁波之洩漏。
作為配線基板1之絕緣基體11，例如能夠使用矽基板或玻璃基板、陶瓷基板、玻璃環氧樹脂等樹脂基板等。導電層12a、導電層12b、導電層13a、及導電層13b之至少一者使用例如以銅或銀為主成分之金屬膜或包含銅或銀之導電性膏，亦可根據需要對表面實施鍍鎳或鍍金等。導通孔14a及導通孔14b例如具有：導體層，其設置於貫通絕緣基體11之開口之內表面；以及填孔材料，其填充於導體層之內側。導體層例如使用銅或銀或包含該等之導電性膏，亦可根據需要而對表面實施鍍鎳或鍍金等。填孔材料使用例如絕緣性材料或導電性材料而形成。導體層並不限定於此，例如亦可藉由於貫導通孔內壁利用鍍敷等被覆金屬材料(銅等)而形成導通孔14a及導通孔14b。
外部連接端子2a設置於導電層13a上，且與導電層13a電性連接。外部連接端子2a具有作為接地端子之功能。此時，導電層12a、導電層13a、及導通孔14a具有作為接地配線之功能。外部連接端子2b設置於導電層13b上，且與導電層13b電性連接。外部連接端子2b具有作為信號端子或電源端子之功能。此時，導電層12b、導電層13b、及導通孔14b具有作為信號配線或電源配線之功能。外部連接端子2a及外部連接端子2b例如具有焊料球。並不限定於此，外部連接端子2a及外部連接端子2b亦可具有焊盤代替焊料球。
半導體晶片3A隔著晶粒黏著膜等有機接著層而搭載於第1面上。半導體晶片3A具有電極，且以使電極露出之方式積層為多級。積層為多級之半導體晶片3A經由晶粒黏著膜等有機接著層而依次接著。積層為多級之半導體晶片3A之電極藉由接合線4而與配線基板1電性連接。半導體晶片3A經由接合線4而與導電層12a電性連接。作為接合線4，例如可列舉金導線、銀導線、銅導線等。銅導線之表面亦可由鈀膜覆蓋。
密封樹脂層5以將半導體晶片3A密封之方式設置。密封樹脂層5含有SiO2等無機填充材料。又，無機填充材料除包含SiO2以外，亦可包含例如氫氧化鋁、碳酸鈣、氧化鋁、氮化硼、氧化鈦、或鈦酸鋇等。無機填充材料例如為粒狀，具有調整密封樹脂層5之黏度或硬度等之功能。密封樹脂層5中之無機填充材料之含量例如為60%以上且90%以下。作為密封樹脂層5，例如能夠使用無機填充材料與絕緣性之有機樹脂材料之混合物。作為有機樹脂材料，例如可列舉環氧樹脂。再者，無機填充材料亦可於密封樹脂層5之表面露出。
金屬化合物層6以與密封樹脂層5之表面相接之方式設置。於圖1中，金屬化合物層6具有：金屬化合物部6a，其與密封樹脂層5之表面相接且包含金屬碳化物；以及金屬化合物部6b，其設置於金屬化合物部6a上且包含金屬氮化物。金屬化合物部6b設置於金屬化合物部6a與導電性屏蔽層7之間。於無機填充材料於密封樹脂層5之表面露出之情形時，金屬化合物層6與露出之無機填充材料相接。藉此，能夠提高密封樹脂層5與導電性屏蔽層7之密接性。金屬化合物層6亦可不必為連續膜。例如，亦可將相互隔開之複數個金屬化合物部視為金屬化合物層6。
金屬化合物部6a之厚度例如較佳為0.1nm以上且100nm以下。於未達0.1nm之情形時，存在密封樹脂層5與導電性屏蔽層7之密接性降 低之情況。於超過100nm之情形時，存在金屬化合物部6a之電阻率變高，而屏蔽效果降低之情況。金屬化合物部6b之厚度例如較佳為0.1nm以上且100nm以下。於未達0.1nm之情形時，存在密封樹脂層5與導電性屏蔽層7之密接性降低之情況。於超過100nm之情形時，存在金屬化合物部6b之電阻率變高，而屏蔽效果降低之情況。
作為金屬碳化物，例如可列舉鎳之碳化物、鈦之碳化物、鐵之碳化物、鉻之碳化物、銅之碳化物、鉭之碳化物、鋁之碳化物、或不鏽鋼(SUS304、SUS316等)之碳化物等。作為金屬氮化物，例如可列舉鎳之氮化物、鈦之氮化物、鐵之氮化物、鉻之氮化物、銅之氮化物、鉭之氮化物、鋁之氮化物、或不鏽鋼(SUS304、SUS316等)之氮化物等。再者，金屬化合物層6亦可不必包含金屬碳化物。
金屬化合物層6覆蓋配線基板1之側面之至少一部分。此時，亦可使接地配線之至少一部分之側面，例如使導電層12a及導電層13a之至少一導電層之側面於配線基板1之側面露出，而使上述至少一導電層之側面接觸於金屬化合物層6。藉此，能夠經由外部連接端子2a而使不必要之電磁波釋放至外部。上述至少一導電層與金屬化合物層6之接觸部亦可設置複數個。
導電性屏蔽層7以隔著金屬化合物層6覆蓋密封樹脂層5之方式設置。導電性屏蔽層7例如較佳為包含銅、鎳、鈦、金、銀、鈀、鉑、鐵、鋁、錫或鉻等金屬、上述金屬之合金、不鏽鋼、或銦錫氧化物(Indium Tin Oxide：ITO)等。導電性屏蔽層7亦可具有上述材料之複合層或積層。
導電性屏蔽層7之厚度較佳為根據其電阻率而設定。例如，較佳為以將導電性屏蔽層7之電阻率除以厚度所得之薄片電阻值成為0.5Ω以下之方式，設定導電性屏蔽層7之厚度。藉由將導電性屏蔽層7之薄片電阻值設為0.5Ω以下，能夠再現性良好地抑制來自密封樹脂層5之 不必要之電磁波之洩漏。導電性屏蔽層7之厚度例如較佳為0.1μm以上且20μm以下。於未達0.1μm之情形時，存在屏蔽效果降低之情況。於超過20μm之情形時，存在導電性屏蔽層7之應力較大而導電性屏蔽層7剝離之情況。
導電性屏蔽層7具有將自半導體晶片3A等輻射之不必要之電磁波屏蔽而抑制向外部洩漏之功能。亦可將金屬化合物層6視為導電性屏蔽層之一部分。
導電性屏蔽層7亦可覆蓋配線基板1之側面之至少一部分。此時，導電性屏蔽層7與接地配線之至少一部分，例如與導電層12a及導電層13a之至少一導電層電性連接。例如，亦可使導電層12a及導電層13a之至少一導電層之側面於配線基板1之側面露出，而使導電性屏蔽層7與上述至少一導電層之側面相接。上述至少一導電層與導電性屏蔽層7相接，藉此能夠經由外部連接端子2a而向外部釋放不必要之電磁波。上述至少一導電層與導電性屏蔽層7之接觸部亦可設置複數個。導通孔14a亦可具有於配線基板1之側面露出而與導電性屏蔽層7相接之切斷面。由於藉由設置上述切斷面，能夠增加導通孔14a與導電性屏蔽層7之接觸面積，故而能夠降低連接電阻。
於半導體裝置10中，來自厚度方向之電磁波雜訊較來自厚度方向之垂直方向之電磁波雜訊產生得更多。因此，於導電性屏蔽層7中，較佳為密封樹脂層5之上表面上之區域厚於密封樹脂層5之側面上之區域。
本實施形態之半導體裝置於密封樹脂層與導電性屏蔽層之間具備包含金屬碳化物與金屬氮化物之金屬化合物層。利用金屬化合物層能夠提高密封樹脂層與導電性屏蔽層之密接性。認為其原因在於，金屬氮化物中之金屬原子或氮原子與密封樹脂層中之無機填充材料或樹脂結合。
本實施形態之半導體裝置並不限定於圖1所示之構造。圖3係表示半導體裝置之其他構造例之剖面模式圖。圖3所示之半導體裝置10與圖1所示之半導體裝置10比較，金屬化合物層6不設置於配線基板1之側面，且導電性屏蔽層7與導電層12a及導電層13a之至少一導電層之側面相接之構成不同。藉此，能夠經由外部連接端子2a而將不必要之電磁波向外部釋放。上述至少一導電層與導電性屏蔽層7之接觸部亦可設置複數個。導電性屏蔽層7亦可延伸至基體11之第2面上為止。
圖4係表示半導體裝置之其他構造例之剖面模式圖。圖4所示之半導體裝置10與圖1所示之半導體裝置10比較，於金屬化合物層6由包含金屬碳化物及金屬氮化物之兩者之混合層形成之構成上有所不同。此時，金屬化合物層6之厚度例如較佳為0.1nm以上且100nm以下。於未達0.1nm之情形時，存在密封樹脂層5與導電性屏蔽層7之密接性降低之情況。於超過100nm之情形時，存在金屬化合物層6之電阻率變高而屏蔽效果降低之情況。
圖5係表示半導體裝置之其他構造例之剖面模式圖。圖5所示之半導體裝置10與圖1所示之半導體裝置10比較，進而具備具有金屬層7a與金屬層7b之導電性屏蔽層7與設置於導電性屏蔽層7上之保護層8之構成不同。並不限定於圖5，亦可不設置金屬層7b而半導體裝置10具備設置於金屬層7a上之保護層8。
金屬層7a具有作為緩衝層(基底層)之功能。金屬層7a例如包含鈦、鉻、鎳、鉬、鉭或鐵等金屬、上述金屬之合金、不鏽鋼、或ITO等。金屬層7a亦可具有上述材料之複合膜或積層膜。較佳為金屬層7a與金屬化合物層6之密接性較金屬層7b與金屬化合物層6之密接性更高。金屬層7a之厚度例如較佳為0.01μm以上且20μm以下。於未達0.01μm之情形時，密封樹脂層5與導電性屏蔽層7之密接性降低。於超過20μm之情形時，存在金屬層7a之應力較大而金屬層7a剝離之情 況。
較佳為金屬層7b之電阻率較金屬層7a之電阻率低。金屬層7b例如包含銅、銀、金、鈀、或鉑等金屬。金屬層7b之厚度例如較佳為0.1μm以上且20μm以下。於未達0.1μm之情形時，存在屏蔽效果降低之情況。於超過20μm之情形時，存在金屬層7b之應力較大而金屬層7b剝離之情況。
保護層8耐蝕性及耐遷移性優異，例如具有提高導電性屏蔽層7之防潮性而抑制導電性屏蔽層7之腐蝕之功能。作為保護層8，例如使用金屬材料、樹脂材料、陶瓷材料等。保護層8例如包含鈦、鉻、鎳、鐵、鋁、鉬、鉭、錳、鑭或銅等金屬、或不鏽鋼、上述金屬之氧化物、上述金屬之氮化物、ITO、碳、石墨、類鑽碳、ZrB、MoS、TiON、TiAlN、環氧樹脂、聚醯亞胺樹脂、丙烯酸樹脂、矽酮樹脂、聚醯胺樹脂等。保護層8之厚度例如較佳為0.01μm以上且20μm以下。於未達0.01μm之情形時，存在抑制導電性屏蔽層7之腐蝕之效果降低之情況。於超過20μm之情形時，存在保護層8之應力較大而金屬層7b剝離之情況。又，成本亦變高。
圖6係表示半導體裝置之其他構造例之剖面模式圖。圖6所示之半導體裝置10與圖1所示之半導體裝置10比較，具備半導體晶片3B代替半導體晶片3A，且不具備接合線4之構成不同。半導體晶片3B具有與導電層12b電性連接之凸塊31。凸塊31例如包含金、錫、鉛、銀、銅、鉍、及鋅之至少一種金屬、或上述金屬之合金等。凸塊31亦可為複合膜或積層膜。
半導體晶片3B例如係藉由對形成有凸塊31之基板切割使之單片化而形成。半導體晶片3B利用覆晶安裝而搭載於配線基板1上。此時，亦可進行助焊劑之塗佈或預處理等。於使用助焊劑之情形時，利用溶劑或純水等將配線基板1洗淨。又，圖6所示之半導體裝置10於配 線基板1與半導體晶片3B之間具備底部填充膠樹脂等樹脂層32。半導體晶片3B亦可隔著凸塊而積層。又，具備貫通電極之半導體晶片3B亦可隔著凸塊而積層。
於圖1、圖3至圖6所示之半導體裝置10中，較不設置導電性屏蔽層7之半導體裝置更能夠減少電磁波雜訊之量。又，於圖1、圖3至圖6所示之半導體裝置中，例如於-55℃~150℃之熱循環試驗(Temperature Cycling Test：TCT)中，即便經過2000個循環之後亦難以產生導電性屏蔽層7之異常、半導體晶片之連接不良等。又，例如於150℃、1000小時之高溫保存試驗或85℃、濕度85%、偏壓電壓3.2V、1000小時之高溫高濕偏壓試驗中，難以產生例如導電性屏蔽層7之腐蝕、半導體晶片之連接不良等。
其次，參照圖7至圖9對本實施形態之半導體裝置之製造方法例進行說明。圖7係表示圖1所示之半導體裝置10之製造方法例之流程圖。圖7所示之半導體裝置之製造方法例具備基板準備步驟(S1)、元件搭載步驟(S2)、樹脂密封步驟(S3)、分離步驟(S4)、熱處理步驟(S5)、蝕刻步驟(S6)、以及屏蔽層形成步驟(S7)。再者，本實施形態中之半導體裝置之製造方法例之步驟內容及步驟順序未必限定為圖7所示之步驟。
圖8及圖9係用來說明半導體裝置10之製造方法例之剖面模式圖。於圖8中，模式性地圖示進行基板準備步驟(S1)至分離步驟(S4)之後之半導體裝置。於圖9中，模式性地圖示進行基板準備步驟(S1)至屏蔽層形成步驟(S7)之後之半導體裝置。
基板準備步驟(S1)係準備配線基板1之步驟。此處，作為一例而製作複數個配線基板1矩陣狀地連設之構造之集合基板。於基板準備步驟(S1)中，於於分離步驟(S4)中切割之部位預先形成導電層12a及導電層13a。又，於配線基板1上預先貼附片狀或膏狀之晶粒黏著膜。亦 可利用切割、雷射、由拉伸所致之生生斷開等而將晶粒黏著膜切斷。
元件搭載步驟(S2)係於配線基板1之第1面上搭載半導體晶片3A之步驟。於元件搭載步驟(S2)中，一面使半導體晶片3A之電極露出一面使半導體晶片3A隔著晶粒黏著膜而積層為多級。又，於元件搭載步驟(S2)中，亦可進行將半導體晶片3A彼此及半導體晶片3A與導電層12b經由接合線4而電性連接之接合。
於元件搭載步驟(S2)中，亦可於搭載半導體晶片3A之後進行加熱處理。於上述加熱處理中，藉由將配線基板1放入至烤箱進行加熱，能夠使配線基板1與半導體晶片3A接著而使半導體晶片3A彼此接著。然後，亦可進行電漿洗淨而使半導體晶片3A之電極表面清潔化。例如，亦可使用氬、氧、氫、或氬及氫之兩者進行電漿處理。亦可於接合之後進行上述電漿處理。
樹脂密封步驟(S3)係以將半導體晶片3A密封之方式形成密封樹脂層5之步驟。作為密封樹脂層5之形成方法，例如可列舉使用無機填充材料與有機樹脂等之混合物之轉注模塑法、壓縮模塑法、注射模塑法、片狀模塑法、或樹脂點膠法等。
分離步驟(S4)係針對每一半導體裝置10進行基板之切割而分離為各個半導體裝置10之步驟。例如，使用金剛石刀等刀進行切割。亦可於切割時將導電層12a等具有作為接地配線之功能之導電層切斷而使上述導電層於配線基板1之側面露出。於分離步驟(S4)後，例如亦可利用具備YAG(Yttrium Aluminum Garnet，釔-鋁-石榴石)雷射等之雷射標記裝置，於密封樹脂層5之上表面刻印產品名、產品編號、生產年份星期、生產工廠等產品資訊。
於熱處理步驟(S5)中，將已單片化之半導體裝置放入至烤箱，以100℃以上且260℃以下之溫度進行加熱而將被半導體裝置10吸濕之水分等去除。於未達100℃之情形時，水分未被去除而導致密封樹脂層5 與導電性屏蔽層7之密接性降低。於超過260℃之情形時，由於加熱溫度較回流焊溫度高，故而存在對半導體裝置10帶來損傷之情況。亦可將去除上述水分等之步驟稱為脫氣步驟。熱處理步驟(S5)亦可具有複數個熱處理步驟。例如，亦可於利用烤箱進行烘烤之後，於減壓腔室內進一步進行烘烤。減壓腔室內之烘烤與烤箱中之烘烤相同，以100℃以上且260℃以下之溫度進行。
蝕刻步驟(S6)係利用乾式蝕刻將密封樹脂層5之一部分去除之步驟。乾式蝕刻例如於供給有包含氬及氮之至少一種元素之氣體之環境下進行。再者，上述氣體亦可包含氧及氫之至少一種元素。於蝕刻步驟(S6)中，較佳為將密封樹脂層5之一部分例如自密封樹脂層5之表面去除至1.0nm以上且100nm以下之深度為止。於未達1.0nm之情形時，存在無法充分提高密封樹脂層5與導電性屏蔽層7之密接性之情況。於超過100nm之情形時，由於蝕刻時間為長時間，故而製程時間較長。所去除之密封樹脂層5之深度例如可藉由調整蝕刻時間或所供給之氣體之流量等蝕刻條件來控制。又，亦可藉由蝕刻步驟(S6)使無機填充材料之一部分露出。
作為乾式蝕刻，亦可使用反向濺射而將密封樹脂層5之一部分去除。所謂反向濺射係指施加電壓而產生電漿，使所供給之氣體之離子碰撞於被處理體而將被處理體表面之氧化物等物質以離子形式撞飛之處理。
藉由進行蝕刻，能夠提高密封樹脂層5與導電性屏蔽層7之密接性。可認為其原因在於由密封樹脂層5之表面積之增大、或所露出之無機填充材料之微細之凹凸所致之固定效應等。
屏蔽層形成步驟(S7)係以與密封樹脂層5之表面相接之方式形成金屬化合物層6，且以覆蓋密封樹脂層5之方式形成導電性屏蔽層7之步驟。於屏蔽層形成步驟(S7)中，將已單片化之半導體裝置10配置於 托盤上。托盤例如包含鋁、銅、鐵、鎳、鉻、鈦等金屬、上述金屬之合金、不鏽鋼、複合材料、樹脂等。再者，例如亦可使用具有樹脂層與設置於樹脂層上之金屬層之積層構造之托盤。亦可使用具有黏著性之樹脂膜等來代替托盤。
於屏蔽層形成步驟(S7)中，例如以與密封樹脂層5之表面相接之方式形成金屬化合物部6a，於金屬化合物部6a上形成金屬化合物部6b，以隔著金屬化合物部6a及金屬化合物部6b而覆蓋密封樹脂層5之方式形成導電性屏蔽層7。例如，藉由利用濺鍍依序形成金屬化合物部6a、金屬化合物部6b、及導電性屏蔽層7，而可在不使被處理基板曝露於大氣下進行連續處理。亦可利用一體之裝置連續地進行上述熱處理步驟(S5)、蝕刻步驟(S6)、及屏蔽層形成步驟(S7)。
除濺鍍以外還能夠使用例如蒸鍍法、離子鍍覆法、轉印法、網版印刷法、噴霧塗佈法、噴射點膠法、噴墨法、氣溶膠法等形成金屬化合物部6a、金屬化合物部6b、及導電性屏蔽層7。
於蝕刻步驟(S6)中，亦可將氮氣供給至處理室而於包含氮之環境下進行乾式蝕刻，然後，於屏蔽層形成步驟(S7)中，形成導電性屏蔽層7。再者，亦可於氬與氮之混合環境下進行乾式蝕刻。又，上述環境亦可包含氧及氫之至少一種元素。
若於包含氮之環境下進行乾式蝕刻，則於密封樹脂層5之表面存在氮。若於存在氮之密封樹脂層5之表面上形成導電性屏蔽層7，則導電性屏蔽層7中所包含之金屬與氮反應而產生金屬氮化物。因此，不另外設置形成金屬化合物部6b之步驟即可形成包含金屬氮化物之金屬化合物部6b。因此，能夠簡化製造步驟。根據上述製造方法，例如能夠製造圖3所示之金屬化合物層6不設置於配線基板1之側面，而導電性屏蔽層7接於導電層12a及導電層13a之至少一導電層之側面之構造之半導體裝置1。
於形成密封樹脂層5之後於密封樹脂層5之表面存在樹脂成分之碳。若於存在碳之密封樹脂層5之表面上形成導電性屏蔽層7，則導電性屏蔽層7中所包含之金屬與碳反應而產生金屬碳化物。因此，不另外設置形成金屬化合物部6a之步驟即可形成包含金屬碳化物之金屬化合物部6a。有於蝕刻環境中樹脂表面之碳活化而金屬化合物層6成為金屬碳化物與金屬氮化物之混合層之情況。
於進行基板準備步驟(S1)至屏蔽層形成步驟(S7)之後，設置與導電層13a電性連接之外部連接端子2a，並設置與導電層13b電性連接之外部連接端子2b。並不限定於此，例如亦可於元件搭載步驟(S2)中設置外部連接端子2a、2b。進而，亦可設置藉由使用所製作之半導體裝置之外部連接端子2a、2b測定電阻值而檢查是否為良品等之步驟。以上為本實施形態中之半導體裝置之製造方法例之說明。
上述實施形態係作為示例而提出者，並不意圖限定發明之範圍。該等新穎之實施形態能夠以其他各種形態實施，於不脫離發明之主旨之範圍內能夠進行各種省略、替換、變更。該等實施形態或其變化包含於發明之範圍或主旨中，並且包含於申請專利範圍所記載之發明與其均等之範圍中。
【實施例】
(實施例1)
針對每一樣品改變蝕刻步驟(S6)中之蝕刻條件而製作樣品1至樣品3之半導體裝置。將各樣品之蝕刻條件示於表1。於樣品1之製作中，於使用Ar氣體與N2氣體之兩者之氣體進行蝕刻之後形成導電性屏蔽層。於樣品2之製作中，於僅使用Ar氣體進行蝕刻之後形成導電性屏蔽層。於樣品3之製作中，不進行蝕刻而形成導電性屏蔽層。於樣品1至樣品3中，導電性屏蔽層具有不鏽鋼層(SUS)與設置於不鏽鋼層上之銅層(Cu)之積層構造。不鏽鋼層(SUS)之厚度為0.1μm。銅層(Cu) 之厚度為3μm。進而，於樣品1至樣品3之製作中，於導電性屏蔽層上形成厚度為0.3μm之不鏽鋼層。
對所製作之樣品進行利用交叉切割法之密接性試驗。將藉由密接性試驗而剝離之樣品之個數比例(剝離率(%))示於表1。
如表1所示，於使用Ar氣體及N2氣體之兩者進行蝕刻而製作之樣品1中，剝離率為0%。相對於此，於僅使用Ar氣體進行蝕刻而製作之樣品2或不進行蝕刻而製作之樣品3中，產生導電性屏蔽層之剝離。
(實施例2)
藉由於包含無機填充材料之樹脂層上形成厚度10nm之不鏽鋼層，而製作樣品A、樣品B、及樣品C。於樣品A之製作中，供給Ar氣體及N2氣體之兩者而進行樹脂層之蝕刻。於樣品B之製作中，僅供給Ar氣體而進行樹脂層之蝕刻。於樣品C之製作中不進行樹脂層之蝕刻。樣品A之製作中之蝕刻步驟之Ar氣體流量及N2氣體流量如表2所示，與實施例1之樣品1之製作中之蝕刻步驟之Ar氣體流量及N2氣體流量相同。樣品B之製作中之蝕刻步驟之Ar氣體流量如表2所示，與實施例1之樣品2之製作中之蝕刻步驟之Ar氣體流量相同。
對所製作之樣品利用使用XPS(X-ray Photoelectron Spectroscopy(X射線光電子光譜學)：XPS)之深度方向分析，確認樹脂層與不鏽鋼層之間之金屬碳化物及金屬氮化物之有無。將結果示於表2。
【表2】
如表2所示，樣品A包含金屬碳化物與金屬氮化物。相對於此，樣品B及樣品C均不包含金屬氮化物。根據該情況可知，藉由於使用Ar氣體及N2氣體之兩者進行蝕刻之後形成導電性屏蔽層，而形成包含金屬碳化物與金屬氮化物之金屬化合物層。
根據實施例1及實施例2可知，藉由形成包含金屬氮化物之金屬化合物層，能夠提高密封樹脂層與導電性屏蔽層之密接性。

Claims (5)

  1. 一種半導體裝置，其具備：配線基板，其具有包含第1面與第2面之基體及接地配線；半導體晶片，其搭載於上述第1面上；外部連接端子，其設置於上述第2面上，且包含與上述接地配線電性連接之接地端子；密封樹脂層，其將上述半導體晶片密封；金屬化合物層，其與上述密封樹脂層之表面相接，且包含金屬氮化物；及導電性屏蔽層，以隔著上述金屬化合物層而覆蓋上述密封樹脂層之方式設置；上述接地配線於上述配線基板之側面露出，且與上述導電性屏蔽層電性連接。
  2. 如請求項1之半導體裝置，其中，上述金屬化合物層具有：第1金屬化合物部，其與上述密封樹脂層之表面相接，且包含金屬碳化物；及第2金屬化合物部，其設置於上述第1金屬化合物部與上述導電性屏蔽層之間，且包含上述金屬氮化物。
  3. 如請求項1或2之半導體裝置，其進而具備設置於上述導電性屏蔽層上之保護層，且上述導電性屏蔽層具有：第1金屬層，其隔著上述金屬化合物層而覆蓋上述密封樹脂層；及第2金屬層，其設置於上述第1金屬層上，且電阻率較上述第1金屬層更低。
  4. 一種半導體裝置之製造方法，其具備如下步驟：將半導體晶片搭載於配線基板之第1面上，上述配線基板具有包含上述第1面與第2面之基體及接地配線；以將上述半導體晶片密封之方式形成密封樹脂層；使上述接地配線於上述配線基板之側面露出；以與上述密封樹脂層之表面相接之方式，形成含有金屬氮化物之金屬化合物層；以與上述接地配線電性連接，且隔著上述金屬化合物層而覆蓋上述密封樹脂層之方式形成導電性屏蔽層；及將包含與上述接地配線電性連接之接地端子之外部連接端子形成於上述第2面上。
  5. 一種半導體裝置之製造方法，其具備如下步驟：將半導體晶片搭載於配線基板之第1面上，上述配線基板具有包含上述第1面與第2面之基體及接地配線；以將上述半導體晶片密封之方式形成密封樹脂層；使上述接地配線於上述配線基板之側面露出；利用包含氮之環境下之乾式蝕刻將上述密封樹脂層之一部分去除；以與上述接地配線電性連接，且覆蓋上述密封樹脂層之方式形成導電性屏蔽層，並且於上述密封樹脂層與上述導電性屏蔽層之間形成含有金屬氮化物之金屬化合物層；及將包含與上述接地配線電性連接之接地端子之外部連接端子形成於上述第2面上。
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