CN110010582B - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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CN110010582B
CN110010582B CN201811610366.5A CN201811610366A CN110010582B CN 110010582 B CN110010582 B CN 110010582B CN 201811610366 A CN201811610366 A CN 201811610366A CN 110010582 B CN110010582 B CN 110010582B
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layer
metal compound
semiconductor device
metal
sealing resin
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CN110010582A (zh
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本间庄一
高野勇佑
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Kioxia Corp
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Kioxia Corp
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Abstract

本发明的实施方式提供能够提高导电性屏蔽层与密封树脂层的密接性的半导体装置及其制造方法。实施方式的半导体装置具备：配线衬底，具有包含第1面与第2面的基体及接地配线；半导体芯片，搭载在第1面上；外部连接端子，设置在第2面上，且包含与接地配线电性连接的接地端子；密封树脂层，将半导体芯片密封；金属化合物层，接触于密封树脂层的表面，且包含金属氮化物；以及导电性屏蔽层，以隔着金属化合物层而覆盖密封树脂层的方式设置。接地配线在配线衬底的侧面露出，且与导电性屏蔽层电性连接。

Description

半导体装置及其制造方法
分案申请的相关信息
本案是分案申请。该分案的母案是申请日为2016年4月6日、申请号为201610208262.6、发明名称为“半导体装置及其制造方法”的发明专利申请案。
[相关申请案]
本申请案享有以日本专利申请案2015-152646号(申请日：2015年7月31日)为基础申请案的优先权。本申请案通过参照该基础申请案而包含基础申请案的全部内容。
技术领域
本发明的实施方式涉及一种半导体装置及其制造方法。
背景技术
在使用于通讯设备等的半导体装置中，为了抑制EMI(Electro MagneticInterference，电磁干扰)等电磁波故障，而使用将密封树脂层的表面以导电性屏蔽层覆盖的构造。为了利用所述构造获得充分的屏蔽效果，优选为将导电性屏蔽层与接地配线电性连接，而经由接地配线将电磁波干扰释放至外部。
为了使导电性屏蔽层与接地配线之间的电阻率较低，作为导电性屏蔽层的材料而例如使用铜等。然而，铜等的导电性屏蔽层容易从密封树脂层剥离。如此，如果导电性屏蔽层与密封树脂层的密接性较低那么存在半导体装置的可靠性降低的情况。
发明内容
本发明的实施方式提供一种导电性屏蔽层与密封树脂层的密接性较高的半导体装置及其制造方法。
实施方式的半导体装置具备：配线衬底，具有包含第1面与第2面的基体及接地配线；半导体芯片，搭载在第1面上；外部连接端子，设置在第2面上，且包含与接地配线电性连接的接地端子；密封树脂层，将半导体芯片密封；金属化合物层，接触于密封树脂层的表面，且包含金属氮化物；以及导电性屏蔽层，以隔着金属化合物层而覆盖密封树脂层的方式设置。接地配线在配线衬底的侧面露出，且与导电性屏蔽层电性连接。
附图说明
图1是表示半导体装置的构造例的剖面示意图。
图2是表示半导体装置的构造例的立体示意图。
图3是表示半导体装置的其他构造例的剖面示意图。
图4是表示半导体装置的其他构造例的剖面示意图。
图5是表示半导体装置的其他构造例的剖面示意图。
图6是表示半导体装置的其他构造例的剖面示意图。
图7是表示半导体装置的制造方法例的流程图。
图8是用来说明半导体装置的制造方法例的剖面示意图。
图9是用来说明半导体装置的制造方法例的剖面示意图。
具体实施方式
以下，参照附图对实施方式进行说明。附图中所记载的各构成要素的厚度与平面尺寸的关系、各构成要素的厚度的比率等存在与现实不同的情况。另外，在实施方式中，对实质上相同的构成要素标注相同的符号并适当省略说明。
图1是表示半导体装置的构造例的剖面示意图。图2是表示半导体装置的构造例的立体示意图。半导体装置10具备配线衬底1、外部连接端子2a、2b、半导体芯片3A、接合线4、密封树脂层5、金属化合物层6、以及导电性屏蔽层7。
配线衬底1具有：绝缘基体11，具有第1面与第2面；导电层12a，设置在第1面上；导电层12b，设置在第1面上；导电层13a，设置在第2面上，且经由通孔14a而与导电层12a电性连接；导电层13b，设置在第2面上，且经由通孔14b而与导电层12b电性连接；阻焊剂等绝缘层15，具有使导电层12a的一部分露出的开口部；以及阻焊剂等绝缘层16，具有使导电层13a的一部分及导电层13b的一部分露出的开口部。配线衬底1也可具有与半导体芯片3A的至少一部分重叠的导电层。与半导体芯片3A的至少一部分重叠的导电层与通孔14a电性连接，且与通孔14b电性分离。通过设置所述导电层，能够抑制经由配线衬底1的多余的电磁波的泄漏。
作为配线衬底1的绝缘基体11，例如能够使用硅衬底或玻璃衬底、陶瓷衬底、玻璃环氧树脂等树脂衬底等。导电层12a、导电层12b、导电层13a、及导电层13b的至少一者使用例如以铜或银为主成分的金属膜或包含铜或银的导电性膏，也可根据需要对表面实施镀镍或镀金等。通孔14a及通孔14b例如具有：导体层，设置在贯通绝缘基体11的开口的内表面；以及填孔材料，填充在导体层的内侧。导体层例如使用铜或银或包含这些的导电性膏，也可根据需要而对表面实施镀镍或镀金等。填孔材料使用例如绝缘性材料或导电性材料而形成。导体层并不限定于此，例如也可通过在贯通孔内壁利用镀敷等被覆金属材料(铜等)而形成通孔14a及通孔14b。
外部连接端子2a设置在导电层13a上，且与导电层13a电性连接。外部连接端子2a具有作为接地端子的功能。此时，导电层12a、导电层13a、及通孔14a具有作为接地配线的功能。外部连接端子2b设置在导电层13b上，且与导电层13b电性连接。外部连接端子2b具有作为信号端子或电源端子的功能。此时，导电层12b、导电层13b、及通孔14b具有作为信号配线或电源配线的功能。外部连接端子2a及外部连接端子2b例如具有焊料球。并不限定于此，外部连接端子2a及外部连接端子2b也可具有焊盘代替焊料球。
半导体芯片3A隔着芯片粘接膜等有机粘接层而搭载在第1面上。半导体芯片3A具有电极，且以使电极露出的方式积层为多级。积层为多级的半导体芯片3A经由芯片粘接膜等有机粘接层而依次粘接。积层为多级的半导体芯片3A的电极通过接合线4而与配线衬底1电性连接。半导体芯片3A经由接合线4而与导电层12a电性连接。作为接合线4，例如可列举金导线、银导线、铜导线等。铜导线的表面也可被钯膜覆盖。
密封树脂层5以将半导体芯片3A密封的方式设置。密封树脂层5含有SiO2等无机填充材料。另外，无机填充材料除包含SiO2以外，也可包含例如氢氧化铝、碳酸钙、氧化铝、氮化硼、氧化钛、或钛酸钡等。无机填充材料例如为粒状，具有调整密封树脂层5的粘度或硬度等的功能。密封树脂层5中的无机填充材料的含量例如为60％以上且90％以下。作为密封树脂层5，例如能够使用无机填充材料与绝缘性的有机树脂材料的混合物。作为有机树脂材料，例如可列举环氧树脂。此外，无机填充材料也可在密封树脂层5的表面露出。
金属化合物层6以与密封树脂层5的表面接触的方式设置。在图1中，金属化合物层6具有：金属化合物部6a，与密封树脂层5的表面接触且包含金属碳化物；以及金属化合物部6b，设置在金属化合物部6a上且包含金属氮化物。金属化合物部6b设置在金属化合物部6a与导电性屏蔽层7之间。在无机填充材料在密封树脂层5的表面露出的情况下，金属化合物层6与露出的无机填充材料接触。由此，能够提高密封树脂层5与导电性屏蔽层7的密接性。金属化合物层6也可不必为连续膜。例如，也可将相互隔开的多个金属化合物部视为金属化合物层6。
金属化合物部6a的厚度例如优选为0.1nm以上且100nm以下。在未达0.1nm的情况下，存在密封树脂层5与导电性屏蔽层7的密接性降低的情况。在超过100nm的情况下，存在金属化合物部6a的电阻率变高，而屏蔽效果降低的情况。金属化合物部6b的厚度例如优选为0.1nm以上且100nm以下。在未达0.1nm的情况下，存在密封树脂层5与导电性屏蔽层7的密接性降低的情况。在超过100nm的情况下，存在金属化合物部6b的电阻率变高，而屏蔽效果降低的情况。
作为金属碳化物，例如可列举镍的碳化物、钛的碳化物、铁的碳化物、铬的碳化物、铜的碳化物、钽的碳化物、铝的碳化物、或不锈钢(SUS304、SUS316等)的碳化物等。作为金属氮化物，例如可列举镍的氮化物、钛的氮化物、铁的氮化物、铬的氮化物、铜的氮化物、钽的氮化物、铝的氮化物、或不锈钢(SUS304、SUS316等)的氮化物等。此外，金属化合物层6也可不必包含金属碳化物。
金属化合物层6覆盖配线衬底1的侧面的至少一部分。此时，也可使接地配线的至少一部分的侧面，例如使导电层12a及导电层13a的至少一导电层的侧面在配线衬底1的侧面露出，而使所述至少一导电层的侧面接触于金属化合物层6。由此，能够经由外部连接端子2a而使多余的电磁波释放至外部。所述至少一导电层与金属化合物层6的接触部也可设置多个。
导电性屏蔽层7以隔着金属化合物层6覆盖密封树脂层5的方式设置。导电性屏蔽层7例如优选为包含铜、镍、钛、金、银、钯、铂、铁、铝、锡或铬等金属、所述金属的合金、不锈钢、或铟锡氧化物(Indium Tin Oxide：ITO)等。导电性屏蔽层7也可具有所述材料的复合层或积层。
导电性屏蔽层7的厚度优选为根据其电阻率而设定。例如，优选为以将导电性屏蔽层7的电阻率除以厚度所得的薄片电阻值成为0.5Ω以下的方式，设定导电性屏蔽层7的厚度。通过将导电性屏蔽层7的薄片电阻值设为0.5Ω以下，能够再现性良好地抑制来自密封树脂层5的多余的电磁波的泄漏。导电性屏蔽层7的厚度例如优选为0.1μm以上且20μm以下。在未达0.1μm的情况下，存在屏蔽效果降低的情况。在超过20μm的情况下，存在导电性屏蔽层7的应力较大而导电性屏蔽层7剥离的情况。
导电性屏蔽层7具有将从半导体芯片3A等辐射的多余的电磁波屏蔽而抑制向外部泄漏的功能。也可将金属化合物层6视为导电性屏蔽层的一部分。
导电性屏蔽层7也可覆盖配线衬底1的侧面的至少一部分。此时，导电性屏蔽层7与接地配线的至少一部分，例如与导电层12a及导电层13a的至少一导电层电性连接。例如，也可使导电层12a及导电层13a的至少一导电层的侧面在配线衬底1的侧面露出，而使导电性屏蔽层7与所述至少一导电层的侧面接触。所述至少一导电层与导电性屏蔽层7接触，由此能够经由外部连接端子2a而向外部释放多余的电磁波。所述至少一导电层与导电性屏蔽层7的接触部也可设置多个。通孔14a也可具有在配线衬底1的侧面露出而与导电性屏蔽层7接触的切断面。由于通过设置所述切断面，能够增加通孔14a与导电性屏蔽层7的接触面积，所以能够降低连接电阻。
在半导体装置10中，来自厚度方向的电磁波干扰较来自厚度方向的垂直方向的电磁波干扰产生得更多。因此，在导电性屏蔽层7中，优选为密封树脂层5的上表面上的区域厚于密封树脂层5的侧面上的区域。
本实施方式的半导体装置在密封树脂层与导电性屏蔽层之间具备包含金属碳化物与金属氮化物的金属化合物层。利用金属化合物层能够提高密封树脂层与导电性屏蔽层的密接性。认为其原因在于，金属氮化物中的金属原子或氮原子与密封树脂层中的无机填充材料或树脂结合。
本实施方式的半导体装置并不限定于图1所示的构造。图3是表示半导体装置的其他构造例的剖面示意图。图3所示的半导体装置10与图1所示的半导体装置10比较，金属化合物层6不设置在配线衬底1的侧面，且导电性屏蔽层7与导电层12a及导电层13a的至少一导电层的侧面接触的构成不同。由此，能够经由外部连接端子2a而将多余的电磁波向外部释放。所述至少一导电层与导电性屏蔽层7的接触部也可设置多个。导电性屏蔽层7也可延伸至基体11的第2面上为止。
图4是表示半导体装置的其他构造例的剖面示意图。图4所示的半导体装置10与图1所示的半导体装置10比较，金属化合物层6由包含金属碳化物及金属氮化物的两者的混合层形成的构成不同。此时，金属化合物层6的厚度例如优选为0.1nm以上且100nm以下。在未达0.1nm的情况下，存在密封树脂层5与导电性屏蔽层7的密接性降低的情况。在超过100nm的情况下，存在金属化合物层6的电阻率变高而屏蔽效果降低的情况。
图5是表示半导体装置的其他构造例的剖面示意图。图5所示的半导体装置10与图1所示的半导体装置10比较，还具备具有金属层7a与金属层7b的导电性屏蔽层7与设置在导电性屏蔽层7上的保护层8的构成不同。并不限定于图5，也可不设置金属层7b而半导体装置10具备设置在金属层7a上的保护层8。
金属层7a具有作为缓冲层(基底层)的功能。金属层7a例如包含钛、铬、镍、钼、钽或铁等金属、所述金属的合金、不锈钢、或ITO等。金属层7a也可具有所述材料的复合膜或积层膜。优选为金属层7a与金属化合物层6的密接性较金属层7b与金属化合物层6的密接性更高。金属层7a的厚度例如优选为0.01μm以上且20μm以下。在未达0.01μm的情况下，密封树脂层5与导电性屏蔽层7的密接性降低。在超过20μm的情况下，存在金属层7a的应力较大而金属层7a剥离的情况。
优选为金属层7b的电阻率较金属层7a的电阻率低。金属层7b例如包含铜、银、金、钯、或铂等金属。金属层7b的厚度例如优选为0.1μm以上且20μm以下。在未达0.1μm的情况下，存在屏蔽效果降低的情况。在超过20μm的情况下，存在金属层7b的应力较大而金属层7b剥离的情况。
保护层8耐蚀性及耐迁移性优异，例如具有提高导电性屏蔽层7的防潮性而抑制导电性屏蔽层7的腐蚀的功能。作为保护层8，例如使用金属材料、树脂材料、陶瓷材料等。保护层8例如包含钛、铬、镍、铁、铝、钼、钽、锰、镧或铜等金属、或不锈钢、所述金属的氧化物、所述金属的氮化物、ITO、碳、石墨、类金刚石碳、ZrB、MoS、TiON、TiAlN、环氧树脂、聚酰亚胺树脂、丙烯酸树脂、硅酮树脂、聚酰胺树脂等。保护层8的厚度例如优选为0.01μm以上且20μm以下。在未达0.01μm的情况下，存在抑制导电性屏蔽层7的腐蚀的效果降低的情况。在超过20μm的情况下，存在保护层8的应力较大而金属层7b剥离的情况。另外，成本也变高。
图6是表示半导体装置的其他构造例的剖面示意图。图6所示的半导体装置10与图1所示的半导体装置10比较，具备半导体芯片3B代替半导体芯片3A，且不具备接合线4的构成不同。半导体芯片3B具有与导电层12b电性连接的凸块31。凸块31例如包含金、锡、铅、银、铜、铋、及锌的至少一种金属、或所述金属的合金等。凸块31也可为复合膜或积层膜。
半导体芯片3B例如是通过对形成有凸块31的衬底切割使之单片化而形成。半导体芯片3B利用倒装芯片安装而搭载在配线衬底1上。此时，也可进行助焊剂的涂布或预处理等。在使用助焊剂的情况下，利用溶剂或纯水等将配线衬底1洗净。另外，图6所示的半导体装置10在配线衬底1与半导体芯片3B之间具备底部填充胶树脂等树脂层32。半导体芯片3B也可隔着凸块而积层。另外，具备贯通电极的半导体芯片3B也可隔着凸块而积层。
在图1、图3至图6所示的半导体装置10中，较不设置导电性屏蔽层7的半导体装置更能够减少电磁波干扰的量。另外，在图1、图3至图6所示的半导体装置中，例如在-55℃～150℃的热循环试验(Temperature Cycling Test：TCT)中，即便经过2000个循环之后也难以产生导电性屏蔽层7的异常、半导体芯片的连接不良等。另外，例如在150℃、1000小时的高温保存试验或85℃、湿度85％、偏压电压3.2V、1000小时的高温高湿偏压试验中，难以产生例如导电性屏蔽层7的腐蚀、半导体芯片的连接不良等。
其次，参照图7至图9对本实施方式的半导体装置的制造方法例进行说明。图7是表示图1所示的半导体装置10的制造方法例的流程图。图7所示的半导体装置的制造方法例具备衬底准备步骤(S1)、元件搭载步骤(S2)、树脂密封步骤(S3)、分离步骤(S4)、热处理步骤(S5)、蚀刻步骤(S6)、以及屏蔽层形成步骤(S7)。此外，本实施方式中的半导体装置的制造方法例的步骤内容及步骤顺序未必限定为图7所示的步骤。
图8及图9是用来说明半导体装置10的制造方法例的剖面示意图。在图8中，示意性地图示进行衬底准备步骤(S1)至分离步骤(S4)之后的半导体装置。在图9中，示意性地图示进行衬底准备步骤(S1)至屏蔽层形成步骤(S7)之后的半导体装置。
衬底准备步骤(S1)是准备配线衬底1的步骤。此处，作为一例而制作多个配线衬底1矩阵状地连设的构造的集合衬底。在衬底准备步骤(S1)中，于在分离步骤(S4)中切割的部位预先形成导电层12a及导电层13a。另外，在配线衬底1上预先贴附片状或膏状的芯片粘接膜。也可利用切割、激光、由拉伸所致的生生断开等而将芯片粘接膜切断。
元件搭载步骤(S2)是在配线衬底1的第1面上搭载半导体芯片3A的步骤。在元件搭载步骤(S2)中，一面使半导体芯片3A的电极露出一面使半导体芯片3A隔着芯片粘接膜而积层为多级。另外，在元件搭载步骤(S2)中，也可进行将半导体芯片3A彼此及半导体芯片3A与导电层12b经由接合线4而电性连接的接合。
在元件搭载步骤(S2)中，也可在搭载半导体芯片3A之后进行加热处理。在所述加热处理中，通过将配线衬底1放入至烤箱进行加热，能够使配线衬底1与半导体芯片3A粘接而使半导体芯片3A彼此粘接。然后，也可进行等离子体洗净而使半导体芯片3A的电极表面清洁化。例如，也可使用氩、氧、氢、或氩及氢的两者进行等离子体处理。也可在接合之后进行所述等离子体处理。
树脂密封步骤(S3)是以将半导体芯片3A密封的方式形成密封树脂层5的步骤。作为密封树脂层5的形成方法，例如可列举使用无机填充材料与有机树脂等的混合物的转注模塑法、压缩模塑法、注射模塑法、片状模塑法、或树脂点胶法等。
分离步骤(S4)是针对每一半导体装置10进行衬底的切割而分离为各个半导体装置10的步骤。例如，使用金刚石刀等刀进行切割。也可在切割时将导电层12a等具有作为接地配线的功能的导电层切断而使所述导电层在配线衬底1的侧面露出。在分离步骤(S4)后，例如也可利用具备YAG(Yttrium Aluminum Garnet，钇-铝-石榴石)激光等的激光标记装置，在密封树脂层5的上表面刻印产品名、产品编号、生产年份星期、生产工厂等产品信息。
在热处理步骤(S5)中，将已单片化的半导体装置放入至烤箱，以100℃以上且260℃以下的温度进行加热而将被半导体装置10吸湿的水分等去除。在未达100℃的情况下，水分未被去除而导致密封树脂层5与导电性屏蔽层7的密接性降低。在超过260℃的情况下，由于加热温度较回流焊温度高，所以存在对半导体装置10带来损伤的情况。也可将去除所述水分等的步骤称为脱气步骤。热处理步骤(S5)也可具有多个热处理步骤。例如，也可在利用烤箱进行烘烤之后，在减压腔室内进一步进行烘烤。减压腔室内的烘烤与烤箱中的烘烤相同，以100℃以上且260℃以下的温度进行。
蚀刻步骤(S6)是利用干式蚀刻将密封树脂层5的一部分去除的步骤。干式蚀刻例如在供给有包含氩及氮的至少一种元素的气体的环境下进行。此外，所述气体也可包含氧及氢的至少一种元素。在蚀刻步骤(S6)中，优选为将密封树脂层5的一部分例如从密封树脂层5的表面去除至1.0nm以上且100nm以下的深度为止。在未达1.0nm的情况下，存在无法充分提高密封树脂层5与导电性屏蔽层7的密接性的情况。在超过100nm的情况下，由于蚀刻时间为长时间，所以制程时间较长。所去除的密封树脂层5的深度例如通过调整蚀刻时间或所供给的气体的流量等蚀刻条件来控制。另外，也可通过蚀刻步骤(S6)使无机填充材料的一部分露出。
作为干式蚀刻，也可使用反向溅射而将密封树脂层5的一部分去除。所谓反向溅射是指施加电压而产生等离子体，使所供给的气体的离子碰撞于被处理体而将被处理体表面的氧化物等物质以离子形式撞飞的处理。
通过进行蚀刻，能够提高密封树脂层5与导电性屏蔽层7的密接性。可认为其原因在于由密封树脂层5的表面积的增大、或所露出的无机填充材料的微细的凹凸所致的固定效应等。
屏蔽层形成步骤(S7)是以与密封树脂层5的表面接触的方式形成金属化合物层6，且以覆盖密封树脂层5的方式形成导电性屏蔽层7的步骤。在屏蔽层形成步骤(S7)中，将已单片化的半导体装置10配置在托盘上。托盘例如包含铝、铜、铁、镍、铬、钛等金属、所述金属的合金、不锈钢、复合材料、树脂等。此外，例如也可使用具有树脂层与设置在树脂层上的金属层的积层构造的托盘。也可使用具有粘着性的树脂膜等来代替托盘。
在屏蔽层形成步骤(S7)中，例如以与密封树脂层5的表面接触的方式形成金属化合物部6a，在金属化合物部6a上形成金属化合物部6b，以隔着金属化合物部6a及金属化合物部6b而覆盖密封树脂层5的方式形成导电性屏蔽层7。例如，通过利用溅镀依序形成金属化合物部6a、金属化合物部6b、及导电性屏蔽层7，而不使被处理衬底曝露于大气即可进行连续处理。也可利用一体的装置连续地进行所述热处理步骤(S5)、蚀刻步骤(S6)、及屏蔽层形成步骤(S7)。
除溅镀以外还能够使用例如蒸镀法、离子镀覆法、转印法、网版印刷法、喷雾涂布法、喷射点胶法、喷墨法、气溶胶法等形成金属化合物部6a、金属化合物部6b、及导电性屏蔽层7。
在蚀刻步骤(S6)中，也可将氮气供给至处理室而在包含氮的环境下进行干式蚀刻，然后，在屏蔽层形成步骤(S7)中，形成导电性屏蔽层7。此外，也可在氩与氮的混合环境下进行干式蚀刻。另外，所述环境也可包含氧及氢的至少一种元素。
如果在包含氮的环境下进行干式蚀刻，那么在密封树脂层5的表面存在氮。如果在存在氮的密封树脂层5的表面上形成导电性屏蔽层7，那么导电性屏蔽层7中所包含的金属与氮反应而产生金属氮化物。因此，不另外设置形成金属化合物部6b的步骤即可形成包含金属氮化物的金属化合物部6b。因此，能够简化制造步骤。根据所述制造方法，例如能够制造图3所示的金属化合物层6不设置在配线衬底1的侧面，而导电性屏蔽层7接触于导电层12a及导电层13a的至少一导电层的侧面的构造的半导体装置1。
在形成密封树脂层5之后在密封树脂层5的表面存在树脂成分的碳。如果在存在碳的密封树脂层5的表面上形成导电性屏蔽层7，那么导电性屏蔽层7中所包含的金属与碳反应而产生金属碳化物。因此，不另外设置形成金属化合物部6a的步骤即可形成包含金属碳化物的金属化合物部6a。有在蚀刻环境中树脂表面的碳活化而金属化合物层6成为金属碳化物与金属氮化物的混合层的情况。
在进行衬底准备步骤(S1)至屏蔽层形成步骤(S7)之后，设置与导电层13a电性连接的外部连接端子2a，并设置与导电层13b电性连接的外部连接端子2b。并不限定于此，例如也可在元件搭载步骤(S2)中设置外部连接端子2a、2b。进而，也可设置通过使用所制作的半导体装置的外部连接端子2a、2b测定电阻值而检查是否为良品等的步骤。以上为本实施方式中的半导体装置的制造方法例的说明。
所述实施方式是作为示例而提出者，并不意图限定发明的范围。这些新颖的实施方式能够以其他各种方式实施，在不脱离发明的主旨的范围内能够进行各种省略、替换、变更。这些实施方式或其变形包含在发明的范围或主旨中，并且包含在权利要求书所记载的发明与其均等的范围中。
【实施例】
(实施例1)
针对每一样品改变蚀刻步骤(S6)中的蚀刻条件而制作样品1至样品3的半导体装置。将各样品的蚀刻条件示于表1。在样品1的制作中，在使用Ar气体与N2气体的两者的气体进行蚀刻之后形成导电性屏蔽层。在样品2的制作中，在仅使用Ar气体进行蚀刻之后形成导电性屏蔽层。在样品3的制作中，不进行蚀刻而形成导电性屏蔽层。在样品1至样品3中，导电性屏蔽层具有不锈钢层(SUS)与设置在不锈钢层上的铜层(Cu)的积层构造。不锈钢层(SUS)的厚度为0.1μm。铜层(Cu)的厚度为3μm。进而，在样品1至样品3的制作中，在导电性屏蔽层上形成厚度为0.3μm的不锈钢层。
对所制作的样品进行利用交叉切割法的密接性试验。将通过密接性试验而剥离的样品的个数比例(剥离率(％))示于表1。
【表1】
Figure BDA0001924600740000101
如表1所示，在使用Ar气体及N2气体的两者进行蚀刻而制作的样品1中，剥离率为0％。相对于此，在仅使用Ar气体进行蚀刻而制作的样品2或不进行蚀刻而制作的样品3中，产生导电性屏蔽层的剥离。
(实施例2)
通过在包含无机填充材料的树脂层上形成厚度10nm的不锈钢层，而制作样品A、样品B、及样品C。在样品A的制作中，供给Ar气体及N2气体的两者而进行树脂层的蚀刻。在样品B的制作中，仅供给Ar气体而进行树脂层的蚀刻。在样品C的制作中不进行树脂层的蚀刻。样品A的制作中的蚀刻步骤的Ar气体流量及N2气体流量如表2所示，与实施例1的样品1的制作中的蚀刻步骤的Ar气体流量及N2气体流量相同。样品B的制作中的蚀刻步骤的Ar气体流量如表2所示，与实施例1的样品2的制作中的蚀刻步骤的Ar气体流量相同。
对所制作的样品利用使用XPS(X-ray Photoelectron Spectroscopy(X射线光电子光谱学)：XPS)的深度方向分析，确认树脂层与不锈钢层之间的金属碳化物及金属氮化物的有无。将结果示于表2。
【表2】
气体 金属碳化物 金属氮化物
样品A Ar及N2 有 有
样品B 仅Ar 有 无
样品C - 有 无
如表2所示，样品A包含金属碳化物与金属氮化物。相对于此，样品B及样品C均不包含金属氮化物。根据该情况可知，通过在使用Ar气体及N2气体的两者进行蚀刻之后形成导电性屏蔽层，而形成包含金属碳化物与金属氮化物的金属化合物层。
根据实施例1及实施例2可知，通过形成包含金属氮化物的金属化合物层，能够提高密封树脂层与导电性屏蔽层的密接性。
[符号的说明]
1 配线衬底
2a 外部连接端子
2b 外部连接端子
3 半导体芯片
3A 半导体芯片
3B 半导体芯片
4 接合线
5 密封树脂层
6 金属化合物层
6a 金属化合物部
6b 金属化合物部
7 导电性屏蔽层
7a 金属层
7b 金属层
8 保护层
10 半导体装置
11 绝缘基体
12a 导电层
12b 导电层
13a 导电层
13b 导电层
14a 通孔
14b 通孔
15 绝缘层
16 绝缘层
31 凸块
32 树脂层

Claims (9)

1.一种半导体装置，其特征在于具备：
配线衬底，具有包含第1面与第2面的基体及接地配线；
半导体芯片，搭载在所述第1面上；
外部连接端子，设置在所述第2面上，且包含与所述接地配线电性连接的接地端子；
密封树脂层，将所述半导体芯片密封；
金属化合物层，设置在所述密封树脂层的表面，且混合有至少第1金属化合物与第2金属化合物的2个金属化合物；以及
导电性屏蔽层，以隔着所述金属化合物层而覆盖所述密封树脂层的方式设置；
所述接地配线在所述配线衬底的侧面露出，且与所述导电性屏蔽层电性连接；
所述金属化合物层的膜厚是0.1nm以上100nm以下。
2.根据权利要求1所述的半导体装置，其特征在于所述第1金属化合物是金属碳化物，所述第2金属化合物是金属氮化物。
3.根据权利要求1或2所述的半导体装置，其特征在于所述导电性屏蔽层的膜厚是0.01μm以上20μm以下。
4.一种半导体装置的制造方法，其特征在于具备如下步骤：
将半导体芯片搭载在配线衬底的第1面上，所述配线衬底具有包含所述第1面与第2面的基体及接地配线；
以将所述半导体芯片密封的方式形成密封树脂层；
使所述接地配线在所述配线衬底的侧面露出；
形成金属化合物层，所述金属化合物层设置在所述密封树脂层的表面，且混合有至少第1金属化合物与第2金属化合物的2个金属化合物；
以与所述接地配线电性连接，且隔着所述金属化合物层而覆盖所述密封树脂层的方式形成导电性屏蔽层；以及
将包含与所述接地配线电性连接的接地端子的外部连接端子形成在所述第2面上；
所述金属化合物层的膜厚是0.1nm以上100nm以下。
5.根据权利要求4所述的半导体装置的制造方法，其特征在于对所述密封树脂层进行干式蚀刻之后形成金属化合物层。
6.根据权利要求5所述的半导体装置的制造方法，其特征在于所述干式蚀刻是反向溅射。
7.根据权利要求6所述的半导体装置的制造方法，其特征在于所述反向溅射是以包含氮的气体进行。
8.根据权利要求4所述的半导体装置的制造方法，其特征在于所述第1金属化合物是金属碳化物，所述第2金属化合物是金属氮化物。
9.根据权利要求4至8中任一权利要求所述的半导体装置的制造方法，其特征在于所述金属化合物层是通过溅射而形成。
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Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10652996B2 (en) * 2015-12-21 2020-05-12 3M Innovative Properties Company Formable shielding film
JP2018160527A (ja) * 2017-03-22 2018-10-11 東芝メモリ株式会社 半導体パッケージ、及び、半導体パッケージのマーキング方法
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JP7407498B2 (ja) * 2017-09-15 2024-01-04 日東電工株式会社 配線回路基板およびその製造方法
US20190229064A1 (en) * 2018-01-24 2019-07-25 Powertech Technology Inc. Laser color marking method for a semiconductor package
WO2019159913A1 (ja) 2018-02-15 2019-08-22 株式会社村田製作所 高周波モジュール
CN108323144B (zh) * 2018-03-14 2020-07-28 广州方邦电子股份有限公司 电磁屏蔽膜、线路板及电磁屏蔽膜的制备方法
KR102487841B1 (ko) * 2018-03-14 2023-01-11 삼성전자주식회사 반도체 패키지
JP7074201B2 (ja) 2018-09-27 2022-05-24 株式会社村田製作所 モジュールおよびその製造方法
US11296037B2 (en) * 2019-04-01 2022-04-05 Samsung Electronics Co., Ltd. Semiconductor package
KR102662052B1 (ko) * 2019-07-26 2024-05-02 삼성전자 주식회사 Emi 차폐 부재 및 이를 포함하는 전자 장치
JP2021125525A (ja) * 2020-02-04 2021-08-30 キオクシア株式会社 半導体パッケージおよびその製造方法
JP2021150311A (ja) 2020-03-16 2021-09-27 キオクシア株式会社 半導体装置
JP2022118877A (ja) 2021-02-03 2022-08-16 キオクシア株式会社 半導体装置及び半導体装置の製造方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005109306A (ja) * 2003-10-01 2005-04-21 Matsushita Electric Ind Co Ltd 電子部品パッケージおよびその製造方法
EP1727201A1 (en) * 2005-05-27 2006-11-29 Hou, PonWei Shielding material for preventing outleakage and penetration of electromagnetic waves
JP2010016362A (ja) * 2008-06-06 2010-01-21 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法
CN102339817A (zh) * 2010-07-15 2012-02-01 株式会社东芝 半导体封装以及使用其的移动设备
CN104716053A (zh) * 2013-12-13 2015-06-17 株式会社东芝 半导体装置的制造方法及半导体装置

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58199543A (ja) * 1982-05-17 1983-11-19 Toshiba Corp 半導体装置のパツケ−ジ
JPH10261729A (ja) * 1997-03-17 1998-09-29 Nippon Telegr & Teleph Corp <Ntt> 半導体装置
JP4434778B2 (ja) * 2004-02-25 2010-03-17 Ｎｅｃエレクトロニクス株式会社 半導体装置
JP5408253B2 (ja) * 2009-06-17 2014-02-05 日本電気株式会社 Ｉｃパッケージ
CN102036541B (zh) * 2009-09-25 2014-02-19 鸿富锦精密工业（深圳）有限公司 电磁屏蔽膜及具有该电磁屏蔽膜的镜头模组
KR20110134200A (ko) * 2010-06-08 2011-12-14 삼성전기주식회사 전자기 밴드갭 구조물을 포함하는 ｅｍｉ 노이즈 차폐 기판
TW201226197A (en) * 2010-12-30 2012-07-01 Chenming Mold Ind Corp Plastic member and manufacturing method thereof
US8959757B2 (en) * 2011-12-29 2015-02-24 Rf Micro Devices, Inc. Method of manufacturing an electronic module
JP5779227B2 (ja) * 2013-03-22 2015-09-16 株式会社東芝 半導体装置の製造方法
JP5877814B2 (ja) * 2013-05-07 2016-03-08 株式会社半導体エネルギー研究所 半導体装置
JP5684349B1 (ja) * 2013-09-10 2015-03-11 株式会社東芝 半導体装置および半導体装置の検査方法
US9269673B1 (en) * 2014-10-22 2016-02-23 Advanced Semiconductor Engineering, Inc. Semiconductor device packages

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005109306A (ja) * 2003-10-01 2005-04-21 Matsushita Electric Ind Co Ltd 電子部品パッケージおよびその製造方法
EP1727201A1 (en) * 2005-05-27 2006-11-29 Hou, PonWei Shielding material for preventing outleakage and penetration of electromagnetic waves
JP2010016362A (ja) * 2008-06-06 2010-01-21 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法
CN102339817A (zh) * 2010-07-15 2012-02-01 株式会社东芝 半导体封装以及使用其的移动设备
CN104716053A (zh) * 2013-12-13 2015-06-17 株式会社东芝 半导体装置的制造方法及半导体装置

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