TWI224387B - Semiconductor package substrate with protective layer on pads formed thereon and method for fabricating the same - Google Patents

Abstract

A semiconductor package substrate with a protective layer on pads formed thereon and a method for fabricating the same are proposed. An insulating layer is formed with a plurality of blind vias to expose an inner trace structure underneath the insulating layer. After a conductive film is formed on the surface of the insulating layer and the blind vias, a first resist layer is formed thereon with a plurality of openings to expose the conductive film. A patterned trace structure including a plurality of pads is formed within the openings and conductive blind vias are formed within the blind vias of the insulating layer by an electroplating process, wherein at least a pad is electrically connected to the conductive blind via. A second resist layer is partially formed on the patterned trace structure and a barrier metal layer is partially formed on the pads without covering the second resist layer by an electroplating process. After the second resist layer, the first resist layer, and the conductive film underneath the resist layer are removed, a solder mask is formed over the substrate with a plurality of openings formed to expose the pads. An organic solderability preservative layer is formed on the pads without covering the barrier metal layer, for providing a semiconductor package substrate with pads covered by either a barrier metal layer or an organic solderability preservative layer.

Description

1224387 V. Description of the invention (l) [Technical field to which the invention belongs] The present invention relates to the structure of a semiconductor package substrate and its dream method, and more particularly to a circuit build-up structure formed on a semiconductor package substrate A barrier metal layer and an organic protective layer 2, a front structure, and a manufacturing method thereof are formed on the sexual connection pad. θ [Previous technology] In the trend of thin, short, versatile, high-speed, and high-frequency electronic products, the technology of printed circuit boards (p C Β) or IC packaging substrates has developed toward fine lines and small apertures. At present, the manufacturing process of printed circuit boards (PCB) or IC packaging substrates has been reduced from about 100 // m above the conventional circuit size: including line width, line spacing (S pace), and aspect ratio to about m. , And research and development towards smaller line accuracy. Compared with the traditional Stubstractive method, the current industry adopts the Additive method, which can make finer lines, in order to respond to higher-turnout circuit boards. Copper forms a seed layer on an insulating circuit board, and then directly forms a circuit layer on the insulating layer. This method can be further divided into a full-additive method and a semi-additive method. additive) method to avoid problems caused by the process of engraving the surname. The typical process of the semi-additive method that can be used to make thinner circuits is shown in Figures 1A to 1F. Please refer to FIG. 1A. First, a core circuit board 10 is provided. The core circuit board 10 includes a plurality of patterned circuit layers 11, an insulation layer 12 between the two circuit layers 11, and the circuit layer 1. 1 electrical connection plating

_Edit 1_1 17356 全懋 .ptd Page 7 1224387 V. Description of the invention (2) Vias 13. Please refer to FIG. 1B, and then provide two organic insulating layers 1 4 to be bonded to the surface of the core circuit board 10 by vacuum pressing. Please refer to FIG. 1C. Next, a plurality of openings 1 4 0 are patterned in the organic insulating layer 14, and the exposed part of the circuit layer 1 1 is formed, and a blank is formed on the surface of the organic insulating layer 14. Electroplated copper thin layer 1 5. Referring to FIG. 1D, a patterned resist layer 16 is formed on the electroless copper 15, and the resist layer 16 is formed with a large number of openings 16 except the exposed parts. Mine copper 15. Referring to FIG. 1E, a plating metal layer is formed in the resist layer opening 160 by electroplating. The plating metal layer is generally a conductive circuit layer 17 composed of metallic copper. Referring to FIG. 1F, after removing the resist layer 16 and the electroless copper thin layer 15 covered by the resist layer 16, a layered substrate 100 is completed. Among them, most of the conductive wirings made of copper are formed on the surface of the semiconductor package substrate, and most of them are electrically connected pads, which are used to transmit electronic signals or power sources. At the same time, the electrical connections A protective layer is generally formed on the exposed surface of the pad to effectively provide electrical coupling between the electrical connection pad and the conductive element (such as gold wire, bump or solder ball) and the chip or circuit board, and also avoid the influence of the external environment. As a result, the electrical connection pad body (metal copper) is oxidized. The type of the electrical connection pad may be, for example, a bump pad or a pre-solder pad (P res ο 1 derpad) for electrically coupling the semiconductor flip-chip package substrate and the wafer, or a wire-type semiconductor package substrate. With chip

17356 Quan 懋 .ptd Page 8 I224387 V. Description of the Invention (3) '— Electrically-coupled solder pad (F inger), and for example, a package substrate and a life-span-coupled solder ball pad (B a 1 1 pad) . By forming a protective layer on the surface of the electrical soil surface and biting the chrome body, it is possible to provide a + green connection pad (metal copper) coated in the protective layer, which is not easy to be oxidized by external environmental influences. In order to improve the quality of the electrical S connection, which is implanted on the electrical connection pads, such as blocks, pre-solders, solder balls or bonding wires, etc. / The protective layer formed by the general semiconductor industry on the electrical connection pads of the substrate includes: an organic protective layer (Such as organic solderability protective agent layer (0SP, alsoolderability preservative layer)) and barrier metal layer (such as nickel / gold metal layer). The reaction principle of the 2 # ^ organic solderability protective agent process is mainly based on the use of benzene: η (ΒθηZ〇—TF1—AZ〇, BTA) and other chemicals on the clean copper surface of the copper thin gland wool connection pad) A layer of protective organic matter in the form of a complex compound can not only produce a thin film with a thickness of about 0.35 micrometers, but also the protective organic film can be rusted to protect the copper surface (electrical connection pad) from the external environment. Solder balls or i-wires are intended to be used for conductive components such as bumps, pre-solders, and other materials, but dry, dry, and eloquence films can be quickly diluted by acid or flux, so that the copper surface can still show good Solderability. It belongs to J) barrier metal layer ~ usually made of noble metal materials (such as nickel / gold gold, car 1le / formed on the exposed surface of the electric flail pads, and is used to form the barrier metal of the electric flail Layer, due to the conventional semi-additive method (^) of the electroless copper thin layer commonly used by the two kings, it is finished in the line patterning process == removed by etching, and then the plated circuit layer is protected from external exposure '丨 Dyeing, that is, the process of forming a solder resist (green paint) on the substrate surface,

17356 全懋 .ptd Page 9 1224387 V. Description of the invention (4) The surface of the saturable connection pad is to be formed with a surface of the nickel / gold (Ni / Au) metal layer to expose the opening of the anti-deficient layer, because The copper layer used for electroplating has been removed. Therefore, it is necessary to use the electro-less method, that is, there is no driving force (D r 丨 v 丨 ngf 〇rce) to make recording / gold. A metal layer is formed on the electrical connection pad in the opening of the solder resist layer. Qing Cang read Figures 2A and 2B, which are schematic diagrams of the conventional technique of using electroless plating on the surface of an electrical connection pad of a package substrate, that is, a chemical nickel / gold process to form a nickel / gold metal layer. Please refer to Figure 2A. As mentioned earlier, in order to deposit the nickel / gold metal layer on the surface of the electrical connection pad correctly, a patterned circuit layer is formed after completing the required previous process. On the surface of the packaging substrate 100 of 7, there is a solder mask 18 (Solder ma sk) 18 like green paint by printing or coating, and the circuit layer I on the surface of the packaging substrate 100? It includes a plurality of electrical connection pads 170, and an opening 18 is formed at the electrical connection layer 180 at the solder resist layer 18 to expose the electrical connection pad 170 °. See also Figure 2B. During the chemical nickel / gold process, the substrate 100 is subjected to an electroless nickel immersion gold process (Electroless Nickel / Immersion G ο 1 d (EN / IG)), through the opening 1 of the solder resist layer 1 § 0, so that the recording / gold metal layer 19 is deposited on the surface of the electrical connection pad 170 where the opening of the anti-repellent agent layer 18 is exposed. Therefore, as mentioned earlier, since the keyless copper thin layer, which is commonly used to conduct current for plated patterned circuits in the SAP process, is removed after the circuit is completed,

17356 Quan Ye.ptd Page 10 1224387 V. Description of the invention

= The nickel-gold metal layer formed after the backing is formed by electroplating and Γ electroless ore method (such as chemical nickel / gold method), suitable for leather garments / ^ Also, the process window is narrow The production process is difficult to approve, and the production process is exhausted. In July, the chemical zinc used in the month of control (CoSt) is higher (the plating solution is more expensive), and even: the process liquid in the gold process will be formed on the seal.梦 暴 档 表面 的 歪 # 今 tp PeeUng year-old sexual assault, resulting in poor peeling of the solder resist layer. The reliability of the nickel / gold metal layer on the man-made connection pad is low. A I t ^ meets the market demand. The semiconductor package structure strives to be thin and short. ==, small size, high integration development. The semiconductor package substrate of the Jianjia i-chip carrier (chip carrier) is compared with the electrical connection pads of f, I-24, so that the crystals carried on the substrate say: S3 is a good and complete electrical Sexual connection, high accumulation of materials, said that the film pass works freely and fully exerts its functions and characteristics. However, if the precision of the wire is to be further advanced, the size area and adjacent pitch of the electrical flail pads on the substrate must also be reduced accordingly, resulting in the formation of the electrical connection pads. The openings of the solder resist layer are too small, & into the chemical nickel into the clothing, due to the poor convection of the liquid, the mass transfer of the nickelized particles is not good, and the phenomenon of full plating is difficult to make the subsequent chemical conversion impossible. Immersed onto the nickel metal layer smoothly, so the phenomenon of jump plating occurs, or the surface of the electrical connection pad is too rough to form a dense and dense nickel / gold metal layer, resulting in poor process reliability. question. Wang Ba μ [Contents of the Invention]

1224387 V. Description of the invention (6) In view of the shortcomings of the conventional technology described above, the main object of the present invention is to provide a semiconductor package substrate with an electrical connection pad protection layer and a manufacturing method thereof, which can simultaneously form The electrical connection pad of the barrier metal layer and the electrical connection pad with an organic solderability protection agent. Another object of the present invention is to provide a semiconductor package substrate with an electrical connection pad protection layer and a manufacturing method thereof, which can simultaneously integrate a semi-additive method to form a circuit structure method, and use electroplating and a chemical tank manufacturing process to form the electrical connection pad. Barrier metal layer and organic solderability protectant. Another object of the present invention is to provide a semiconductor package substrate with an electrical connection pad protective layer and a manufacturing method thereof, which avoids the narrow application range of the process caused by the conventional chemical nickel / gold process, the process precision control is not easy, and the process cost is high. Problems, and even the process liquid has a corrosive attack on the solder resist layer on the surface of the package substrate, which causes poor reliability issues such as peeling of the solder resist layer and contamination of the nickel / gold metal layer on the electrical connection pad. Yet another object of the present invention is to provide a semiconductor package substrate with an electrical connection pad protective layer and a method for manufacturing the same, which avoids poor liquid convection in the chemical nickel / gold process, which results in poor quality transmission of nickelized particles and is not easy to fill. The phenomenon of plating prevents subsequent metallization from being successfully immersed on the nickel metal layer, so that the phenomenon of jump plating or excessively roughening the surface of the electrical connection pad cannot form a dense nickel / gold metal layer. In order to achieve the above-mentioned object, the present invention provides a method for manufacturing a semiconductor package substrate with a protective layer of an electrical connection pad. The main manufacturing process includes: providing an insulating layer, and a plurality of blind holes are formed in the insulating layer to cover the exposed portion. Inner layer circuit under the insulating layer; a conductive layer is formed on the surface of the insulating layer and the blind hole

17356 Quan 懋 .ptd Page 12 1224387 V. Description of the invention (7) film; forming a first resistive layer on the conductive film, and forming the first resistive layer with a majority of the conductive film exposed outside of the opening; performing a plating process A patterned circuit layer is formed in the opening of the first resistance layer, and a conductive blind hole is formed in a blind hole in the insulating layer. The patterned circuit layer includes a plurality of electrical connection pads, and at least one electrical connection pad is electrically connected. To the conductive blind hole; forming a second resistive layer on a portion of the patterned circuit structure, and performing a plating process to form a barrier metal layer on a portion of the electrical connection pad not covered with the second resistive layer; Except for the second resist layer, the first resist layer, and the conductive film covering the first resist layer; a solder resist layer is formed on the surface of the package substrate, and a part of the electrical resist is exposed except for the opening formed in the solder resist layer. The barrier metal layer on the conductive connection pad and part of the electrical connection pad body; and an organic solderability protective agent layer is formed on the electrical connection pad whose surface is not covered with the barrier metal layer. In another embodiment, the method for manufacturing a semiconductor package substrate with an electrical connection pad protective layer according to the present invention includes the following steps: providing an insulating layer, and forming a plurality of blind holes in the insulating layer to cover the exposed portion. An inner layer circuit under the insulating layer; a conductive film is formed on the insulating layer and the surface of the blind hole; a first resistive layer is formed on the conductive film, and the first resistive layer is formed with a majority of the conductive film exposed outside the opening; electroplating In the manufacturing process, a plurality of electrical connection pads are formed in the opening of the first resistive layer and a conductive blind hole is formed in the blind hole of the insulating layer, and the electrical connection pad is electrically connected to the conductive blind hole; A second resistive layer is formed on the electrical connection pad, and a plating process is performed to form a barrier metal layer on the portion of the electrical connection pad not covered with the second resistive layer; the second resistive layer, the first resistive layer, and the A conductive film covered under the first resistive layer; a solder resist layer is formed on the surface of the package substrate, and the resist

17356 Quan 懋 .ptd Page 13 1224387 V. Description of the invention (8) The solder layer is formed with a barrier metal layer and a portion of the electrical connection pad body on the electrical connection pad exposed outside the opening; and the surface is not covered with resistance. An organic solderability protective agent layer is formed on the electrical connection pad of the barrier metal layer. Through the above process, the present invention provides a semiconductor package substrate with an electrical connection pad protection layer. The semiconductor package substrate mainly includes at least one insulating layer, and a plurality of conductive blind holes are formed in the insulating layer for electrical connection. To the inner layer circuit covered under the insulating layer; at least one patterned circuit layer is 'formed by a conductive film on the insulating layer by electro-mineral method', and the patterned circuit layer includes a plurality of electrical connection pads, At least one of the electrical connection pads is electrically connected to the conductive blind hole; a barrier metal layer that completely covers the upper surface of a portion of the electrical connection pads; a solder resist layer is formed on the surface of the package substrate, And the solder resist layer is formed with at least one barrier metal layer and part of the electrical connection pad body exposed on the electrical connection pad outside of at least one opening; and an organic solderability protective layer is formed on the solder resist layer. The hole is not covered by the electrical connection pad with the barrier metal layer. Because in the present invention, the semi-additive method is directly used in the production of patterned lines and conductive blind holes, the conductive film (electroless copper thin layer) required for electroplating is used, and a second resistance layer, such as a dry film (D ryfi 1 m), image transfer is performed to cover a part of the substrate, so as to form a barrier metal layer, such as a metal / gold metal layer, on the upper surface of the electrical connection pads of the part, by using electroplated nickel / Gold replaces the conventional chemical nickel / gold structure and method, thereby avoiding various process defects caused by the conventional chemical nickel / gold, and then covering the surface of the packaging substrate with a solder resist layer to protect the packaging substrate from Damaged by external environmental pollution, and formed a plurality of solder resist layers

17356 Quan 懋 .ptd Page 14 Wu Kai, description of the invention (9) Part of the electrical pad body is exposed outside the hole, forming an organic protective layer on the surface, and the layer and the organic protective layer have the above-mentioned conductive film. A part of the barrier metal layer is further added to cover the second resist layer to electrically perform the solder resist layer process. Formation of barrier metal layer process control, lower peeling of the agent layer on the surface of the packaging substrate and poor electrical connection problems, and avoiding poor fluidity, forming difficult to dip (I mmersed) on nickel connections塾 The surface is too rough. At the same time, an electrical connection pad with a protective layer can be integrated on the pad through the electrical connection pad in the repellent layer on the sink plate at the same time, and the property is connected to the larger process in the industry. The connection surface is not covered with H to complete. The layer of electricity can be used for the second electrical resistive connection; 'Increase the cost, the anti-reflective agent is connected to the metal layer that is thin and full of money, and there is no organic matter formed by this shape: barrier metal to provide a measure Elasticity, the barrier metal layer and part: the electric fast food with the barrier metal layer is integrated on the surface and the semiconductor packaging base with the beam-reducing connection pad is integrated. The pattern is fully integrated when using the patterned circuit. Transfer to cover the unsuccessful ^ miss, and then electroplating to form a barrier metal layer on the pad, and ^ -type electroless plating (Electr0-lesS) wears a wider process range, precision = 艨 avoid no electroplating The process shift in the process = the corrosive attack caused by the corrosive attack on the plutonium layer, the contamination of the metal layer, and the contamination of the gold metal layer caused by the trusted circuit design. This phenomenon prevents the subsequent metallization from being smoothly applied, and the phenomenon of skip plating occurs. Or make the electricity The dense nickel / gold gold method is used to form an opening for the electrical connection of the barrier metal layer, and a protective layer is opened in the solder resist layer. The electrical connection pad on the semiconductor package base I has Organic insurance $ Electronic client more demand selective elasticity [implementation method]

4 政和 效应 ’can be further understood. Of course, the following description is the preferred range of the present invention, and it will be described together. '1224387 V. Description of the Invention (ίο) In order to make the purpose of the present invention, Doujisa and Yutong, we will cooperate with the detailed disclosure and the invention can be implemented in various forms, examples, but not to limit the present invention. Please read Section 3 A Figures 3 to 3 are schematic cross-sectional views of an embodiment of a method for manufacturing a semiconductor package substrate with an electrical connection pad according to the present invention. As shown in FIG. 3A, first, a dielectric insulating layer 30 formed on the surface of a multilayer circuit layer is provided. The dielectric insulating layer 30 is formed with a plurality of blind holes 3 01 to expose the inner layer circuit 3 0a. A conductive film 31 is formed on the dielectric insulating layer 30; the insulating layer 30 may be, for example, epoxy

Resin), pioiimide, Cyanate Ester, Glass Fiber, ABF (Ajinomoto Build-up F l 1 m, manufactured by Ajinomoto) Made of arsenylimide / triazine (BT, Bisaleimide Triazine) or mixed epoxy resin and glass fiber (FR 5) and other materials; this conductive film 3 1 is mainly used as a metal plating layer (including patterning) described later The circuit structure and the barrier metal layer on the electrical connection pad) are required for the current conduction path. The conductive film 31 may be composed of a metal, an alloy, or several metal layers deposited, which may be selected from copper, tin, nickel, chromium, A group of metals composed of titanium and copper-chromium alloys. The conductive film 31 can be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), no electric clock, or chemical deposition, such as Spu 11 ering, evaporation, and arc vapor. Arc vapor deposition, Ion beam sputtering, Laser Fused deposition (Laserab 1 ati 〇ndepositi 〇η), Plasma promoted chemical conversion

17356 Quan 懋 .ptd Page 16 1224387 V. Description of the invention (11) Formed by vapor deposition or electroless plating. However, according to the experience that the conductive film 31 is preferably made of T-wood composed of electroless copper particles, as shown in FIG. 3B, the conductive film 3 is covered with a first resistance layer 32 by means of bonding or the like. The first resist layer 3, ^ film or liquid photoresist layer (Ph0t0resist), " and ^ W ,,, L (ExpOsure), and development (Development), etc. The resist layer 32 is formed with a plurality of openings 32, so that a part of the conductive film 3 of the exposed circuit structure is patterned into a pattern: as shown in the paste, and then a plating process is performed to open the first resist layer in 3 2 0. A patterned circuit layer 33 is formed, and conductive blind holes 3 0 2 are formed in the blind holes 3101 of the Ganfa and Ba margin layers 30. Among them, the electrical connection pad 3 3 0 of the patterned line company makes the electrical connection pad 33 〇 ::: Ϊ; !! 0 of the conductive blind hole 3 0 2 is electrically connected to the inner layer line. 3 0- can be formed directly under the electrical connection pad 330 from 202, and the wires of the t: case circuit layer 33 are used to electrically connect the electrical connection pad 33 to the inner layer circuit 30a. Part 2 of the logic pad 330: 2: 'The electrical resistance layer 34 on the substrate is not intended to be formed with a barrier metal layer layer, so that the material of the portion to be formed with the barrier metal layer 34 may be equal. The second resistive layer 34 is exposed outside the 3rd row, and the second resistive layer is the same as the material of the first resistive layer 32. Taxi: Brother 3E shown in the picture, and then electroplating (Electr ati to dazzle through the selenium .... & "clothing flow conduction line, in the conductive blind hole 3 0 2 and the electrical connection pad 3 3 () The isoelectric metal layer 35r is a resistance-to-resistance connection. The direct bond on the 330 forms a barrier so that it can be gold, nickel, silver, silver, tin, nickel /

17356 懋 .Ptd Page 17 1224387

， '/ Titanium, nickel / manganese, palladium / gold or nickel /! Bar / gold, etc. H Nimotoya to nickel / gold metal layer (as shown in Figure 3F), the bean system + the next one is after plating , And then in the bean god furnace, first, a layer of nickel 351 membrane core ore;: ;; two nickel :; metal through the upper surface of the conductor, the electrical properties: two f " " 3 5 ^ ^ ^ ^ t .V /, V. Λ Such as nickel, gold, or other metals described in W, for example, the exposed surface of the sexual connection pad is selected. ^ Simply replace /; category. / 、 为 间 早 之 说 #, both belong to the present invention as shown in FIG. 3G, and then remove the second resistive layer 34 and the first resistive layer 32 to complete the formation of the plating barrier metal layer 35 to cover On part of the entire upper surface of the pad 33 0. As shown in FIG. 3 (a), the conductive film 31 previously covered by the first resistive layer 32 is removed by a technique such as last name engraving. As shown in FIG. 3I, a surface of the package substrate is covered with a Solder mask 36, such as a green paint, to protect the package substrate from external environmental pollution. The solder resist layer 3 6 A plurality of openings 3 6 0 ′ are formed so that the electrical connection pad 3 3 0 of the completed key barrier metal layer 3 5 and the electrical connection pad 3 3 〇 where a barrier metal layer is not formed on part of the surface. Exposed in the solder resist layer openings 3 6 0. As shown in FIG. 3J, an organic solderabi1ity preservative layer 37 is formed on the electrical connection pad 3 3 0 whose surface is not covered with the barrier metal layer 3 5. The connection pad 3 3 0 is covered with a barrier metal layer 3 5, so when immersed in chemistry

17356 Quan 懋 .ptd Page 18 1224387 V. Description of the invention ~ (13) ~ " ϋ The organic solderability protective agent layer is deposited only on the electrical connection pad 3 which is not covered with a barrier = layer 35. 30 on the metal copper body. Among them, the material of the early protective layer 3, a, ', μ has tritriazole, etc., and the disk generally uses azole compounds (such as stupid pad 3 3 0 body gold) The copper J f has a barrier metal I 35 electrically connected to the surface of the electrical connection pad (barely formed as an organometallic complex, in order to prevent the electrical connection pad from being exposed to an organic film on the copper side of the copper. In order to facilitate the purpose of soldering. The world and the environment generate oxidation, and can achieve the protection and integration of a barrier metal layer at the same time. The method described above, that is, the electrical connection pad 33 0 on a substrate, in order to improve the purple, organic The solderability protective agent layer 37 is required to be flexible. /, For the larger process and needs of the vegetable industry and the client, please refer to Figure 4, on the surface of the dagger plate, there are most of the ^ earth through application patterns. The middle system can directly form a conductive blind hole 3 0 2 in the base layer 30, the electrical connection pad 3 3 0 and the insulated electrical connection pads 330 can directly borrow the remaining wire portions to make the blind hole 3 0 2 Electrically conductively connected to the inner layer = resistance = 30a formed by electroplating on the connection pad 330 formed in the insulating layer 30. And Continue to cover the system of organic resins that are to be formed into organic materials. The second material is completely covered with the second resist layer openings. The second resist layer is used to "use" and then the second metal layer is used. The opening of the electrical connection pad is not covered with a full layer of barriers, so that the organic connection pad can be formed on the two connection pads at the same time. "Early-genus" is also part of the electrical connection. Organic solderability on electrical connection pads

17356 Full 懋 .ptd

1224387 V. Description of the invention (14) Protective agent layer. As mentioned above, the present invention is to use a semi-additive method to complete the patterned circuit and the conductive blind hole, and then retain the conductive film and the first resistive layer forming the patterned structure, and then form a second resistive layer to cover Do not want to form the area with a barrier metal layer, and then pass through the conductive film, conductive blind hole, and the electrical connection pad that form the patterned circuit structure, apply a barrier metal layer on the electrical connection pad, and then Removal of these resist layers and conductive films, and subsequent processes of the solder resist layer, so that the solder resist layer has a large number of openings, revealing the electrical connection pads and the surface of the completed metallurgy barrier metal layer. The electrical connection pad body with no protective layer is formed. Secondly, an organic solderability protection agent is deposited on the electrical connection pad exposed in the opening of the solder resist layer. Please refer to FIGS. 5 to 6 for a multi-chip semiconductor device of a semiconductor package substrate with an electrical connection pad protection layer of the present invention. As electronic products are now developing in the direction of multi-function, high-electricity and high-speed operation, in order to support this development direction, the semiconductor industry has actively developed a multi-chip module (Mu 11 i chip) that can integrate semiconductor devices with multiple chips. module (MCM), so as to combine multiple semiconductor wafers into a single package structure to reduce the overall circuit size and improve electrical functions. A semiconductor device with a multi-chip module is connected and electrically connected to at least two or more semiconductor wafers on a wafer carrier (such as a substrate) of a single package, and the connection method between the wafer and the wafer carrier is generally Two methods: one is stacked to stack semiconductor wafers vertically on the wafer carrier, and the other is to use sidebyside to mount multiple semiconductor wafers side by side on the wafer carrier. installation

17356 懋 .ptd page 20 1224387

As shown in FIG. 5, in order to use a multi-chip module conductor device with a stacking method, first the first semiconductor wafer 41 is electrically conductively connected to the chip by a number of metal bumps 41 1 on its circuit surface. An organic solderability protective agent layer is formed on the surface of the substrate 40 for the connection pad 4 0 2, and the surface of the electrical connection pad 4 2 which is electrically connected to the metal bump 4 1 1 (of course, it can also be A nickel / gold metal layer is formed) to protect the electrical connection pad 4 〇2 from being affected by the external environment and rust. The organic solderability protection layer of the electrical connection pad 402 shown in the figure has been carried out. The solder is removed by the flux during the soldering; then, the "one-percent second" semiconductor wafer 42 is connected to the first wafer 41, and the second wafer is passed through the majority of the bonding wires 43. 4 2 is electrically connected to the electrical connection pad 4 01 of the substrate 4 0, and the electrical connection pad 4 electrically connected to the bonding wire 4 3 is formed with a barrier metal layer 4 0 on the surface a If the antimony / gold metal layer is used, the bonding wire 4 3 (usually a gold wire) can be effectively fresh-knotted to the electrical connection 401. As shown in FIG. 6, it is a semiconductor device with a multi-chip module using a side-by-side method. Among them, most semiconductor wafers placed on a substrate can be mounted on the substrate in a side-by-side manner by wire bonding and flip-chip. The first semiconductor wafer 51 can be bonded to the surface of the substrate 50 through a bonding wire 5 2 to form a barrier metal layer 5 0 a on an electrical connection pad 5 01 such as a nickel / gold metal layer, and the second semiconductor The chip 5 3 can pass through the metal bumps 5 3 1 on the circuit surface of the chip to be soldered to the electrical connection pad 5 0 2 with an organic solderability protective layer formed on the surface of the substrate 50, and the organic solderability is protected. The flux layer can be removed by the flux during soldering to form a semiconductor assembly device that integrates most semiconductor wafers.

Fifth invention description (16) As mentioned above, through the surface of the insulative connection pads, there are different conductive elements, metal barrier layers and organic protective layers formed on the semiconductor package substrate at the same time. It is electrically connected to the electrical connection pads of the selective body device such as the front ball, metal bumps, and welding wires. The electrical connection pads of the a-plate require different electrical properties, so as to provide greater design flexibility through the invention according to the semiconductor. . And its manufacturing method, not only can a semiconductor package substrate with a protective pad protection layer have a barrier metal layer, but also can be formed with an organic resistability protective agent layer T by electroplating on some electrical connection pads on the t board, The connection pad is deposited on the connection pad to form a pad and the remaining conductive elements to effectively provide the electrical connection on the substrate and cause the electrical ^: coupling. At the same time, it can also avoid the production of nickel / gold due to the external environment. Oxidation; and exempts conventional chemistry. The problem is to improve the reliability of the packaging structure as the electrical connection of the sealing board. The previous number U and the mask, the surface of the board with no more than 4 stroke connection pads, and the process can be implemented on the substrate :: Calculate = the specific embodiment described above, only using 2-side or double two, too A1 Effectiveness, not to limit the feasibility of the present invention = Explaining the spirit and technology of the invention disclosed above, any :, without changing ^ Fancheng's special effects and dances are still Covered by the library & Ί It should still be an application for

17356 Quan 懋 .ptd Page 22 1224387 Brief description of the drawings [Simplified description of the drawings] Figures 1 A to 1 F are schematic diagrams of the conventional semi-additive substrate manufacturing process; Figures 2 A and 2 B are conventionally used without A schematic diagram of the process of forming a barrier metal layer on the surface of the electrical connection pads of the substrate by electroplating; Sections 3 A to 3 J are schematic sectional views of the embodiment of the method for manufacturing a semiconductor package substrate with an electrical connection pad protection layer of the present invention; Section 4 This is a schematic cross-sectional view of a second embodiment of a method for manufacturing a semiconductor package substrate with an electrical connection pad protection layer according to the present invention. FIG. 5 is a multi-chip with stacking method used for a semiconductor package substrate with an electrical connection pad protection layer according to the present invention. The semiconductor device of the module; and FIG. 6 is a semiconductor device with a multi-chip module in a side-by-side manner applied to a semiconductor package substrate with an electrical connection pad protection layer of the present invention. 10 Core circuit board 11 Circuit layer 12, 14, 30 Insulation layer 13 Key vias 15 Electroless copper 16 Resist layer 17, 33 Circuit layer 18, 36 Solder resist layer 19, 35, 40a, 50a Barrier metal layer 3 0a Inner layer line

17356 Quan 懋 .ptd Page 23 1224387 Simple explanation of the diagram 31 Guide 32 No. 34 No. 37 There are 40, 50 bases 41, 42, 51, 53 Half 43, 52 Welding 140, 180 Power film one resistance layer two resistance layer machine Solderability protector layer conductor wafer hole 160 opening 1 7 0, 3 3 0, 4 0 1, 4 0 2, 5 0 1, 5 0 2 electrical connection pad 301 blind hole 3 0 2 conductive blind hole 3 2 0 first resist opening 35 1 nickel metal layer 3 5 2 gold metal layer 3 6 0 solder resist layer opening 411,531 metal bump

17356 懋 .ptd Page 24

Claims (1)

1224387 VI. Application scope ^ " '一 ^ --- A semiconductor package substrate with an electrical connection pad protection layer, including: a hole-to-edge layer, a plurality of conductive blinds = 1 formed in the insulating layer, and a connection To the inner layer circuit covered under the insulating layer; is formed on the insulating layer, and the conductive film is electrically connected with electric clocks, wherein: the circuit layer includes a plurality of conductive layers; Blind hole; /, ^ The electrical connection pad is electrically connected to a barrier metal layer, which is supported by a surface; it is partially covered by the electrical connection pad—a solder resist layer, and the resist resist layer has a " ^ ^ Install the surface of the substrate, and part of the electrical connection outside the hole of the metal layer disk ^ Obstacles on the electrical connection 卩 卩 Electrical connection pad body ·！ Upper resistance array-organic solderability trap 1 W Kun 'And: L is not covered with = general =: is formed on the antireflective layer, such as the patent application _ Γ, is the electrical connection pad of the layer. The package substrate is complex; brother = the electrical connection 塾 protective layer 。。。 This surface is formed on a multi-layer circuit substrate :: as in the scope of patent application 丨Xiang Ximu, packaging substrate, of which, the strong, electrical connection pad protective layer of the semiconductor line packaging substrate complex f ^ substrate is a flip-chip packaging substrate and • If the scope of patent application 帛: item '. .,,: ② Substrate, among which is the semiconductor with the protective layer of the connection pad. If the patent application scope is 11§, the connection pad may be a bump pad. Page 25 1-member semiconductor with electrical connection pad protection layer 1224387 6. Scope of patent application Package substrate, where the electrical connection pad can be wire bonding pad. 6. The semiconductor package substrate with an electrical connection pad protection layer as claimed in item 1 of the patent application scope, wherein the barrier metal layer can be gold, copper, silver, tin, silver / Iε, chromium / titanium, silver / 金, Ιε / 金 and Record / Ιε / 金 are formed of one of the groups. 7. The semiconductor package substrate with an electrical connection pad protection layer as claimed in item 1 of the scope of the patent application, wherein the organic solderable protective agent layer is a layer-based protection pad of the azole compound-based method for manufacturing a board base package. The c-gtl type of electrical appliances is 18, including the number of blind holes, and the middle layer edge should be formed and the layer edge must be provided-provided; the 0-line wire guide layer is formed in the shape of the lower surface edge hole. And cover the edge of the layer to expose the exposed layer to form the upper film conductance and open the film. The electrical layer resistance is divided into a first section and the exposed number is D 3m. -The first step is to make the layered edge electrical connection of the D-blind connection in the process of electroplating, including the forming process. The pad is connected to the connection layer and the road circuit wire has a small picture, and the pad and the connection hole Blind electrical conductance with multiple holes in the shape of multiple holes and the second step of resistance formation on the second case •, the blind power distribution unit of lil is connected to the electrical connection 4gt} Characteristic β — the layer of the opening Resistance Metal cap layer overlying the barrier metal is not hindered in the process to form plating system plating Hai first barrier layer in the cover and barrier coating layer a second barrier bis · Λ 'of the film in addition to electrical conduction shift 17356 Quan 懋 .ptd Page 26 1224387 VI. Application for a patent A solder resist layer is formed on the surface of the package substrate, and the solder resist layer is formed with barrier metal layers and parts on the electrical connection pads other than openings. An electrical connection pad body; and forming an organic solderability protective agent layer on the electrical connection pad whose surface is not covered with a barrier metal layer. 9. The method for manufacturing a semiconductor package substrate with an electrical connection pad protection layer according to item 8 of the scope of application for a patent, wherein the insulating layer is formed on a surface of a multilayer circuit substrate. 10. The method for manufacturing a semiconductor package substrate with an electrical connection pad protection layer according to item 8 of the scope of the patent application, wherein the package substrate is one of a flip-chip package substrate and a wire-type package substrate. 1 1. The method for manufacturing a semiconductor package substrate with an electrical connection pad protection layer according to item 8 of the scope of patent application, wherein the electrical connection pad may be a bump pad. 1 2. According to the method for manufacturing a semiconductor package substrate with an electrical connection pad protective layer according to item 8 of the scope of patent application, wherein the electrical connection pad may be a wire bonding pad. 1 3. According to the method of manufacturing a semiconductor package substrate with an electrical connection pad protection layer in the scope of patent application No. 8, wherein the barrier metal layer may be gold, copper, Ibar, silver, tin, copper / I &, chromium / Titanium, 构成 / 金, Ιε / 金 and // 纪 / 金 are formed of one of the groups. 14. The method for manufacturing a semiconductor package substrate with an electrical connection pad protection layer according to item 8 of the scope of patent application, wherein the conductive film can be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), or electroless plating. And chemical deposition. 1 5. A semiconductor with an electrical connection pad protection layer as claimed in item 8 of the patent application 17356 Quan 懋 .ptd Page 27 1224387 6. Scope of Patent Application The method of manufacturing a package substrate, wherein the first and second resistive layers can be one of a dry film and a liquid photoresist. 16. The method for manufacturing a semiconductor package substrate with an electrical connection pad protection layer according to item 8 of the scope of patent application, wherein the organic solderability protection agent layer is an azole compound. 1 7. —A method for manufacturing a semiconductor package substrate with a protective layer of an electrical connection pad, comprising: providing an insulating layer, and forming a plurality of blind holes in the insulating layer to expose the inner layer circuits covered under the insulating layer; A conductive film is formed on the insulating layer and the surface of the blind hole; a first resistive layer is formed on the conductive film, and the first resistive layer is formed with a majority of the conductive film exposed outside of the opening; a plating process is performed to the first resistive layer A plurality of electrical connection pads are formed in the opening and conductive blind holes are formed in the blind holes of the insulating layer, and the electrical connection pads are electrically connected to the conductive blind holes; a second resistance is formed on some of the electrical connection pads. Layer, and a plating process is performed to form a barrier metal layer by electroplating on a portion of the electrical connection pads not covered with the second resist layer; removing the second resist layer, the first resist layer, and a layer covering the first resist layer A conductive film; forming a solder resist layer on the surface of the package substrate, and forming the solder resist layer with a barrier metal layer and a portion of the electrical connection pad body exposed on a portion of the electrical connection pad outside the opening; and on the surface Formed on an electrical connection pad not covered with a barrier metal layer 17356 Quan 懋 .ptd Page 28 1224387 6. Scope of patent application Organic solderability protective agent layer. 18. The method for manufacturing a semiconductor package substrate with an electrical connection pad protection layer according to item 17 of the scope of patent application, wherein the insulating layer is formed on the surface of a multilayer circuit substrate. 19. The method for manufacturing a semiconductor package substrate with an electrical connection pad protection layer according to item 17 of the scope of patent application, wherein the package substrate is one of a flip-chip package substrate and a wire-type package substrate. 20. The method for manufacturing a semiconductor package substrate with a protective layer of an electrical connection pad according to item 17 of the scope of patent application, wherein the electrical connection pad may be a bump soldering pad. 2 1. According to the method for manufacturing a semiconductor package substrate with a protective layer of an electrical connection pad in item 17 of the scope of patent application, wherein the electrical connection pad may be a wire bonding pad. 2 2. According to the method for manufacturing a semiconductor package substrate with an electrical connection pad protection layer according to item 17 of the scope of patent application, wherein the barrier metal layer may be gold, nickel, Ibar, silver, tin, nickel / bar, Formed by one of the groups consisting of / chin, record / gold, Ιε / gold, and nickel / $ bar / gold. 2 3. According to the method for manufacturing a semiconductor package substrate with an electrical connection pad protection layer No. 17 in the scope of patent application, wherein the conductive film can be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), It is formed by one of methods of electroplating and chemical deposition. 24. According to the method for manufacturing a semiconductor package substrate with an electrical connection pad protection layer of item 17 of the scope of patent application, wherein the first and second resist layers may be one of a dry film and a liquid photoresist. 2 5 .Semiconductor with protective layer of electrical connection pad as claimed in item 17 of the scope of patent application 17356 懋 .ptd page 29 1224387 ] 7356 Full 懋 .ptd Page 30