TWI405312B - Semiconductor package structure, carrier thereof and manufacturing method for the same - Google Patents

Abstract

A semiconductor package structure, a carrier thereof and a manufacturing method for the same are provided. The carrier has a plurality of pads, each of which is formed with a recess therein. The recess is filled with a solder material, and the solder material is further dispersed on an upper surface of each of the pads. When the pads and the solder material are welded, a concentration point of thermal stress will shift to an opening lip edge of the recess that welded with solder, so as to lower the risk of forming a fracture on the upper surface of the pads. Furthermore, the structure of the recess can reduce the maximum value of thermal stress. Thus, the yield of the reliability test of the semiconductor package structure and the usage life time thereof can be enhanced.

Description

Semiconductor package structure, carrier for semiconductor package structure, and method of manufacturing same

The present invention relates to a semiconductor package structure, a carrier for a semiconductor package structure, and a method of manufacturing the same, and, in particular, to a semiconductor package structure for increasing soldering reliability, a carrier for a semiconductor package structure, and a method of manufacturing the same.

Nowadays, in order to meet the needs of various high-density packaging, the semiconductor packaging industry has gradually developed various types of package structures. Among them, a package structure with a substrate includes a ball grid array (BGA) and a pin array. A pin grid array (PGA), a land grid array (LGA), or a board on chip (BOC). In the above package structure, one of the upper surfaces of the substrate carries at least one wafer, and the number of pads of the wafer is electrically connected to the upper surface of the substrate via a wire bonding or bumping process. Solder pads. At the same time, a lower surface of one of the substrates must also provide a large number of pads to solder several outputs. Furthermore, for a substrate that utilizes a bump to bond a wafer, the substrate is typically selected from a multilayer circuit board that provides a surface circuit layer on the upper surface to form a desired pad, and sometimes the pad, depending on product requirements It is possible to pre-form a pre-solder to increase the reliability of bonding with the bumps of the wafer. Therefore, how to manufacture a package substrate with pre-solder is also an important key technology in the packaging industry.

Please refer to FIGS. 1A and 1B , which illustrate a structure and an assembly diagram of a conventional package substrate with pre-solder and a wafer having bumps, wherein a package substrate 10 is selected from a multilayer circuit board. The surface is provided with a circuit layer 11 and a solder mask. The solder resist layer 12 covers the circuit layer 11, and the solder resist layer 12 has a plurality of openings 121 exposing a portion of the surface of the circuit layer 11 for forming a pad 13. A pre-solder 14 is further formed on each of the pads 13. Furthermore, a wafer 20 is formed on an active surface (not shown) to form a plurality of circuit layers 21, a protective layer 22, a plurality of sub-bump metal layers (UBM) 23, and a plurality of bumps 24. The protective layer 22 covers the circuit layer 21 while the protective layer 22 has a plurality of openings (not labeled) that expose a portion of the surface of the circuit layer 21. The under bump metal layer 23 is formed on the circuit layer 21 in the opening. The bump 24 is formed on the under bump metal layer 23. When soldering is performed at a high temperature, the bumps 24 of the circuit layer 21 of the wafer 20 are soldered and bonded to the pads 13 of the package substrate 10 with the aid of the pre-solder 14, and the pre-solder 14 is integrated into the bumps. Within 24, the soldering operation is completed, and the wafer 20 is electrically connected to the package substrate 10.

However, the pre-solder 14 of the package substrate 10 still has the following problems in practical use. For example, as the semiconductor package structure is miniaturized, the size and pitch of the pads 13 of the package substrate 10 are increasingly reduced. When the outer surface of the solder pad 13 is reduced to less than 80 micrometers (um) and the adjacent pitch of the solder pads 13 is reduced to less than 160 micrometers, the pre-solder 14 can lift the bumps 24 and the pads 13 Between the welding properties, but in the subsequent reliability test of the packaged product (130 ° C / humidity 85% for 96 / 168 hours and 500 cycles at -55 to 125 ° C), it is easy to be in the circuit layer 11 A fracture 15 is generated at the bonding position of the pad 13 to cause the test to fail. The reason why the rupture surface 15 is generated is that the circuit layer 11 and the bonding pad 13 are made of the same material (mainly copper), but since the bonding pad 13 is later electroplated, the bonding force at the bonding position of the two is combined. It is relatively fragile, so that when the thermal stress concentrates, the test defect of the fracture surface 15 is generated at the bonding position, thereby affecting the test yield.

Therefore, it is necessary to provide a semiconductor package structure, a carrier for a semiconductor package structure, and a method of manufacturing the same to solve the problems of the prior art.

A main object of the present invention is to provide a semiconductor package structure, a carrier for a semiconductor package structure, and a method of manufacturing the same, which are formed in a pad of a carrier to fill a solder and fill the solder pad The surface, when the solder pad and the solder are soldered, can transfer the thermal stress concentration position to the opening lip of the groove to reduce the risk of forming a rupture surface between the pad and the circuit layer, and the groove structure can also be Reduce the maximum thermal stress, which in turn improves the yield and reliability of the reliability test.

In order to achieve the above object, the present invention provides a carrier for a semiconductor package structure, which is provided on a carrier board: a circuit layer is formed on a surface of the carrier; an insulating layer is overlying the circuit layer. And the insulating layer forms a plurality of openings to expose a portion of the circuit layer; a plurality of pads are formed on the circuit layer in the opening, and each of the pads is recessed with a groove; and a plurality of solders respectively Formed in the grooves of each of the pads and covered with the upper surface of each of the pads.

In an embodiment of the invention, the carrier is selected from a circuit substrate, and the solder is used as a pre-solder; or the carrier is selected from a wafer, and the solder is used as a bump.

In an embodiment of the invention, the bottom of the recess of the solder pad extends downward into a recess of the circuit layer; or the bottom of the recess of the solder pad penetrates through the circuit layer.

In one embodiment of the invention, the pads of the carrier have an adjacent pitch of less than 160 microns; and the pads of the carrier have an outer diameter of less than 80 microns.

Furthermore, the present invention provides a method of fabricating a carrier for a semiconductor package structure, comprising the steps of: providing a carrier having a circuit layer and an insulating layer on a surface thereof, the insulating layer covering the circuit layer and forming a plurality of layers Opening, to expose a portion of the circuit layer; removing at least a portion of a thickness of the circuit layer in the opening; forming a pad on the circuit layer in each of the openings, the pad having a recess; and, in each of the soldering A solder is formed in the groove of the pad, and the solder is covered on the upper surface of each of the pads.

In an embodiment of the present invention, in the step of removing at least a portion of the thickness of the circuit layer, etching is performed by using an etchant or a plasma to form the recessed portion of the circuit layer; or A circuit layer that penetrates the opening by laser drilling or mechanical drilling is selected.

In an embodiment of the invention, in the step of forming the pad, the pad having the recess is formed on the circuit layer in each of the openings by an electroless plating process.

In an embodiment of the present invention, in the step of forming the solder, the solder is filled in the grooves of each of the pads by plating or printing, and is filled with the pads. Above the surface.

In an embodiment of the invention, after the step of forming the solder, the method further comprises: reflowing the solder.

In an embodiment of the invention, the carrier is selected from a circuit substrate, and the solder is used as a pre-solder; or the carrier is selected from a wafer, and the solder is used as a bump.

In one embodiment of the invention, the pads of the carrier have an adjacent pitch of less than 160 microns; and the pads of the carrier have an outer diameter of less than 80 microns.

In addition, the present invention provides a semiconductor package structure comprising: a circuit substrate having: a first circuit layer formed on a surface of the circuit substrate; a first insulating layer overlying the first circuit layer And the first insulating layer forms a plurality of first openings to expose a portion of the first circuit layer; and a plurality of first pads formed on the first circuit layer in the first opening; a wafer Having: a second circuit layer formed on one active surface of the wafer; a second insulating layer covering the second circuit layer, and the second insulating layer forming a plurality of second openings to expose a portion of the The second circuit layer; and a plurality of second pads formed on the second circuit layer in the second opening, wherein at least one of the first pad of the circuit substrate and the second pad of the chip a recess is formed in the recess; and a plurality of bumps are connected between the first pad and the second pad, and the solder of the bump fills the recess.

In an embodiment of the present invention, the first pad is provided with the groove, and the bottom of the groove extends downward into a recess of the first circuit layer; or the bottom of the groove penetrates through the first A circuit layer.

In an embodiment of the present invention, the first pad is provided with the groove, the adjacent pitch of the first pad is less than 160 micrometers; and the outer surface of the pad of the first carrier is less than 80 Micron.

In an embodiment of the present invention, the second bonding pad is provided with the recess, and the bottom of the recess extends downward into a recess of the second circuit layer; or the bottom of the recess penetrates through the first Two circuit layers.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

In a preferred embodiment of the present invention, the carrier for a semiconductor package structure of the present invention is mainly provided with a circuit layer, an insulating layer, a plurality of pads, and a plurality of solders on a carrier. The carrier is primarily selected from a substrate for packaging or may be selected from a wafer. The invention is used for recessing a central portion of the pad of the carrier to form a recess for filling the solder and covering the upper surface of the pad. For example, as shown in FIG. 2, the carrier for a semiconductor package structure according to the first embodiment of the present invention is mainly provided on a circuit substrate 30: a circuit layer 31 is formed on one surface of the circuit substrate 30; An insulating layer 32 is disposed on the circuit layer 31, and the insulating layer 32 forms a plurality of openings 321 to expose a portion of the circuit layer 31; a plurality of pads 33 are formed on the circuit layer 31 in the opening 321 Each of the pads 33 is recessed with a recess 331; and a plurality of solders 34 are formed in the recesses 331 of each of the pads 33, and the upper surfaces of the pads 33 are covered. The present invention will be described in detail below with reference to FIGS. 3A to 3D for explaining the manufacturing flow and the detailed structure of the carrier for a semiconductor package structure of FIG. 2 in detail.

Referring to FIG. 3A, a first step of a method for manufacturing a carrier for a semiconductor package according to a first embodiment of the present invention is to provide a circuit substrate 30 having a circuit layer 31 and an insulating layer 32 on a surface thereof. The insulating layer 32 covers the circuit layer 31 and forms a plurality of openings 321 to expose a portion of the circuit layer 31. In this step, the circuit board 30 (ie, the carrier board) is selected from a circuit board for semiconductor packaging, for example, a single-layer or multi-layer printed circuit board, a ceramic circuit board, or a flexible circuit board, and the circuit board 30 Preferably, it is selected from a substrate for a flip chip (FC) package. The circuit substrate 30 is provided with a circuit layer 31 on a surface (for example, an upper surface), and the circuit substrate 30 may have other circuit designs depending on the package configuration of the application, for example, the circuit substrate 30 may have other interconnections inside thereof. The internal circuit layer (not shown) and another surface circuit layer (not labeled) on the other surface to provide a number of input/output (IO). In this embodiment, the material of the circuit layer 31 is preferably selected from the group consisting of copper, aluminum, gold, silver or an equivalent conductive metal thereof. The insulating layer 32 covers the circuit layer 31, and the insulating layer 32 is preferably a solder mask formed by a liquid photosensitive material, and the plurality of openings 321 can be formed by processing means such as exposure and development. To expose a portion of the circuit layer 31.

Referring to FIG. 3B, a second step of the method for manufacturing a carrier for a semiconductor package according to the first embodiment of the present invention is to remove at least a part of the thickness of the circuit layer 31 in the opening 321. In this step, the present invention selectively etches with an etchant or plasma to remove at least a portion of the thickness of the circuit layer 31 in the opening 321, but is suitably controlled so as not to penetrate the circuit layer 31. Not only the surface of the circuit layer 31 but also the recessed portion 311 can be formed to increase the bonding area of the circuit layer 31 and the subsequently formed pad 33, thereby increasing the bonding strength between the two. In the etching process described above, the depth of the opening 321 is increased only by the occurrence of the depressed portion 311, but the inner diameter of the opening 321 is generally not enlarged.

Referring to FIG. 3C, a third step of the method for manufacturing a carrier for a semiconductor package according to the first embodiment of the present invention is to form a pad 33 on the circuit layer 31 in each of the openings 321, which is 33. There is a groove 331. In this step, the present invention preferably forms the pad 33 by an electroless plating process, and a patterned photoresist layer (not shown) is preferably formed in advance before the electroless plating process. On the layer 32, the patterned photoresist layer forms a plurality of windows (not shown) corresponding to the openings 321 to define the outer diameter of the upper surface of the pad 33 by the window. The material of the pad 33 is preferably selected from the group consisting of copper, aluminum, gold, silver or an equivalent conductive metal thereof. The present invention does not limit the deposition thickness of the pad 33, but the outer surface of the pad 33 is preferably controlled to be less than 80 microns, and the adjacent pitch of the pad 33 is preferably controlled to be less than 160 microns. The solder pad 33 is deposited on the recess portion 311 of the circuit layer 31 formed in each of the openings 321 by appropriately controlling the processing conditions of the electroless plating process, and extends outward along the hole wall of the opening 321 to the insulating layer. The upper surface of 32, and the pad 33 will form the groove 331 at its central position. The shape of the groove 331 corresponds to the shape of the opening 321, which is generally cylindrical, but is not limited thereto. The number of the grooves 331 of each of the pads 33 is preferably one, but is not limited thereto.

Referring to FIG. 3D, a fourth step of the method for manufacturing a carrier for a semiconductor package according to the first embodiment of the present invention is to form a solder 34 in the recess 331 of each of the pads 33 and to make the solder 34. The upper surface of each of the pads 33 is covered. In this step, the present invention may alternatively fill the recesses 331 of each of the pads 33 with the solder 34 by a plating or printing process. The material of the solder 34 may be selected from tin, lead-containing solder or lead-free solder. For example, the lead-containing solder may be selected from Sn63/Pb37 (63% tin and 37% lead), and the lead-free solder may be selected from Sn0. .7Cu (containing 0.7% copper), Sn3.5Ag (containing 3.5% copper), Sn3.5Ag0.7Cu (containing 3.5% silver and 0.7% copper), Sn9Zn (containing 9% zinc), Sn5Sb ( 5% of 锑), Sn58Bi (including 58% of bismuth), Sn52In (including 52% of indium), In3Ag (containing 97% of indium and 3% of silver), Au20Sn (including 80% of gold and 20% Tin), but not limited to this. After the plating or printing process is completed, the solder 34 will fill the recess 331 and overflow to cover the entire upper surface of the pad 33 for use as a pre-solder. Furthermore, in an embodiment, as shown in FIG. 2, in the present invention, after the solder 34 is formed, the solder 34 is further reflowed to form an arc due to cohesive force when the solder 34 is melted. Appearance.

Referring to FIG. 4, the circuit substrate 30 of the first embodiment of the present invention is a package substrate which can be used to bond a wafer 40 to form a flip chip semiconductor package structure. In one embodiment, the wafer 40 is selected from a silicon wafer cut from a semiconductor wafer, and is formed on an active surface (not labeled) to form a plurality of circuit layers 41, an insulating layer 42, and a plurality of bumps. Metal layer 43 and a plurality of bumps 44. The insulating layer 42 covers the circuit layer 41 while the insulating layer 42 has a plurality of openings 421 that expose a portion of the surface of the circuit layer 41. The under bump metal layer 43 is formed on the circuit layer 41 in the opening 421. The bump 44 is formed on the under bump metal layer 43. The bumps 44 may be selected from the same or different materials of the solder 34, such as selected from tin or various lead-containing solders or lead-free solders.

Referring to FIG. 5, when soldering is performed at a high temperature, the bump 44 of the circuit layer 41 of the wafer 40 is soldered and bonded to the pad 33 of the circuit substrate 30 with the aid of the solder 34, and the soldering is performed. The solder 34 in the upper surface of the pad 33 and the recess 331 is integrated into the bump 44 to form a solder structure, thereby electrically connecting the wafer 40 to the circuit substrate 30. After the fabrication of the flip-chip semiconductor package structure was completed, the present invention was then subjected to reliability testing (130 ° C / humidity 85% for 96/168 hours and 500 cycles at -55 to 125 ° C). The test results show that even if the outer diameter of the upper surface of the pad 33 of the circuit substrate 30 is reduced to 80 μm or less and the adjacent pitch of the pad 33 is reduced to 160 μm or less, the soldering between the bump 44 and the pad 33 is performed. The construction is still sufficient to withstand the thermal stress caused by the difference in coefficient of thermal expansion (CTE) and no fracture is formed. It is confirmed by analysis that since the pad 33 of the circuit substrate 30 of the present invention is provided with the groove 331 to accommodate the solder 34, the groove 331 can provide a larger surface area, so that the pad 33 and the bump 44 are disposed. Has a larger weld joint area. At the same time, the thermal stress concentration point S of the welded structure will also be transferred to the opening lip of the groove 33 of the pad 33, and the maximum value of the thermal stress will be significantly reduced. Therefore, the design of the present invention for accommodating the solder 34 by the recess 331 can strengthen the solder joint strength between the bump 44 and the pad 33 during high-temperature soldering, and reduce the incidence of test defects, thereby improving the test. Yield and product life.

Referring to FIGS. 6A to 6D, the manufacturing method of the carrier for semiconductor package structure according to the second embodiment of the present invention is similar to the first embodiment of the present invention, and substantially the same drawing number is used, but the difference is that the first In the second embodiment, in the second step, the circuit layer 31 in the opening 321 of the insulating layer 32 is selected by laser drilling or mechanical drilling. Therefore, in the third step, the bottom of the groove 331 of the pad 33 will penetrate downward through the circuit layer 31 for a predetermined length, which can be appropriately adjusted according to product requirements. Thereby, the bonding area of the circuit layer 31 and the subsequently formed pad 33 can be further increased, thereby increasing the bonding strength between the two. Furthermore, in the fourth step, the recess 331 will accommodate more of the solder 34. When the circuit substrate 30 is bonded to a wafer 40 (similar to that shown in FIGS. 4 and 5), the recess 331 can also provide a larger surface area, so that the pad 33 and the bump 44 have a larger space. Welding joint area. At the same time, the thermal stress concentration point S of the soldering structure of the pad 33 and the bump 44 will also be transferred to the opening lip of the recess 33 of the pad 33, and the maximum value of the thermal stress will be significantly lowered. Therefore, the second embodiment of the present invention can further strengthen the solder joint strength of the bumps 44.

Referring to FIG. 7, the semiconductor package structure of the third embodiment of the present invention is similar to the first embodiment of the present invention, and generally uses the same drawing number, but the difference is that the third embodiment has a groove design. Applied to the wafer 40, the circuit layer 41 exposed by the opening 421 of the insulating layer 42 of the wafer 40 is first etched with an etchant or plasma to remove at least a portion of the circuit layer 41 in the opening 421. The thickness, but not the circuit layer 41, is formed so that a depressed portion 411 can be formed on the surface of the circuit layer 41. Then, a pad 45 is formed on the recess 411 of the circuit layer 41 of the wafer 40, and each of the pads 45 is recessed at a central position thereof to form a recess 451, and a solder 46 is filled into the recess. The upper surface of each of the pads 45 is covered in 451. The solder 46 can be further reflowed to form a bump shape. Furthermore, in the third embodiment, the circuit substrate 30 is a flip chip substrate, and the pad 33 on the upper surface thereof can also have the design of the recess 331 to accommodate the solder 34 as a pre-solder. . Therefore, when the wafer 40 and the circuit substrate 30 are bonded at a high temperature, the groove 451 of the pad 45 of the wafer 40 can also increase the bonding strength between the pad 45 and the solder 46, and change the thermal stress concentration point. S to the opening lip of the groove 451, and can reduce the maximum thermal stress, and improve the yield of the reliability test and the service life of the product.

Furthermore, in the third embodiment, in order to make the pad 45 have a sufficient height (thickness), the present invention can further form a re-distribution layer on the protective layer 42a on the active surface of the wafer 40 (redistribution). The insulating layer 42b serves as the insulating layer 42 for the purpose of increasing the height (thickness) of the pad 45. In addition, if the circuit layer 41 of the active surface of the wafer 40 is designed, it is also possible to select a circuit layer 41 in the opening 421 of the insulating layer 42 by laser drilling or mechanical drilling to make the pad 45 concave. The bottom of the groove 451 penetrates through the circuit layer 41 for a predetermined length (not shown) to further increase the bonding area of the circuit layer 41 and the subsequently formed pad 45, thereby increasing the bonding strength. Alternatively, in another embodiment, under the premise that the pad 45 of the wafer 40 already has the recess 451, the upper surface of the pad 33 of the circuit substrate 30 may also remain flat, and the recess 331 is omitted. The design and only the conventional pre-solder (not shown) is disposed on the upper surface of the pad 33.

As described above, the pre-solder 14 on the pad 13 of the conventional package substrate 10 of FIGS. 1 and 2 is still easily bonded to the bumps 14 of the wafer 20 after being bonded to the bumps 24 of the wafer 20. The problem of the rupture surface 15 is caused by the concentration of thermal stress at the joint position, and the present invention according to FIGS. 3 to 5 is formed by the groove 331 in the pad 33 of the carrier structure such as the circuit substrate 30 so as to be filled in. The solder 34 and the solder 34 are covered on the upper surface of the pad 33, which can effectively increase the bonding area and bonding strength between the solder 34 and the pad 33. Furthermore, after the solder pad 33 and the solder 34 are soldered, the thermal stress concentration point S can be transferred to the opening lip of the recess 331 to reduce the formation of a rupture surface on the surface of the recess 311 of the solder pad 31. The risk, at the same time, the configuration of the groove 331 can also reduce the maximum thermal stress, thereby improving the yield of the reliability test and the service life of the product.

The present invention has been disclosed in its preferred embodiments, and is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

T0. . . Package substrate

11. . . Circuit layer

12. . . Solder mask

121. . . Opening

13. . . Solder pad

14. . . Pre-solder

15. . . Rupture surface

20. . . Wafer

twenty one. . . Circuit layer

twenty two. . . The protective layer

twenty three. . . Under bump metal layer

twenty four. . . Bump

30. . . Circuit substrate

31. . . Circuit layer

311. . . Depression

32. . . Insulation

321. . . Opening

33. . . Solder pad

331. . . Groove

34. . . solder

40. . . Wafer

41. . . Circuit layer

411. . . Depression

42. . . Insulation

42a. . . The protective layer

42b. . . Re-insulation

421. . . Opening

43. . . Under bump metal layer

44. . . Bump

45. . . Solder pad

451. . . Groove

46. . . solder

S. . . Thermal stress concentration point

1A and 1B are schematic views of a substrate for packaging having a pre-solder and a wafer having bumps.

Fig. 2 is a schematic view showing a carrier for a semiconductor package structure according to a first embodiment of the present invention.

3A to 3D are flowcharts showing a method of manufacturing a carrier for a semiconductor package according to the first embodiment of the present invention.

Fig. 4 is a view showing the semiconductor package structure of the first embodiment of the present invention before solder bonding.

Fig. 5 is a schematic view showing the semiconductor package structure of the first embodiment of the present invention after solder bonding.

6A to 6D are flowcharts showing a method of manufacturing a carrier for a semiconductor package structure according to a second embodiment of the present invention.

Fig. 7 is a view showing the semiconductor package structure of the third embodiment of the present invention before solder bonding.

30. . . Circuit substrate

31. . . Circuit layer

311. . . Depression

32. . . Insulation

321. . . Opening

33. . . Solder pad

331. . . Groove

34. . . solder

40. . . Wafer

41. . . Circuit layer

42. . . Insulation

421. . . Opening

43. . . Under bump metal layer

44. . . Bump

Claims (7)

A carrier board for semiconductor package construction, which is disposed on a carrier board: a circuit layer is formed on a surface of the carrier board; an insulating layer covers the circuit layer, and the insulating layer forms a plurality of openings a portion of the circuit layer is exposed; a plurality of pads are formed on the circuit layer in the opening, and each of the pads is recessed with a recess, and a bottom of the pad of the pad penetrates through the circuit layer; And a plurality of solders respectively formed in the grooves of each of the pads and covering the upper surface of each of the pads. The carrier for semiconductor package structure according to claim 1, wherein the carrier is selected from a circuit substrate, and the solder is used as a pre-solder. The carrier for semiconductor package construction according to claim 1, wherein the adjacent pads of the carrier are spaced apart by less than 160 μm; and the upper surface of the pads of the carrier is less than 80 μm. A manufacturing method of a carrier for a semiconductor package structure, comprising the steps of: providing a carrier plate having a circuit layer and an insulating layer on a surface, the insulating layer covering the circuit layer and forming a plurality of openings to expose a part of the The circuit layer; removing at least a portion of the thickness of the circuit layer in the opening; forming a solder pad on the circuit layer in each of the openings, the solder pad having a recess, the bottom of the recess of the solder pad penetrating through the bottom Circuit layer And forming a solder in the grooves of each of the pads, and allowing the solder to fill the upper surface of each of the pads. A semiconductor package structure comprising: a circuit substrate having: a first circuit layer formed on a surface of the circuit substrate; a first insulating layer overlying the first circuit layer, and the first The insulating layer forms a plurality of first openings to expose a portion of the first circuit layer, and a plurality of first pads are formed on the first circuit layer in the first opening; a wafer having: a first a second circuit layer formed on one active surface of the wafer; a second insulating layer overlying the second circuit layer, and the second insulating layer forming a plurality of second openings to expose a portion of the second circuit And a plurality of second pads formed on the second circuit layer in the second opening; and a plurality of bumps connected between the first pad of the circuit substrate and the second pad of the wafer Wherein the first pad is provided with a recess, the bottom of the recess penetrating through the first circuit layer, and the solder of the bump is filled into the recess. The semiconductor package structure of claim 5, wherein the first pad is provided with the groove, and the adjacent spacing of the first pad is less than 160 microns; and the upper surface of the pad of the first carrier has an outer diameter of less than 80 microns. The semiconductor package structure of claim 5, wherein the second pad is provided with the groove, and the bottom of the groove penetrates through the second circuit layer downward.