TW200428605A - Method for fabricating substrate with plated metal layer over pads thereon - Google Patents
Method for fabricating substrate with plated metal layer over pads thereon Download PDFInfo
- Publication number
- TW200428605A TW200428605A TW092115796A TW92115796A TW200428605A TW 200428605 A TW200428605 A TW 200428605A TW 092115796 A TW092115796 A TW 092115796A TW 92115796 A TW92115796 A TW 92115796A TW 200428605 A TW200428605 A TW 200428605A
- Authority
- TW
- Taiwan
- Prior art keywords
- electrical connection
- metal layer
- package substrate
- connection pad
- layer
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Manufacturing Of Printed Wiring (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electroplating Methods And Accessories (AREA)
Abstract
Description
200428605 五、發明說明（l) 發明所屬之技術領_ 本發明係關於〜1 1 鍵金屬層之方法= f =電性連接墊形成電 電鍍有一㉟/金金屬在：片封，用基板之銲塾外露表面 連接品質之電性連接蝥。猎以提供讀基板良好電性 ^先前技術】 一般半導體封袭爲 組成之導電線路，彡；：表面形成有多數例如由銅材質所 4·^為訊號傳輸之用。二加以延伸而成為電性連接墊，以 ίΛ鬼或銲j灰）順利祕、、常’為令導電元件（如金線、錫銲 或銲球）順利地I : 句々ν笔兀件（如金線、 I連接墊外露表面上必唁#輕接至晶片或電路板表面，電性 (Nl/Ag)等金屬層來做;^設接一層+如鎮丰t (Nl/Au)、錄/銀 々拉人θ 马鲜接導電兀件與電性連接墊之門 ^接3層:傳統電性連接墊一般包含提供覆晶型封裝基B 1 ip —Chip Package Substrate)與晶片電性耦合之凸i塊 銲墊（BUmp Pad)、預銲錫銲墊（Pres〇lder pad)，或是供 |打，式封裝基板（Wire BoruHng package Substrate)與晶 片電性耦合之打線墊（Finger)，亦或是可以提供封裝基^ …二他包路板電性銲結之銲球墊（Ba丨丨pad)等，藉由形 _電性連接墊表面之鎳/金金屬層，可防止電性連接墊^- 丨，並且提高導電元件與電性連接墊間之銲接信賴性 (δο1ά^ Joint Reliability)〇 性 :，統製程中於電性連接墊上形成鎳/金金屬層之方 孚 ^包含有化學鎳/金製程、離子濺擊法、電漿沉200428605 V. Description of the invention (l) The technical field of the invention _ The present invention is about the method of a ~ 1 1 bond metal layer = f = electrical connection pads are formed by electroplating with a ㉟ / gold metal in: sheet sealing, welding with a substrate电 Electrical connection with exposed surface connection quality 蝥. In order to provide good electrical properties of the read substrate ^ Previous technology: Generally, semiconductor circuits are composed of conductive lines, 彡;: Most of the surface is formed of copper, for example, for signal transmission. Second, it will be extended to become an electrical connection pad, with ίΛ or soldering ash) to make the conductive component (such as gold wire, solder or solder ball) smoothly. I: 句 々 ν On the exposed surface of the gold wire and I connection pad, it must be connected lightly to the surface of the chip or circuit board, and metal layers such as electrical (Nl / Ag); ^ set a layer + such as Zhenfeng t (Nl / Au), recording / Silver pull θ The door of the conductive conductive element and the electrical connection pad ^ is connected to 3 layers: The traditional electrical connection pad generally includes a flip-chip package base B 1 ip-Chip Package Substrate) and the chip is electrically coupled BUmp Pad, Presolder Pad, or Finger Pad for electrically coupling the Wire BoruHng package Substrate and the chip. Or can provide packaging base ^… Erta package circuit board electrical bonding pads (Ba 丨 丨 pad), etc., by the shape of the nickel / gold metal layer on the surface of the electrical connection pad, can prevent electrical connection Pad ^-丨, and improve the soldering reliability (δο1ά ^ Joint Reliability) between the conductive element and the electrical connection pad: the electrical connection during the control process Fu pad of forming nickel / gold metal layer ^ with nickel / gold process, sputtering ion blow method, plasma Shen
17228 全懋.Ptd 1凌以及電鍍鎳/金製程等。 、 200428605 五、發明說明（2) _ 惟該化學錄/金製程常發生許多例如跳鍍與黑塾 (Black pad)等銲錫性欠佳或銲點強度不足等信賴性問 題。其中，該跳鍍問題之產生係於製程中由於化鎳槽降溫 休息一段時間再生產時，即使所有作業條件均已備妥，仍 會出現電鍍能力不足不易滿鍍之現象，使後續之金無法順 利鍍上，因此出現露銅現象；而該黑墊問題之形成，係由 於化鎳表面在進行浸金置換時，其鎳面受到過度氧化反 應，加以體積甚大之金原子不規則沉積與其粗彳造晶粒之稀 疏多孔，造成底鎳持續經化學電池效應之促動，而不斷產 生氧化與老化，以致金面底下產生未能熔走的鎳鏽所繼續 累積而成；上述化學鎳/金製程之跳鍍與黑墊之問題均容 易造成日後金線、銲錫凸塊、預銲錫或銲球等與電性連接 墊間脫落剝離無法相互電性耦合之現象·。而離子濺擊法或 電漿沉積法之成本則過高，不符經濟效益。 因此，一般業界多採用電鍍方式以在電性連接墊上形 成錄/金金屬層。如第1圖所示，習知電鍍錄/金之製程係 於一已完成前段製程，例如線路圖案化之上、下線路層' 1 1，1 2、若干導通孔1 3等已形成於其中，之基板1上，運用 顯影與蝕刻等技術，在該基板1上定義出若干電性連接墊 1 4 (如打線墊或銲球墊等），該基板1之外表面上並覆有一 拒銲層1 5。 第1圖所示基板上之電性連接墊1 4，雖已揭示電性連 接墊1 4上電鍍有一鎳/金金屬層1 6結構，但為形成此結 構，則必須在基板上形成有導電線路同時另外佈設眾多之17228 Quan. Ptd 1 Ling and electroplated nickel / gold process. 200428605 V. Description of the Invention (2) _ However, the chemical recording / gold process often suffers from reliability issues such as poor solderability such as jump plating and black pads or insufficient solder joint strength. Among them, the problem of jump plating is caused by the cooling of the nickel bath during the production process and rest for a period of time. Even if all the operating conditions are prepared, there will still be insufficient plating ability and full plating, which will make subsequent gold smooth. Copper plating appears, and therefore the phenomenon of exposed copper appears; and the formation of the black pad problem is due to the excessive oxidation reaction of the nickel surface of the nickel surface during the immersion gold replacement, and the irregular deposition of large gold atoms and their rough fabrication The sparse and porous grains cause the bottom nickel to continue to be driven by the chemical battery effect, and continue to produce oxidation and aging, so that nickel rust that cannot be removed under the gold surface continues to accumulate; the above-mentioned chemical nickel / gold process The problems of jump plating and black pads are likely to cause the phenomenon that the gold wires, solder bumps, pre-solders or solder balls, etc., fall off and peel off from the electrical connection pads and cannot be electrically coupled to each other in the future. The cost of ion sputtering or plasma deposition is too high, which is not economical. Therefore, the general industry uses electroplating to form a recording / gold metal layer on the electrical connection pads. As shown in Figure 1, the conventional plating / gold process is based on a completed previous process, such as the patterning of the upper and lower circuit layers' 1 1, 1, 2, and several vias 13 have been formed therein. On the substrate 1, a number of electrical connection pads 14 (such as wire bonding pads or solder ball pads) are defined on the substrate 1 by using development and etching techniques. The outer surface of the substrate 1 is covered with a solder resist. Layers 1 to 5. The electrical connection pads 14 on the substrate shown in FIG. 1 have been disclosed with a nickel / gold metal layer 16 structure electroplated on the electrical connection pads 14, but in order to form this structure, a conductive layer must be formed on the substrate. Many lines are also laid out at the same time
17228 全懋.ptd 第9頁 200428605 五、發明說明（3) -電鍍導線1 7，俾利用電鍍導線1 7將鎳/金金屬層1 6電鍍於 電性連接墊1 4上。如此一來，雖可於電性連接墊1 4形成鎳 /金金屬層1 6，但亦必須佈設眾多電鍍導線進行電鍍，不 但占據了基板1上之佈線面積，而且在高頻使用時，因多 餘之電鍍導線之天線效應，容易造成雜訊。而如果使用回 蝕刻方式（Etchback)雖可切除電鍍導線1 7，但仍會遺留下 電鍍導線尾端部份。因此在基板上電性連接墊1 4雖形成有 鎳/金金屬層之結構，但又包含一堆電鍍導線尾端之紊亂 -結構。故’線路佈設面積不足以及在南頻使用易產生雜訊 之問題依舊存在，此外，由於在該電性連接墊1 4上電 鍍鎳V金金屬層1 6時，該電鍍導線1 7表面亦形成有鎳/金金 屬層，而後續必需經過多次之回蝕刻，方可移除該些無電 路作用之電鍍導線1 7，因而導致基板嚴重刮傷，再者，對 於基板線路佈設複雜，電性連接墊形成密度高的情況下， 即無有效剩餘基板面積可供另外佈設有電鍍導線，造成電 鍍錄/金製程困難度的增加。 另一種業界熟知的電鍍製程係以金層圖案化電鍍法' (Gold Pattern Plat ing， GPP)製作。請參閱第 2A至 2DSI 戶#示，該製程係首先在基板2之上.、下表面上各形成有一 電層21 (如第2 A圖所示），該基板2中並形成若干之導通 孔（？！^)或盲孔（61111(1乂13)(未圖示）以電性導接該基板上 下表面之導電層21。 接著，如第2B圖所示，於該基板2導電層21覆蓋一光 阻層22(Photoresist)，並使該光阻層2 2形成有多數開孔17228 All 懋 .ptd Page 9 200428605 V. Description of the Invention (3)-Plating lead 17, using the lead 17 to plate the nickel / gold metal layer 16 on the electrical connection pad 14. In this way, although the nickel / gold metal layer 16 can be formed on the electrical connection pads 14, it is also necessary to arrange a large number of plated wires for electroplating, which not only takes up the wiring area on the substrate 1, but also has high frequency usage. The antenna effect of the extra plated wires can easily cause noise. If the Etchback method is used, the plated wire 17 can be cut off, but the tail end portion of the plated wire is still left. Therefore, although the electrical connection pads 14 on the substrate are formed with a structure of a nickel / gold metal layer, they also include a pile of disorder-structures at the ends of the plated wires. Therefore, the problems of insufficient circuit layout area and easy to generate noise in the use of the South frequency still exist. In addition, when the nickel V gold metal layer 16 is plated on the electrical connection pad 14, the surface of the plated wire 17 is also formed. There is a nickel / gold metal layer, and subsequent subsequent etch-backs must be performed to remove these electroless plated wires 17, which causes serious scratches on the substrate. Furthermore, the layout of the substrate circuit is complicated and electrical. In the case where the formation density of the connection pads is high, that is, there is no effective remaining substrate area for additional plating wires, which causes an increase in the difficulty of the electroplating / gold process. Another well-known electroplating process is made by Gold Pattern Plating (GPP). Please refer to Sections 2A to 2DSI. The process is to first form an electrical layer 21 on the lower surface of the substrate 2 (as shown in Figure 2A), and a number of via holes are formed in the substrate 2 (?! ^) Or blind hole (61111 (1 乂 13) (not shown) to electrically connect the conductive layer 21 on the upper and lower surfaces of the substrate. Next, as shown in FIG. 2B, the conductive layer 21 on the substrate 2 Cover a photoresist layer 22 (Photoresist), and form a plurality of openings in the photoresist layer 22
17228 全懋.ptd 第10頁 200428605 五、發明說明（4) 以露出預備形成線路區域之導電層2 1，俾藉該導電層2 1作 為電流傳導路徑，以在該導電層2 1上未被光阻層2 2覆蓋之 區域電鍵一層鎳/金金屬層23。 之後，如第2 C圖所示，移除該光阻層2 2，復以該鎳/ 金金屬層2 3當作遮罩阻層，利用姓刻技術將錄/金金屬層 2 3下之導電層2 1進行線路圖案化，以使該導電層2 1形成之 線路圖案2 1 a表面著覆一層鎳/金金屬層2 3，如第2 D圖所 示。 該GPP技術雖係利用導電層取代電鍍導線來提供鎳/金 電鍍電流通過，惟於基板整個線路層（包含電性連接墊與 所有導電線路）表面均覆蓋上鎳/金金屬層，其材料成本極 其昂貴，而且，線路層表面整個覆蓋有鎳金層，亦會導致 基板實施後續線路圖案化製程時，因拒銲層與鎳金層材質 特性差異而導致兩者之間著附困難，無法達到穩定的結 合° 因此，如何簡化製程步驟、花費較少成本以避免傳統 化學鎳/金製程產生之跳鍍與黑墊等問題，以及免除習知 電鍍鎳/金製程衍生之增設電鍍導線產生之信賴性不良與 成本浪費等問題，實為目前亟欲解決之課題。 【發明内容】 鑒於以上所述習知技術之缺點，本發明之主要目的係 提供一種半導體封裝基板電性連接墊形成電鍍金屬層之方 法，俾使電性連接墊之外露表面電鍍有一如鎳/金之金屬 層，有助於金線、銲錫凸塊或銲球與晶片或電路板之電性17228 Quan 懋 .ptd Page 10 200428605 V. Description of the invention (4) The conductive layer 2 1 is exposed to prepare the circuit area, and the conductive layer 21 is used as a current conduction path so that the conductive layer 21 is not The area covered by the photoresist layer 22 is electrically bonded to a nickel / gold metal layer 23. After that, as shown in FIG. 2C, the photoresist layer 22 is removed, and the nickel / gold metal layer 23 is used as a mask resist layer, and the metal / gold metal layer 2 3 The conductive layer 21 is patterned, so that the surface of the circuit pattern 21a formed by the conductive layer 21 is covered with a nickel / gold metal layer 23, as shown in FIG. 2D. Although the GPP technology uses a conductive layer instead of a plated wire to provide nickel / gold plating current, the entire circuit layer of the substrate (including the electrical connection pads and all conductive lines) is covered with a nickel / gold metal layer, and its material cost Extremely expensive, and the entire surface of the circuit layer is covered with a nickel-gold layer, which will also lead to difficulties in attaching the solder resist layer and the nickel-gold layer due to the difference in material characteristics of the substrate during the subsequent circuit patterning process. Stable bonding ° Therefore, how to simplify the process steps and spend less cost to avoid problems such as jump plating and black pads caused by traditional chemical nickel / gold processes, as well as avoiding the trust generated by the addition of electroplated wires derived from the conventional electroplated nickel / gold process Problems such as bad sex and cost waste are really the issues that are urgently needed to be solved. [Summary of the Invention] In view of the shortcomings of the conventional technology described above, the main object of the present invention is to provide a method for forming a plating metal layer on an electrical connection pad of a semiconductor package substrate. A metal layer of gold that helps the electrical properties of gold wires, solder bumps, or balls to the chip or circuit board
17228 全懋.ptd 第11頁 200428605 五、發明說明（5) 弟合，俾藉由該金屬層提供電性連接墊不易因外界環境影 響而導致該電性連接墊本體氧化。 本發明之另一目的係提供一種半導體封裝基板電性連 接墊形成電鍍金屬層之方法，可避免習知化學錄/金製程 產生之跳鍍與黑墊等問題，以有效提昇封裝結構信賴性。 本發明之又一目的係提供一種半導體封裝基板電性連 接墊形成電鍍金屬層之方法，無需於封裝基板之表面另外 佈設電鍍導線，藉以大幅增加封裝基板有效佈線面積，並 減少因佈設電鍍導線所衍生之雜訊干擾問題。 β本發明之再一目的係提供一種半導體封裝基板電性連 接墊形成電鍍金屬層之方法，可避免習知製程需於封裝基 板之整層線路層上均覆蓋一鎳/金金屬層，而僅在該電性 連接墊上形成所需之鎳/金金屬層，藉以有效降低電鍍鎳/ 金之成本。 本發明之再一目的係提供一種半導體封裝基板電性連 接墊形成電鍍金屬層之方法，以增加基板上線路佈設密集 度。 '· 為達上揭目的，本發明提供一方法以形成電性連接墊 i電鍍金屬層，其係包括下列步驟：提供一至少一表面具 複數個導電線路與電性連接墊之半導體封裝基板；再於 該基板之表面覆蓋第一阻層；並於該第一阻層上形成有至 少一開口 ，且該開口係可連通至鄰近之導電線路；接著於 該開口 中形成導電膜（Electrically conductive film)， 俾使該導電膜得以電性導接鄰近之導電線路與電性連接17228 Quan 懋 .ptd Page 11 200428605 V. Description of the Invention (5) Brother He, The electrical connection pad provided by the metal layer is not easy to cause the electrical connection pad body to be oxidized due to the external environment. Another object of the present invention is to provide a method for forming a plated metal layer by electrically connecting pads of a semiconductor package substrate, which can avoid problems such as jump plating and black pads caused by the conventional chemical recording / gold process, so as to effectively improve the reliability of the package structure. Yet another object of the present invention is to provide a method for forming a plated metal layer by electrically connecting pads of a semiconductor package substrate, without the need to separately arrange plated wires on the surface of the package substrate, thereby greatly increasing the effective wiring area of the package substrate and reducing Derived noise interference issues. β Another object of the present invention is to provide a method for forming an electroplated metal layer on an electrical connection pad of a semiconductor package substrate, which can avoid the need for the conventional manufacturing process to cover the entire circuit layer of the package substrate with a nickel / gold metal layer, and only A required nickel / gold metal layer is formed on the electrical connection pad, thereby effectively reducing the cost of nickel / gold plating. Another object of the present invention is to provide a method for forming a plated metal layer by electrically connecting pads of a semiconductor package substrate, so as to increase the wiring density on the substrate. In order to achieve the purpose of disclosure, the present invention provides a method for forming an electroplated metal layer of an electrical connection pad, which includes the following steps: providing a semiconductor package substrate with at least one surface having a plurality of conductive lines and electrical connection pads; Then, a first resistive layer is covered on the surface of the substrate; at least one opening is formed on the first resistive layer, and the opening can communicate with the adjacent conductive circuit; and then a conductive film is formed in the opening. ), So that the conductive film can be electrically connected to adjacent conductive lines and electrically connected
17228 全懋.ptd 第12頁 200428605 五、發明說明（6) 墊；將該基板表面之第一阻層移除後再於該基板上敷設第 二阻層，且該第二阻層形成有多數開孔以顯露出該電性連 接塾；然後進行電鍍製程，以使該電性連接塾外露表面電 鍍有一欲形成如鎳/金之金屬層；再依序將該基板上之第 二阻層與導電膜移除；之後可於該封裝基板表面形成一拒 銲層，並使該拒銲層具有複數個開孔以顯露已完成電鍍金 屬層之電性連接墊，且該拒銲層之開孔孔徑可大於或小於 電性連接墊之大小。 藉由本發明之半導體封裝基板電性連接墊形成電鍍金 屬層之方法，不僅可提供電性連接墊之外露表面包覆有一 含錄金之金屬層，以有效幫助金線、鲜鍚凸塊、或銲球 等與晶片或電路板之電性耦合；亦可避免該電性連接墊本 體受外界環境影響而導致之氧化；且避免習知化學鎳/金 製程時所產生之跳鍍與黑墊等問題，可有效提昇封裝結構 信賴性；同時於電鍍鎳/金時無需在封裝基板之表面佈設 電鍍導線，藉以大幅增加封裝基板有效佈線面積，並減少 因佈設電鍍導線所衍生之雜訊干擾問題「再者，亦可避免 習知電鍍鎳/金製程時，須於封裝基板之整層線路層上均_ 覆蓋一含鎳/金之金屬層，而可有效降低電鍍鎳/金之成 本0 以下列舉實施例以進一步詳細說明本發明，但本發明 並不受此等實施例所限制。尤有甚者，本發明電性連接墊 電鍍金屬層可廣泛運用於一般封裝基板，圖式及說明雖以 覆晶封裝基板闡明其實施情形，惟此非用以限制本發明運17228 Quan 懋 .ptd Page 12 200428605 V. Description of the invention (6) Pad; after the first resistance layer on the substrate surface is removed, a second resistance layer is laid on the substrate, and the second resistance layer is formed with a majority A hole is opened to expose the electrical connection 塾; then a plating process is performed so that the exposed surface of the electrical connection 电镀 is plated with a metal layer such as nickel / gold to be formed; and then the second resistance layer on the substrate and the The conductive film is removed; a solder resist layer can be formed on the surface of the package substrate, and the solder resist layer has a plurality of openings to expose the electrical connection pads of the electroplated metal layer, and the openings of the solder resist layer The aperture may be larger or smaller than the size of the electrical connection pad. The method for forming a plated metal layer by using the electrical connection pads of the semiconductor package substrate of the present invention can not only provide an exposed surface of the electrical connection pads with a metal layer containing gold to effectively help gold wires, fresh bumps, or Electrical coupling of solder balls and wafers or circuit boards; also avoid oxidation of the electrical connection pad body caused by external environment; and avoid jump plating and black pads caused by the conventional chemical nickel / gold process Problems, which can effectively improve the reliability of the package structure. At the same time, when plating nickel / gold, there is no need to arrange plated wires on the surface of the package substrate, thereby greatly increasing the effective wiring area of the package substrate and reducing the noise interference problems caused by the installation of plated wires. In addition, it is also possible to avoid the traditional nickel / gold plating process. It is necessary to cover the entire layer of the package substrate with a metal layer containing nickel / gold, which can effectively reduce the cost of nickel / gold plating. The embodiments further illustrate the present invention in detail, but the present invention is not limited by these embodiments. In particular, the electroplated metal layer of the electrical connection pad of the present invention can be widely used. Although the package substrate in general, the drawings and description set forth flip-chip packaging substrate circumstances embodiment thereof, provided that such operation of the present invention, not to limit the
17228 全懋.ptd 第13頁 20042860517228 懋 .ptd page 13 200428605
第14頁 200428605 五、發明說明（8) 銲球墊（B a 1 1 p a d )，係用以植置多數之銲球（S〇1 d e r b a 1 1 ) 4 9 b以提供該完成覆晶封裝製程之半導體晶片5 0電性 連接至外部裝置（未圖示），如銲錫接接合於電路板。 由於該線路層4 2及電性連接墊4 4之材質一般為金屬 銅，而為提供該基板第一表面4 a與第二表面4 b上之電性連 接墊4 4，避免受外界環境影響發生氧化，或為有效與銲錫 凸塊4 9 a或銲球4 9 b之接合能力，係會在該電性連接墊4 4外 露表面電鑛有金屬層44 a作為金屬阻障層，一般的金屬阻 障層包含鎳黏著層以及形成於該電性連接墊4 4上的金保護 層。然而，該阻障層亦可藉由電鍍（Electroplating)、無 電鍍《Electroless plating)或物理氣相沈積（Physical vapor deposition)等方法，沈積金、錄、纪、銀、錫、 鎳/鈀、鉻/鈦、鈀/金或鎳/鈀/金等材質所形成之群組之 任一者。之後可形成一拒銲層4 8，.以覆蓋住該基板4表 面，且拒銲層形成有若干開孔，使電性連接墊得以顯露於 該拒銲層之開孔，其中至少有一電性連接墊4 4並未與任何 電鍍導線相連通。 ' 請參閱第4A至第4 I圖，為本發明之半導體封裝基板電 性連接墊形成電鍍金屬層之方法之示意圖。 如第4 A圖所示，首先提供一封裝基板4，該封裝基板 除可為如第3圖所示之覆晶式封裝基板，亦可為一般之打 線式（W i r e b ο n d i n g )封裝基板。該封裝基板4並已完成所 需之前段製程，例如多數之導通孔（PTH)或盲孔（B1 ind V 1 a )等（未圖示）形成於其中，該封裝基板4之表面並已形 III 1 1 II II 11 III II ii 111 11 1 IIS ί· ri 1 17228 全懋.ptd 第15頁 200428605 五、發明說明（9) 成有一已線路圖案化之線路層4 2，該線路層4 2包含有複數 個電性連接墊4 4。有關線路圖案化技術繁多，惟乃業界所 周知之製程技術，其非本案技術特徵，故未再予贅述。 如第4B圖所示，再於該基板4之表面利用印刷、旋塗 或貼合等方式覆蓋有第一阻層45。該第一阻層45可為乾膜 或膠帶等。 如第4 C圖所示，並於該第一阻層4 5上利用雷射方式燒 灼或以曝光顯影方式形成有至少一開口 4 5 a，且該開口 4 5 a 連通至鄰近之導電線路4 2。 •如第4D圖所示，接著於該第一阻層開口 45a中形成導 電膜《Electrically conductive filin)46，俾使該導電膜 ^得以電性導接鄰近之導電線路42與電性連接墊44。該導 1膜46主要作為後述進行電鍍金屬層所需之電流傳導 :徑’可由金屬、纟金或堆叠數層金屬層所構成，可選自 ，、錫、錄、鉻、鈦、銅-絡合金及錫—錯合金所構成之群 :之任一者所形&。惟依實際操作的經驗，該導電膜纖 仓係由銅或鈀粒子（特別是無電鍍）等所構成，其可藉由物 理氣相沈積（PVD)、化學氣相沈積（CVD)、無電鍍或化學沈 ，例如濺鍍（sPUttering)、蒸鍍（Evap〇raU〇n)、電弧 洛氣沈積（Arc vapor deP〇Sltl〇n)、離子束濺鍍（I〇n beam sputtering)、雷射熔散沈積（Laser abUti〇n deP0Sltl0n)、電聚促進之化學氣相沈積或有機金屬之化 學氣相沈積等方法，形成於該基板上之該第一阻層開口 4 5 a中 〇Page 14 200428605 V. Description of the invention (8) The solder ball pad (B a 1 1 pad) is used to plant a large number of solder balls (S〇1 derba 1 1) 4 9 b to provide the completed flip-chip packaging process. The semiconductor wafer 50 is electrically connected to an external device (not shown), such as soldered to the circuit board. Since the material of the circuit layer 42 and the electrical connection pad 44 is generally metallic copper, the electrical connection pad 44 on the first surface 4a and the second surface 4b of the substrate is provided to avoid being affected by the external environment. Oxidation occurs, or for effective bonding with solder bumps 4 9 a or solder balls 4 9 b, a metal layer 44 a is formed on the exposed surface of the electrical connection pad 4 4 as a metal barrier layer. General The metal barrier layer includes a nickel adhesion layer and a gold protection layer formed on the electrical connection pad 44. However, the barrier layer can also be deposited by methods such as electroplating, electroless plating, or physical vapor deposition, such as gold, copper, silver, silver, tin, nickel / palladium, and chromium. Any one of the groups consisting of titanium / palladium / gold or nickel / palladium / gold. After that, a solder resist layer 48 can be formed to cover the surface of the substrate 4, and a number of openings are formed in the solder resist layer, so that the electrical connection pad can be exposed in the openings of the solder resist layer, at least one of which is electrically conductive. The connection pad 4 4 is not in communication with any plated wire. 'Please refer to FIGS. 4A to 4I, which are schematic diagrams of a method for forming a plated metal layer on an electrical connection pad of a semiconductor package substrate of the present invention. As shown in FIG. 4A, a package substrate 4 is first provided. The package substrate may be a flip-chip package substrate as shown in FIG. 3 or a general wire-type (W i r e b o n d i n g) package substrate. The package substrate 4 has completed the required previous processes. For example, most of the via holes (PTH) or blind holes (B1 ind V 1 a) (not shown) are formed therein, and the surface of the package substrate 4 has been shaped. III 1 1 II II 11 III II ii 111 11 1 IIS ί · ri 1 17228 Quan 懋 .ptd Page 15 200428605 V. Description of the invention (9) A circuit layer 4 2 has been patterned, and the circuit layer 4 2 Contains a plurality of electrical connection pads 4 4. There are many circuit patterning technologies, but they are well-known process technologies in the industry, and they are not the technical features of this case, so I will not repeat them here. As shown in FIG. 4B, the surface of the substrate 4 is further covered with a first resistive layer 45 by printing, spin coating, or bonding. The first resistive layer 45 may be a dry film or an adhesive tape. As shown in FIG. 4C, at least one opening 4 5a is formed on the first resistive layer 45 by laser burning or exposure development, and the opening 4 5a is connected to the adjacent conductive line 4 2. • As shown in FIG. 4D, a conductive film "Electrically conductive filin" 46 is formed in the first resist opening 45a, so that the conductive film ^ can electrically conduct the adjacent conductive lines 42 and the electrical connection pads 44. . The first conductive film 46 is mainly used as the current conduction required for the electroplated metal layer described later: the diameter can be composed of metal, gold, or several metal layers stacked, and can be selected from the group consisting of tin, tin, chromium, titanium, copper Groups of alloys and tin-alloys: in the shape of either &. However, according to practical experience, the conductive film fiber silo is composed of copper or palladium particles (especially electroless plating), which can be performed by physical vapor deposition (PVD), chemical vapor deposition (CVD), and electroless plating Or chemical precipitation, such as sPUttering, evaporation (Evapora), arc vapor deporation (ion vapor deposition), ion beam sputtering (ion beam sputtering), laser melting Laser ablation (Laser abUtión de P0Slt10n), electropolymerization-promoted chemical vapor deposition, or organic metal chemical vapor deposition are used to form the first resist layer opening 4 5 a on the substrate.
17228 全懋.ptd17228 Full 懋 .ptd
第16頁 200428605 五、發明說明（ίο) 如第4E圖所示，接著，藉由化學方式（例如蝕刻），亦 或透過物理方式撕開或以雷射技術去除該基板表面之第一 阻層4 5，俾在該基板上顯露出該導電膜4 6，以作為後述在 電性連接墊上進行電鍍金屬層所需之電流傳導路徑。 如第4F圖所示，再於該基板上利用印刷、旋塗或貼合 等方式敷設第二阻層4 7，且該第二阻層4 7形成有多數開孔 4 7 a以顯露出該電性連接墊4 4。 如第4G圖所示，接著以電鍍方式（Electroplating)對 該封裝基板4進行電鍍一金屬層步驟，該電鍍金屬可為 金、錄、纪、銀、錫、錄/ί巴、鉻/鈦、錄/金、纪/金或錄 /鈀/金等所形成之群組之任一者。藉由該導電膜4 6之具導 電特性，俾在進行電鍍時可作為電流傳導路徑，較佳者為 電鍍鎳/金金屬層，其係先電鍍一層鎳後，再於其上電鍍 一層金，鎳/金金屬經由該導電膜4 6可電鍍於電性連接墊 4 4顯露之表面，使該電性連接塾4 4之顯露表面覆蓋有一電 鍍金屬層4 4 a，當然本發明電鍍金屬材質之選擇，亦可僅 為如前述之錄、金或其他金屬之一，例如直接以金電鍍於 電性連接墊4 4之顯露表面，其為簡單之替換，皆應屬本梦 明實施之範疇。 如第4 Η圖所示，俟完成電鍍鎳/金金屬層44 a於該電性 連接墊4 4之外露表面後，先移除該第二阻層4 7，接著，再 利用乾蝕刻或溼蝕刻方式將先前作為電鍍電流導通路徑之 導電膜4 6加以去除，即完成欲形成電鍍金屬層44 a覆蓋於 該電性連接墊4 4之外露表面。Page 16 200428605 V. Description of the invention (ίο) As shown in Figure 4E, then, the first resist layer on the substrate surface is removed by chemical means (such as etching), or by physical tearing or laser technology. 45. The conductive film 46 is exposed on the substrate to serve as a current conduction path required to perform the electroplated metal layer on the electrical connection pad described later. As shown in FIG. 4F, a second resistive layer 4 7 is then laid on the substrate by printing, spin coating, or bonding, and the second resistive layer 4 7 is formed with a plurality of openings 4 7 a to expose the Electrical connection pad 4 4. As shown in FIG. 4G, the packaging substrate 4 is then plated with a metal layer by electroplating. The plated metal can be gold, copper, silver, silver, tin, copper / tin, chromium / titanium, Any of the groups formed by Lu / Gold, Ji / Gold or Lu / Pd / Gold. Due to the conductive properties of the conductive film 46, rhenium can be used as a current conduction path during electroplating, preferably a nickel / gold metal layer, which is firstly plated with a layer of nickel and then plated with a layer of gold. The nickel / gold metal can be electroplated on the exposed surface of the electrical connection pad 44 through the conductive film 46, so that the exposed surface of the electrical connection 塾 4 4 is covered with a plated metal layer 4 4a. The choice can also be only one of the foregoing, gold or other metals, such as electroplating directly on the exposed surface of the electrical connection pad 44 with gold, which is a simple replacement and should fall within the scope of the implementation of this dream. As shown in FIG. 4, after the nickel / gold metal layer 44 a is electroplated on the exposed surface of the electrical connection pad 4 4, the second resist layer 4 7 is removed first, and then, dry etching or wet etching is used. The etching method removes the conductive film 46 which was previously used as the conduction path of the plating current to complete the formation of a plating metal layer 44 a to cover the exposed surface of the electrical connection pad 44.
17228 全懋.ptd 第17頁 200428605 五、發明說明（11) ' 如第4 I圖所示，之後再於該封裝基板4表面覆蓋上一 拒銲層（S ο 1 d e r m a s k ) 4 8，例如綠漆，藉以保護該封裝基 板4免受外在環境污染破壞，該拒銲層4 8並形成有複數個 開孔4 8 a，使該完成電鍍金屬層4 4 a之電性連接墊4 4得以顯 露於拒銲層之開孔4 8 a，其中，該拒銲層開孔4 8 a之孔徑可 小於該電性連接墊4 4之大小，以形成一拒銲層限定（S M D， S〇1 d e r m a s k d e f i n e d )電性連接墊，亦或該拒銲層開孔 4 8 a之孔徑係可大於該電性連接墊4 4之大小，以形成一非 拒銲層限定（NSMD， Non-solder mask defined)電性連接 塾®而覆有電鍍金屬層4 4 a之電性連接墊4 4即可供與晶片 或電路板作為電性連接之界面。 透過本發明之半導體封裝基板電性連接墊形成電鍍金 屬層之方法，不僅可提供電性連接墊之外露表面包覆有一 含鎳/金之金屬層，以有效幫助金線、銲鍚凸塊、或銲球 等與晶片或電路板之電性耦合；亦可避免該電性連接墊本 體受外界環境影響而導致之氧化；且避免習知化學鎳/金 製程時所產生之跳鍍與黑墊等問題，可有效提昇封裝結構 信賴性；同時於電鍍鎳/金時無需在封裝基板之表面佈設 導線，藉以大幅增加封裝基板有效佈線面積，並減少 西佈設電鍍導線所衍生之雜訊干擾問題；再者，亦可避免 習知電鍍鎳/金製程時，須於封裝基板之整層線路層上均 覆蓋一含錄/金之金屬層，而可有效降低電鍍録/金之成 本。 本發明之半導體封裝基板電性連接墊形成電鍍金屬層17228 Quan 懋 .ptd Page 17 200428605 V. Description of the invention (11) 'As shown in Figure 4I, the surface of the package substrate 4 is covered with a solder mask (S ο 1 dermask) 4 8 for example, green Lacquer to protect the package substrate 4 from external environmental pollution, the solder resist layer 4 8 and a plurality of openings 4 8 a are formed, so that the electrical connection pads 4 4 of the finished electroplated metal layer 4 4 a can be The opening 4 8 a exposed in the solder resist layer, wherein the hole diameter of the solder resist opening 4 8 a may be smaller than the size of the electrical connection pad 44 to form a solder resist defined (SMD, S〇1 dermaskdefined) The electrical connection pad, or the aperture of the solder resist opening 4 8 a may be larger than the size of the electrical connection pad 44 to form a non-solder mask defined (NSMD) Electrical connection 塾 ® and the electrical connection pads 4 4 covered with the electroplated metal layer 4 4 a can be used as an interface for electrical connection with a chip or a circuit board. The method for forming an electroplated metal layer through the electrical connection pad of the semiconductor package substrate of the present invention can not only provide a nickel / gold-containing metal layer on the exposed surface of the electrical connection pad to effectively help gold wires, solder bumps, Or the ball or the ball is electrically coupled to the chip or the circuit board; it can also avoid the oxidation of the electrical connection pad body due to the external environment; and avoid the jump plating and black pad produced by the conventional chemical nickel / gold process And other issues, which can effectively improve the reliability of the packaging structure; at the same time, when plating nickel / gold, there is no need to lay wires on the surface of the packaging substrate, thereby greatly increasing the effective wiring area of the packaging substrate, and reducing the noise interference problems caused by the plating of the wires on the west; Furthermore, it is also possible to avoid the need to cover the entire layer of the package substrate with a metal layer containing recording / gold during the conventional nickel / gold plating process, which can effectively reduce the cost of plating / gold. The electrical connection pad of the semiconductor package substrate of the present invention forms a plated metal layer
17228 全懋.ptd 第18頁 200428605 五、發明說明（12) 之方法中所述之電性連接墊，係例如封裝基板中之打線 墊、凸塊銲墊、預銲錫銲墊或銲球墊等，先前圖式僅以部 分電性連接墊表示，實際上該電性連接墊之數目、作為電 鍍時電流傳導路徑以及遮罩用之阻層，係依實際製程所需 而加以設計並分佈於基板表面，且該製程可實施於基板之 單一側面或雙側面。 以上所述之具體實施例，僅係用以例釋本發明之特點 及功效，而非用以限定本發明之可實施範疇，在未脫離本 發明上揭之精神與技術範疇下，任何運用本發明所揭示内 容而完成之等效改變及修飾，均仍應為下述之申請專利範 圍所涵蓋。17228 Quan 懋 .ptd Page 18 200428605 V. The electrical connection pads described in the method of the invention (12) are, for example, wire bonding pads, bump pads, pre-solder pads or ball pads in the package substrate. The previous drawing is only shown by some electrical connection pads. In fact, the number of the electrical connection pads, as a current conduction path during plating and a resist layer for the mask, are designed and distributed on the substrate according to the actual process requirements. Surface, and the process can be implemented on one or both sides of the substrate. The specific embodiments described above are only used to illustrate the features and effects of the present invention, rather than to limit the implementable scope of the present invention. Any application of the present invention without departing from the spirit and technical scope of the present invention is disclosed. Equivalent changes and modifications made by the disclosure of the invention should still be covered by the scope of patent application described below.
17228 全懋.ptd 第19頁 200428605 圖式簡單說明 【圖式簡單說明】 第1圖為利用電鍍導線於半導體封裝基板之電性連接 塾上電鍍形成有錄/金金屬層之剖面示意圖； 第2A圖至第2D圖為利用金層圖案化電鍍法（GPP)製程 於半導體封裝基板之電性連接墊上電鍍形成有鎳/金金屬 層之方法剖面示意圖； 第3圖為利用本發明中於半導體封裝基板之電性連接 墊上形成有電鍍金屬層之基板剖面示意圖；以及 第4 A圖至第4 I圖本發明之半導體封裝基板電性連接墊 電鍍金屬層之方法示意圖。 1，2 ，4 基 板 4a 第 一 表 面 4b 第 二 表 面 11 上 線 路 層 12 下 線 路 層 13 導 通 孔 14, 44 電 性 連 接 墊 15, 48 拒 銲 層 16, 23, 44a 電 鍍 金 屬層 17 電 鍍 導 線 21 導 電 層 21a 線 路 圖 案 22 光 阻 層 46 導 電 膜 絕 緣 層 42 導 ^fr· 線 路 •43 通 孔 45 第 一 阻 層 45a 第 一 阻 層 開 α 47 第 二 阻 層 47a 第 •—- 阻 層 開 48a 拒 銲 層 開孔 49a 銲 錫 凸 塊 49b 銲 球 50 半 導 體 晶 片17228 Quan 懋 .ptd Page 19 200428605 Brief Description of Drawings [Simplified Description of Drawings] Figure 1 is a schematic cross-sectional view of a recording / gold metal layer electroplated on the electrical connection of a semiconductor package substrate using plated wires; Section 2A 2D are schematic cross-sectional views of a method for forming a nickel / gold metal layer on an electrical connection pad of a semiconductor package substrate by using a gold layer pattern plating (GPP) process; and FIG. 3 is a diagram illustrating the use of the semiconductor package in the present invention. A schematic cross-sectional view of a substrate with a plated metal layer formed on an electrical connection pad of the substrate; and FIGS. 4A to 4I are schematic views of a method for plating a metal layer on the electrical connection pad of a semiconductor package substrate of the present invention. 1,2,4 Substrate 4a First surface 4b Second surface 11 Upper wiring layer 12 Lower wiring layer 13 Vias 14, 44 Electrical connection pads 15, 48 Solder resist layers 16, 23, 44a Plating metal layer 17 Plating wire 21 Conductive layer 21a, circuit pattern 22, photoresist layer 46, conductive film insulation layer 42, conductive line 43, through-hole 45, first resistive layer 45a, first resistive layer α 47, second resistive layer 47a, first resistive layer 48a Solder mask opening 49a Solder bump 49b Solder ball 50 Semiconductor wafer
17228 全懋.ptd 第20頁17228 懋 .ptd Page 20
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW092115796A TWI307547B (en) | 2003-06-11 | 2003-06-11 | Method for fabricating substrate with plated metal layer over pads thereon |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW092115796A TWI307547B (en) | 2003-06-11 | 2003-06-11 | Method for fabricating substrate with plated metal layer over pads thereon |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW200428605A true TW200428605A (en) | 2004-12-16 |
| TWI307547B TWI307547B (en) | 2009-03-11 |
Family
ID=45071617
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW092115796A TWI307547B (en) | 2003-06-11 | 2003-06-11 | Method for fabricating substrate with plated metal layer over pads thereon |
Country Status (1)
| Country | Link |
|---|---|
| TW (1) | TWI307547B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI406342B (en) * | 2009-04-30 | 2013-08-21 | Lg Innotek Co Ltd | Semiconductor package with nsmd type solder mask and method for manufacturing the same |
-
2003
- 2003-06-11 TW TW092115796A patent/TWI307547B/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI406342B (en) * | 2009-04-30 | 2013-08-21 | Lg Innotek Co Ltd | Semiconductor package with nsmd type solder mask and method for manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI307547B (en) | 2009-03-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4682294B2 (en) | Semiconductor package substrate structure having electrical connection pad metal protective layer and manufacturing method thereof | |
| US7396753B2 (en) | Semiconductor package substrate having bonding pads with plated layer thereon and process of manufacturing the same | |
| CN100342526C (en) | Semiconductor sealing baseplate structure of electric padding metal protective layer and producing method thereof | |
| US7754598B2 (en) | Method for manufacturing coreless packaging substrate | |
| US6576540B2 (en) | Method for fabricating substrate within a Ni/Au structure electroplated on electrical contact pads | |
| US20090308652A1 (en) | Package substrate having double-sided circuits and fabrication method thereof | |
| US6916685B2 (en) | Method of plating metal layer over isolated pads on semiconductor package substrate | |
| US7012019B2 (en) | Circuit barrier structure of semiconductor packaging substrate and method for fabricating the same | |
| US7041591B1 (en) | Method for fabricating semiconductor package substrate with plated metal layer over conductive pad | |
| JP2007214534A (en) | Manufacturing method of circuit board having conductive structure | |
| JP2008004924A (en) | Manufacturing method of package substrate | |
| JP2008085089A (en) | Resin wiring board and semiconductor device | |
| US7253364B2 (en) | Circuit board having electrically conductive structure formed between circuit layers thereof and method for fabricating the same | |
| US7817441B2 (en) | Circuit board | |
| US20090102050A1 (en) | Solder ball disposing surface structure of package substrate | |
| US7544599B2 (en) | Manufacturing method of solder ball disposing surface structure of package substrate | |
| US20070186413A1 (en) | Circuit board structure and method for fabricating the same | |
| JP3860028B2 (en) | Semiconductor device | |
| TWI301662B (en) | Package substrate and the manufacturing method making the same | |
| JP2005244104A (en) | Manufacturing method of wiring board | |
| TWI224387B (en) | Semiconductor package substrate with protective layer on pads formed thereon and method for fabricating the same | |
| TW200428605A (en) | Method for fabricating substrate with plated metal layer over pads thereon | |
| TW571372B (en) | Substrate with plated metal layer over pads thereon, and method for fabricating the same | |
| TW569360B (en) | Method for plating metal layer over pads on substrate for semiconductor package | |
| WO2023210815A1 (en) | Wiring board, semiconductor device, and method for producing wiring board |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MM4A | Annulment or lapse of patent due to non-payment of fees |