JP2005244104A - Manufacturing method of wiring board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method for efficiently obtaining a wiring board, in which a dielectric layer made of a polymer material and a conductive layer are alternately laminated, without having core materials. <P>SOLUTION: The following processes are performed, in this order, namely, a covering process for covering the first main surface MP1 of a metal plate 2 used as a support substrate for reinforcement in manufacture with a metal thin-film layer 3 having selective etching properties to the metal plate 2; a lamination process for forming a conductive pattern 11 for forming a metal terminal pad on the first main surface MP2 of the metal thin-film layer 3, and forming a wiring laminated section 10, by alternately laminating the dielectric layer made of a polymer material and the metal conductive layer, after the covering process; and an etching process for removing the metal plate 2 by selective etching, removing the metal thin-film layer 3 by selective etching, and exposing a conductive pattern 11 formed at the side of the first main surface MP2 of the metal thin-film layer 3, after the lamination process. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a wiring board having no core substrate.

  In recent years, due to the demand for higher functionality and lighter, thinner and smaller electronic devices, high-density integration has rapidly progressed in electronic components such as IC chips and LSIs. There is a demand for higher-density wiring and multi-terminals than ever before.

  As such a package substrate, a build-up multilayer wiring substrate is currently used. The build-up multilayer wiring board uses a rigid property of an insulating core substrate (glass epoxy substrate such as FR-4) in which a reinforcing fiber is impregnated with a resin, and is made of a polymer material on both main surfaces thereof. A build-up layer in which dielectric layers and conductor layers are alternately arranged is formed. In such a build-up multilayer wiring board, high-density wiring is realized in the build-up layer, while the core board plays a reinforcing role. For this reason, the core substrate is configured to be very thick compared to the buildup layer, and the wiring inside it (for example, referred to as a through-hole conductor) for establishing conduction between the buildup layers disposed on the respective main surfaces Are formed penetrating in the thickness direction. However, at the present time when the signal frequency to be used has become a high frequency band exceeding 1 GHz, there is a problem that the wiring penetrating such a thick core substrate contributes as a large inductance.

  Therefore, in order to solve such a problem, there has been proposed a wiring board mainly composed of a build-up layer that does not have a core board and can be formed with high density wiring, as shown in Patent Document 1. In such a wiring board, since the core board is omitted, the entire wiring length is short, which is suitable for high-frequency applications. Regarding the method for manufacturing such a wiring board, there are descriptions in paragraphs 0012 to 0029 and FIGS. 1 to 4 of Patent Document 1, and first, a plating resist is formed on the main surface of the metal plate, and this is used as a mask to form the metal plate. A resist metal layer having selective etching property and a conductor layer forming a wiring pattern are laminated in this order by electrolytic plating. Next, a buildup layer having a dielectric layer and a conductor layer is formed on the wiring pattern. After the lamination, the metal plate and the resist metal layer are removed by etching. Thereby, it is said that it is possible to obtain a thin build-up layer having no core substrate.

JP 2002-26171 A

  However, when a wiring board is manufactured by the manufacturing method as described above, a metal plate that is a support substrate and a resist metal layer may be alloyed by a heat treatment in the manufacturing process to form a new alloy layer. There is a problem that the etching process of the layer including the formed alloy layer takes more time than usual.

  The present invention has been made in view of the above problems, and it is possible to efficiently obtain a wiring board in which dielectric layers and conductor layers made of a polymer material are alternately laminated without having a core substrate. It is an object to provide a simple manufacturing method.

Means for solving the problem, operation and effect of the invention

In order to solve the above problems, in the method for manufacturing a wiring board of the present invention,
A coating step of coating a metal thin film layer having selective etching properties on the first main surface of a metal plate used as a support substrate for reinforcement during production;
After the coating step, a conductor pattern forming a metal terminal pad is formed on the first main surface of the metal thin film layer, and dielectric layers and metal conductor layers made of a polymer material are alternately laminated to form a wiring laminate. A laminating process for forming a portion;
After the laminating step, the metal plate is removed by selective etching, and then the metal thin film layer is removed by selective etching, thereby exposing the conductor pattern formed on the first main surface side of the metal thin film layer. Etching process;
Are performed in this order.

  In a conventional method of manufacturing a wiring board in which a buildup layer is laminated using a metal plate as a support substrate, a metal plate such as the resist metal layer 103 shown in paragraph 0014 of FIG. 1 and FIG. An etching guard metal having an etching selection ratio different from the above is previously formed in a predetermined pattern. Next, as shown in FIG. 1C, a conductive pattern such as a wiring pattern 104 is formed in close contact with the etching guard metal. Thereby, a conductor pattern is protected from the etching liquid used at the time of metal plate etching, and the erosion, corrosion, etc. can be prevented. However, according to the method for manufacturing a wiring board of the present invention, it is not necessary to form an etching guard metal that fulfills the above-described role. Instead, the metal thin film layer is formed so as to cover the entire first main surface of the metal plate. Can do.

  When a buildup layer is laminated using a metal plate as a support substrate, a Cu plate is often used as the metal plate. In this case, since the Cu plate needs to function as a support substrate at the time of lamination, a relatively thick one is used (for example, about 0.8 mm for a Cu plate). When etching such a Cu plate, there is a case where a chemical solution having strong corrosivity and a higher concentration than usual is used for shortening the etching time. However, as described in Patent Document 1, when the metal plate and the dielectric layer are formed in close contact with each other, the etching solution for the metal plate is in contact with the dielectric layer, and at this time, even if the dielectric layer is corroded. Even a material that is resistant to damage may damage the dielectric layer. According to the present invention, the etching process of the thick Cu plate stops at the surface of the metal thin film layer, and the high concentration chemical does not come into contact with the dielectric. In the subsequent etching of the metal thin film layer, since the metal thin film layer is a thin layer, it is not necessary to use a high concentration chemical solution, and damage to the dielectric layer can be greatly reduced.

  The metal thin film layer formed in the method for manufacturing a wiring board of the present invention can be characterized by being made of a metal material composed of at least one of Ti, Cr, Al, Ag, and Sn. According to the method for manufacturing a wiring board described in Patent Document 1, for example, when a metal plate is a Cu plate and an etching guard metal is formed by Ni / Au plating, Cu and Au are used in various heat treatment steps during lamination. May be alloyed and a new alloyed layer may be formed near the interface. An alloy layer made of a metal material of such a metal plate and an etching guard metal may have a high selection ratio with respect to an etching solution used at the time of etching the metal plate. In such a case, the etching time of the metal plate increases. However, the processing capability of the etching process is greatly reduced. In some cases, a new etching process is required to etch the alloy layer, which may increase the number of processes. According to the present invention, by forming the metal thin film layer made of the above-described metal material, the metal thin film layer has the same effect as the etching guard metal, and the alloy is also obtained by each heat treatment in the manufacturing process. Therefore, it is not necessary to increase the etching time of the metal plate by alloying or add an etching process.

  In the method for manufacturing a wiring board according to the present invention, the first main surface of the metal thin film layer is coated with a thin film layer that has selective etching properties with respect to the metal thin film layer and that can be surface roughened. In addition, the thin film layer may be characterized in that the first main surface is subjected to a roughening treatment. According to this, when the adhesion between the metal thin film layer and the build-up layer formed thereon is poor, the thin film layer is formed on the first main surface of the metal thin film layer, and the surface is roughened. Thereby, it becomes possible to improve adhesiveness with the buildup layer laminated | stacked on a metal thin film layer.

BEST MODE FOR CARRYING OUT THE INVENTION

  Hereinafter, embodiments of the present invention will be described. FIG. 1 shows a cross section of a wiring board 100 formed by the method for manufacturing a wiring board of the present invention. A separately formed electronic component IC is mounted on the solder bump FB. Hereinafter, an embodiment of a method for manufacturing the wiring substrate 100 shown in FIG. 1 will be described with reference to FIGS.

  In step 1 of FIG. 2, the metal thin film layer 3 is coated on the first main surface MP1 of the metal plate 2 serving as a support substrate by, for example, one-side sputtering treatment (coating step). Here, the metal plate 2 needs to be formed of a metal material that can be removed by etching, for example, Cu, Cu alloy, SUS (JIS standard), Ni, Fe-Ni alloy, Al, Al alloy, Invar, An Invar alloy or the like can be used. Further, the metal thin film layer 3 has a selective etching property with respect to the metal plate 2 and is difficult to be alloyed with the metal plate 2 by various heat treatments at the time of manufacturing the wiring board, such as Ti, Cr, Al, Ag, Sn, etc. A material comprising at least one of the above can be used. In the present embodiment, a copper plate (Cu) is used as the metal plate, and Ti is used as the metal thin film layer.

  Next, as shown in step 2, the first main surface MP2 of the metal thin film layer 3 is laminated (bonded) with an ultraviolet-sensitive dry film resist 4, and then patterned using exposure and development by ultraviolet irradiation. To do. Then, using the patterned dry film resist 4 as a mask, a conductor pattern 11 (first metal conductor layer M1) to be a metal terminal pad is formed. The conductor pattern 11 formed at this time needs to be resistant to an etching solution in the etching process of the metal thin film layer 3 to be described later. For example, copper, nickel, gold, tin, silver, palladium, or the like can be used. . In the present embodiment, a conductor pattern mainly composed of Cu is formed by electrolytic plating.

  In step 3, the dry film resist 4 used as a mask in step 2 is removed by etching. At this time, if a roughening process is performed on the exposed surface of the conductor pattern 11 before the etching process, the adhesiveness between the resin film 30 laminated on the conductor pattern 11 and the conductor pattern 11 in step 4 is determined. Can be improved.

  Subsequently, in Step 4 shown in FIG. 3, a thermosetting resin film 30 is laminated on the upper layer of the first metal conductor layer M1, and a first dielectric layer B1 is formed by performing a curing process. Then, a hole is formed in a predetermined position of the resin film 30 using a laser, for example, to form a via opening (hereinafter also referred to as a via hole). In addition, the resin film 30 can be comprised, for example with the material which has an epoxy as a main component, and can be formed by the known vacuum lamination method.

  In step 5, the first via conductor 21 belonging to the first metal conductor layer M1 is formed in the via hole of the first dielectric layer B1 formed in step 4, and the first main conductor of the first dielectric layer B1 is formed. A conductor pattern 12 (second metal conductor layer M2) including wiring is formed on the surface. At this time, the first via conductor 21 connects the first metal conductor layer M1 to the second metal conductor layer M2 formed on the first main surface of the first dielectric layer B1.

  In step 6, the above-described steps 2 to 5 are repeated, and the build-up layer (wiring laminate portion) 10 is formed by sequentially laminating the dielectric layer and the metal conductor layer (lamination step). In this embodiment, a solder resist layer SR (fourth dielectric layer B4) is formed on the outermost layer in the buildup layer 10. An opening is formed in the solder resist layer SR, and the conductor pattern 14 (fourth metal conductor layer M4) formed immediately below is exposed. At this time, the conductor layer pattern 14 is a conductor pattern to be a metal terminal pad.

  In the present embodiment, the buildup layer 10 is composed of the metal conductor layers M1 to M4 and the dielectric layers B1 to B4. However, the number of the metal conductor layers and the dielectric layers is not limited to this. Absent. The conductor patterns 11 to 14 and the via conductors 21 to 23 formed in the metal conductor layers M1 to M4 are mainly composed of Cu, for example.

  In addition, the via conductor formed in the buildup layer 10 is different from the laser processing as described above, for example, a via hole is formed by a well-known photo via process, and the via hole is electrolessly formed by, for example, a semi-additive method. It can also be obtained by filling by plating. In this case, each dielectric layer needs to be formed of at least a photosensitive resin film.

  Next, as shown in step 7 of FIG. 4, the metal plate 2 that has played the role of the support substrate at the time of stacking is selectively removed by wet etching using, for example, an etching solution (etching step). At this time, the metal thin film layer 3 functions as an etch stop layer. The etching solution used here has a high concentration so that the etching selectivity is different between the materials of the metal plate 2 and the metal thin film layer 3, particularly a large one is appropriately used, and the etching time is shortened. It is better to use the chemical solution.

  In step 8, the metal thin film layer 3 is selectively removed by wet etching, for example, as in step 7 (etching step). As the etching solution used here, one having a different etching selectivity ratio between the respective materials of the metal thin film layer 3 and the conductor pattern 11 of the first metal conductor layer M1, and particularly a large one may be appropriately used. As a result, the conductor pattern 11 is exposed on the second main surface of the first metal conductor layer. In this embodiment, the conductor pattern 11 mainly composed of Cu is exposed, and the exposed surface can be used as it is as a metal terminal pad.

  In step 9, a plated surface layer 7 made of, for example, Ni—Au plating or Sn (solder) plating is formed on the exposed surface of the conductor pattern 14 by electrolytic plating or electroless plating. Solder bumps FB are formed on the plated surface layer 7 thus formed, thereby forming connection terminals that connect to the electronic component IC shown in FIG. When the process in step 9 is completed, the main surface is not formed of a dielectric layer, and the dielectric layers B1 to B4 and the conductor layers M1 to M4 made of a polymer material are alternately formed. It is possible to obtain a thin wiring substrate formed by lamination.

  The wiring board 100 shown in FIG. 1 is mounted on the wiring board obtained through the above steps 1 to 9 so that the electronic component IC is connected to the solder bumps FB. The gap under the electronic component IC is filled with an underfill material UF, and a reinforcing frame (stiffener) is formed on the first main surface of the fourth dielectric layer B4 so as to surround the mounting portion of the electronic component IC. ST is installed. As the metal material of the reinforcing frame ST, Cu, Cu alloy, SUS (JIS standard), Ni, Fe—Ni alloy, Al, Al alloy, Invar, Invar alloy, or the like can be used.

  In the present embodiment, the adhesion between the metal thin film layer 3 and the buildup layer 10 may be weak. In such a case, there is a possibility that the metal plate 2 cannot function as a support substrate when manufacturing the wiring board. As a means for enhancing the adhesion between the layers, there is a roughening treatment of the layer surface. However, when the metal thin film layer 3 is made of Ti or the like, it is difficult to roughen the surface due to its properties. In such a case, in Step 1, after forming the film of the metal thin film layer 3, the thin film layer 3 'is formed immediately above it with a material that is easy to roughen, such as Cu, and the first main surface is roughened. It should be processed. Thereby, the contact | adherence surface of thin film layer 3 'and the buildup layer 10 can obtain favorable contact | adhesion intensity | strength. The thin film layer 3 ′ needs to be removed by etching after the metal thin film layer 3 is removed by etching in Step 7. However, when the thin film layer 3 ′ is made of the same Cu as the main component of the conductor pattern 11, a part of the conductor pattern 11 may be etched by the etching process of the thin film layer 3 ′. However, since the thin film layer 3 'is formed thin, it is easy to suppress excessive etching of the conductor pattern 11 depending on the selection of the etching solution. On the other hand, it is more effective that the exposed surface of the conductor pattern 11 is slightly etched because it is easy to specify the pad conductor formation position when forming the metal terminal pad.

  Further, regarding the strengthening of the adhesion between the metal thin film layer 3 and the buildup layer 10, it is possible to form a coupling agent film on the metal thin film layer 3 instead of the thin film layer 3 ′ as described above. For example, in the case of a silane coupling agent film, a functional group (vinyl group, amino group, epoxy group, imidazole group, etc.) that can be bonded to the organic material constituting the insulating layer, and a conductor or wiring pattern are configured. Since it has a functional group (a hydroxyl group, a methoxy group, an ethoxy group, or the like) that can be bonded to an inorganic material, it is suitable for enhancing adhesion. However, there is a possibility that a suitable coupling agent film cannot be selected depending on the metal material or the like of the selected metal thin film layer 3.

  In addition, if this invention makes the process 1, the process 7, and the process 8 in the said embodiment essential, at least the objective of this invention will be achieved. The present invention is not limited to the above-described manufacturing method described with reference to FIGS. 2 to 4, and various modifications or improvements can be added without departing from the technical scope based on the description of the claims. Can do. Then, after making the said embodiment into 1st embodiment, the typical thing of other embodiment concerning this invention is demonstrated below.

  FIG. 5 shows a second embodiment of the present invention. The first dielectric layer is composed of a lower first dielectric layer on the support substrate side and an upper first dielectric layer formed thereon. The conductor layer and the dielectric layer are laminated so that the main surface does not have a core substrate and both main surfaces are composed of dielectric layers, and the dielectric that forms at least one main surface. A method of manufacturing a wiring board having a metal terminal pad formed in an opening of a body layer, wherein a support (metal plate) is used for reinforcement at the time of manufacture, and a lower first is formed on the main surface of the support. A dielectric layer is formed, an opening is formed at a predetermined position of the lower first dielectric layer, and a covered conductor portion to be the metal terminal pad is formed so as to cover a region including a wall portion and a bottom portion of the opening. Forming a metal terminal pad and an upper first dielectric layer formed on the lower first dielectric layer. A body layer is formed by laminating a via conductor forming step of forming a via conductor connected to a portion of the covered conductor portion that covers the bottom of the opening, and a remaining conductor layer and a dielectric layer that constitute the wiring board. A wiring board formed on the basis of a method for manufacturing a wiring board, wherein a laminating process and a support removing process for removing the support after the laminating process are performed in this order. The wiring board of FIG. 5 has a structure in which the conductor pattern 11 is different from that of the first embodiment, and the conductor layer and the dielectric layer are laminated so that both main surfaces are composed of the dielectric layers. And a wiring board having a metal terminal pad formed in an opening of the dielectric layer forming at least one main surface, wherein the metal terminal pad (covered conductor portion) has an exposed surface in the opening. And a pad body that is via-connected to the conductor layer inside the wiring board on the back surface of the exposed surface, and is formed along the wall of the opening from the outer edge of the pad body toward the inner layer of the wiring board. And a wall surface conductor portion. Hereinafter, a method for manufacturing the wiring substrate 200 shown in FIG. 5 will be described with reference to FIGS.

  Step 1 shown in FIG. 6 is the same as step 1 in the first embodiment. In step 2, the resin film 30 is laminated on the main surface of the metal thin film layer 3 coated on the metal plate 2 forming the support substrate, and a via opening is formed to form the lower first dielectric layer B1a and To do. The resin film 30 may be a photosensitive resin film such as a provi coat film. In this case, after lamination, the resin film 30 is subjected to patterning processing based on a well-known photo via process, and the lower first dielectric layer B1a. Form. Next, in Step 3, a conductor pattern 11a (first metal conductor layer M1) having a pattern as in Step 3 of FIG. 6 is formed. In order to form the conductor pattern 11a, first, an electroless plating process is performed so as to cover the outermost layer composed of the resin film 30 patterned in Step 2 and its opening. Further, a plating resist (not shown) is formed on the electroless plating layer (not shown), and this is patterned. After the electrolytic plating process is performed using the patterned plating resist as a mask, the plating resist is removed, and then the formed electrolytic plating layer 11a is masked again with a plating resist (not shown) to form an unmasked region. The electroless plating layer is removed, and a plating resist layer (not shown) is removed. Thereby, the conductor pattern 11a can be formed. The conductor pattern 11a formed in this way is formed so as to cover the side surface side and the upper surface side of the wall portion of the opening (step 2 in FIG. 6) of the resin film 30, and the wall surface conductor portion covering this wall portion. Has a bowl shape. In step 4 of FIG. 7, the resin film 30 is laminated so as to cover the conductor pattern 11a, and the upper first dielectric layer B1b is formed. A via opening is formed in the upper first dielectric layer B1b. The via opening is formed so as to be connected to the center of the bottom surface of the conductor pattern 11a as shown in step 4 of FIG.

  In step 5 and subsequent steps, as shown in FIG. 7, the build-up layer 10a is laminated in steps 5 and 6, and in steps 7 and 8 shown in FIG. 8, the metal plate 2 and the metal thin film layer 3 are removed by etching. In step 9, connection terminals and the like are formed. Since these are the same as Step 5 to Step 9 of the first embodiment, description thereof will be omitted. When the process up to step 9 is completed and the mounting of the electronic component IC and the installation of the reinforcing frame (stiffener) ST are completed, the wiring board 200 of FIG. 5 is obtained.

  In the production of such a thin buildup layer, not only in the present invention, the internal stress generated in the buildup layer laminating step, the supporting substrate (metal plate) removing step, and the manufacturing step after removing the supporting substrate is supported. It tends to concentrate on the interface between the conductor pattern in close contact with the substrate (for example, a metal plate) and the dielectric layer formed immediately above. Therefore, defects such as cracks are easily induced from such an interface. Therefore, in a method for manufacturing a wiring board having a thin build-up layer, some measures may be required for such a problem of crack generation. In the present invention, defects such as cracks may occur from the interface between the support in which the metal thin film layer is formed on the first main surface of the support substrate and the dielectric layer in close contact with the support. The invention may also require measures against such problems. The second embodiment shows one embodiment that solves such a problem, and according to this, the adhesion area between the conductor pattern of the first metal conductor layer M1 and the resin film 30 of the first dielectric layer B1 is reduced. 1 is ensured larger than the first embodiment shown in FIG. 1, and the concentration of internal stress can be reduced.

  FIG. 9 shows a wiring board 300 representing the third embodiment of the present invention. The wiring board 100 (FIG. 1) of the first embodiment has a build-up layer formed with the stacking direction reversed. It is characterized by being. As shown in FIGS. 2 to 4 and FIGS. 6 to 8, the present invention does not necessarily need to be laminated from the connection surface side with the mother board or another wiring board, and may be laminated from the electronic component IC mounting side. If only the formation of the connection terminals after the build-up layer lamination and the installation position of the reinforcing frame (stiffener) ST are taken into consideration, there is no problem regardless of which side is formed. In FIG. 9, unlike the first and second embodiments, solder balls SB are formed on the conductor pattern 14. A solder bump FB is formed on the exposed surface of the conductor pattern 11 and an electronic component IC is mounted. The installation position of the reinforcing frame (stiffener) ST is also formed on the first dielectric layer side. Since the other structure is the same as that of the first embodiment, except for the steps of forming the solder bumps FB and the solder balls SB and installing the reinforcing frame (stiffener) ST, the same as the first embodiment. It can be formed through a manufacturing process. Therefore, the description about the manufacturing method of 3rd embodiment is abbreviate | omitted.

  FIG. 10 shows a wiring board 400 according to the fourth embodiment of the present invention. In the fourth embodiment, as in the third embodiment, the build-up layer and the first embodiment are formed with the stacking direction reversed. In the stacking process, the difference from the first embodiment is described. Have. A method for manufacturing the wiring substrate 400 shown in FIG. 10 will be described below with reference to FIGS.

  In this case, step 1 in FIG. 11 is the same as step 1 in FIG. 1 of the first and second embodiments. In step 2, the resin film 30 is laminated directly on the metal thin film layer 3 coated on the metal plate 2, and the first dielectric layer B1 of FIG. 10 is formed by performing a curing process. In a predetermined position of the resin film 30, for example, a hole is formed by using a laser, and an opening for forming a conductor region for flip chip connection with an electronic component (hereinafter also referred to as an FC opening) is formed. . In step 3, a metal material is embedded in the FC opening by a well-known filled via method, for example. Here, a metal material containing Cu as a main component is embedded. After embedding, an ultraviolet-sensitive dry film resist 4 is laminated (bonded) to the entire exposed surface including the first main surface of the first dielectric layer, followed by patterning using exposure and development by ultraviolet irradiation. To do. Then, using the patterned dry film resist 4 as a mask, the conductor pattern 12 (first metal conductor layer M2) is formed. In addition, although it has shown by FIG. 12 about the process after 4th, since the process similar to the process 5-the process 9 of 1st embodiment is performed, description is abbreviate | omitted. Thereby, the buildup layer 10b can be formed. As shown in FIG. 10, solder balls SB are formed on the exposed surface of the conductor pattern 14 formed on the build-up layer 10b via the plated surface layer 7 and a reinforcing frame (stiffener) ST is installed. The wiring board 400 can be formed.

  In the fourth embodiment, when it is desired to form the plating surface layer 7 only on the exposed surface of the conductor pattern 14, an electrolytic Ni—Au plating process is performed immediately before the etching process of the metal plate 2 in step 5 shown in FIG. It is also possible to do this. However, in this case, as shown in FIG. 13, it is necessary to perform electrolytic plating after covering the entire exposed surfaces of the Cu plate 2 and the metal thin film layer 3 with the plating resist 6. Thereby, for example, a solder ball can be formed through the plated surface layer 7 formed here, and the plated surface layer 7 is not formed on the exposed surface of the conductor pattern 11. The same applies to the third embodiment, and the electrolytic Ni—Au plating process is performed by the method described above immediately before the etching process of the metal plate 2 to form the plated surface layer 7 only on the exposed surface of the conductor pattern 14. Can do. In the case of performing this electrolytic plating process, for example, as shown in FIG. 13, any one of the plurality of exposed surfaces or a metal of the conductor pattern 14 electrically connected to each other through the metal plate 2 is used. This can be done by supplying a current from the plate 2 (in FIG. 13, the current is supplied from the plating bar 70 to one exposed surface of the conductor pattern 14). The plating resist 6 is removed by etching after the electrolytic Ni—Au plating process.

The figure which shows the outline of the cross-sectional structure of the wiring board manufactured by the manufacturing method of the wiring board which is 1st embodiment of this invention. The figure showing the process of the manufacturing method of the wiring board which is 1st embodiment of this invention. The figure following FIG. The figure following FIG. The figure which shows the outline of the cross-sectional structure of the wiring board manufactured by the manufacturing method of the wiring board which is 2nd embodiment of this invention. The figure showing the process of the manufacturing method of the wiring board which is 2nd embodiment of this invention. The figure following FIG. The figure following FIG. The figure which shows the outline of the cross-section of the wiring board manufactured by the manufacturing method of the wiring board which is 3rd embodiment of this invention. The figure which shows the outline of the cross-section of the wiring board manufactured by the manufacturing method of the wiring board which is 4th embodiment of this invention. The figure showing the process of the manufacturing method of the wiring board which is 4th embodiment of this invention. The figure following FIG. The figure showing formation of the plating surface layer on the metal terminal pad by an electrolytic plating process.

Explanation of symbols

100, 200, 300, 400 Wiring board 2 Metal plate (Cu plate)
3 Metal thin film layer 10, 10a, 10b Wiring laminate (build-up layer)
11, 11a, 12, 13, 14 Conductor pattern 21, 22, 23 Via conductor 30 Resin film SR Solder resist FB Solder bump SB Solder ball ST Reinforcement frame (stiffener)

Claims (1)

A coating step of coating a metal thin film layer having selective etching properties on the first main surface of a metal plate used as a support substrate for reinforcement during production;
After the coating step, a conductor pattern forming a metal terminal pad is formed on the first main surface of the metal thin film layer, and dielectric layers and metal conductor layers made of a polymer material are alternately laminated to form a wiring laminate. A laminating process for forming a portion;
After the stacking step, the metal plate is removed by selective etching, and then the metal thin film layer is removed by selective etching, thereby exposing the conductor pattern formed on the first main surface side of the metal thin film layer. Etching process;
A method of manufacturing a wiring board, wherein the steps are performed in this order.

Images