JP4445777B2 - Wiring board and method for manufacturing wiring board - Google Patents

Description

  The present invention relates to a wiring board and a manufacturing method thereof.

  In recent years, due to the demand for higher functionality and lighter, thinner and smaller electronic devices, high-density integration has rapidly progressed in electronic components such as IC chips and LSIs. There is a demand for higher-density wiring and multi-terminals than ever before.

  As such a package substrate, a build-up multilayer wiring substrate is currently used. The build-up multilayer wiring board uses a rigid property of an insulating core substrate (glass epoxy substrate such as FR-4) in which a reinforcing fiber is impregnated with a resin, and is made of a polymer material on both main surfaces thereof. A build-up layer in which dielectric layers and conductor layers are alternately arranged is formed. In such a build-up multilayer wiring board, high-density wiring is realized in the build-up layer, while the core board plays a reinforcing role. For this reason, the core substrate is configured to be very thick compared to the buildup layer, and the wiring inside it (for example, referred to as a through-hole conductor) for establishing conduction between the buildup layers disposed on the respective main surfaces Are formed penetrating in the thickness direction. However, at the present time when the signal frequency to be used has become a high frequency band exceeding 1 GHz, there is a problem that the wiring penetrating such a thick core substrate contributes as a large inductance.

  Therefore, in order to solve such a problem, there has been proposed a wiring board mainly composed of a build-up layer that does not have a core board and can be formed with high density wiring, as shown in Patent Document 1. In such a wiring board, since the core board is omitted, the entire wiring length is short, which is suitable for high-frequency applications. In order to manufacture such a wiring board, as described in paragraphs 0012 to 0029 and FIGS. 1 to 4, the metal plate is used to compensate for the mechanical strength of the buildup layer. After the buildup layer is formed thereon, only the thin film buildup layer is obtained by etching the metal plate. This build-up layer is used as a wiring board.

JP 2002-26171 A

  However, as described above, when a metal plate is formed as a support substrate in order to compensate for the mechanical strength of the buildup layer, the metal plate is compared to the in-plane region of the buildup layer as in the conventional core substrate. Therefore, when an external force is applied, there is a problem that stress tends to concentrate near the interface between the conductor layer and the insulator layer in the buildup layer. In particular, as shown in the schematic diagram of FIG. 4, when the surface of the metal pad layer is exposed, the area of adhesion with the insulator layer is small, so that when stress is concentrated, defects such as cracks and delamination are particularly generated. This is an area that is likely to occur.

  As described above, when defects such as cracks and delamination occur in the vicinity of the interface between the conductor layer and the insulator layer in the buildup layer, the quality such as electrical characteristics required for the buildup layer cannot be made desired, If the defect becomes excessive, the manufactured multilayer wiring board will be handled as a defective product, resulting in a decrease in yield.

  The present invention has been made in view of the above problems, and is intended for a multilayer wiring board that does not have a core substrate and uses a build-up layer as a multilayer wiring layer, and improves the quality of the electrical characteristics of the build-up layer. It is an object to provide a multilayer wiring board suitable for the above.

Means for solving the problem, operation and effect of the invention

In order to solve the above problems, the wiring board of the present invention is:
A conductor layer and a dielectric layer are laminated so that both main surfaces are composed of dielectric layers, and a wiring having a metal terminal pad formed in an opening of the dielectric layer forming at least one main surface A substrate,
The metal terminal pad has an exposed surface in the opening, and a pad body that is via-connected to the conductor layer inside the wiring board on the back surface of the exposed surface, and an inner layer of the wiring board from an outer edge of the pad body It is comprised by the wall surface conductor part formed along the wall part of the said opening in a direction, It is characterized by the above-mentioned.

  The feature of the present invention is that, as shown in FIG. 1, in a wiring board in which a conductor layer and a dielectric layer are laminated, a conductor pattern having a conductor structure as shown in FIG. 2 on at least one of its main surfaces. Is formed. This conductor structure is formed as a metal terminal pad, and FIG. 2 is an enlarged sectional view of the metal terminal pad. The metal terminal pad PD has an exposed surface in an opening formed in the lower dielectric layer Ba, and a pad body PDa via-connected to a conductor layer in the wiring board to be formed on the back surface thereof, and the pad body PDa A conductor structure composed of an extended conductor portion (wall surface conductor portion) PDb extending from the outer edge of the wiring substrate in the inner layer direction of the wiring board to be formed. This conductor structure is connected to the via conductor VA in the upper dielectric layer Bb formed in close contact with the lower dielectric layer Ba at the center upper portion of the pad body PDa. Further, the lower surface of the pad main body PDa shown in FIG. 2 functions as a pad surface responsible for connection to an external substrate.

  FIG. 4 shows a cross section of a conventional metal terminal pad (hereinafter also referred to as a pad). The metal terminal pad PD of FIG. 4 has a conductor structure composed only of the pad body PDa of the metal terminal pad PD of the present invention shown in FIG. In this case, the internal stress tends to concentrate at the interface between the pad conductor structure and the dielectric layer, particularly the interface within the broken lines A and B in the figure. Therefore, in the region A in the figure, cracks extending in the inner layer direction of the wiring board as shown in the figure are likely to occur in the dielectric layer in close contact with the pad, starting from the interface between the pad and the dielectric layer. In the region B, the dielectric layer Ba is easily peeled off from the wall surface of the pad PD (also referred to as delamination or delamination). These cracks and delamination are caused by expansion and contraction of the low thermal expansion coefficient pad and the high thermal expansion coefficient dielectric layer based on the respective thermal expansion coefficients by heating and cooling during the lamination process at the time of wiring board manufacture and after lamination. Is caused by applying internal stress to the interface between the two.

  Further, in the laminating process for manufacturing a wiring board having no core substrate as shown in FIG. 1, the exposed surface side of the pad is in close contact with a support having a certain degree of rigidity, and supports the build-up layer and the like to be laminated. There are many cases. In this case, in the laminating step, the rigid support supports the internal stress generated by the expansion and contraction of the dielectric layer, but this support is removed after the laminating step. At this time, in addition to the internal stress generated in the laminating process, a part of the stress supported by the support is also added to the region B in the figure, so at the interface between the pad and the dielectric layer in this region, It will be in the state which tends to produce peeling etc. like FIG. At that time, part of the stress concentrated in the region B is also transmitted to the region A, and the stress increases in the region A, and cracks may occur.

  However, according to the present invention, the pad structure is formed so that the contact area of the dielectric layer is larger than that of the conventional pad. Thereby, the stress concentrated on the pad is dispersed, and cracks and peeling can be effectively prevented. In FIG. 4, the conductor portion (wall surface conductor portion) PDb is formed in the region A, which is a region where cracks are likely to occur, so as to extend from the outer edge of the pad main body PDa to the inner layer direction of the wiring board. This conductor portion PDb can effectively disperse the internal stress applied to the region A where stress is concentrated, and can prevent the occurrence of cracks. In addition, the structure is easy to withstand the stress that is increased when the support is removed. The wall conductor portion PDb can obtain the above-described effect if at least a conductor portion extending in the inner layer direction of the wiring board from the end portion (outer edge portion) of the pad main body PDa is formed. However, as shown in FIG. 2, a portion extending outwardly perpendicular to the stacking direction of the substrates may be formed at the end opposite to the pad main body PDa side.

  Further, as shown in FIG. 2, the via conductor connected to the pad structure of the present invention is connected at the center portion of the pad main body PDa and has a structure not in contact with the wall surface conductor portion PDb. According to this structure, since the pad structure is formed symmetrically, it is easy to balance the dispersion of internal stress, and local stress generation based on the asymmetric structure of the pad cannot occur. Therefore, it is suitable for preventing cracks and peeling. Although a dielectric is formed between the via conductor and the wall surface conductor portion, since the conductor portion is denser than other regions in this region, cracks and the like are hardly generated. Therefore, it is not necessary to fill the region between the via conductor and the wall surface conductor portion with the conductor.

  The wiring board according to the present invention may be characterized in that the wall conductor portion has an end portion opposite to the pad main body having a bowl shape.

  As a result, the contact area between the pad and the dielectric layer can be further increased, and the internal stress can be further dispersed. The wall surface conductor portion PDb (FIG. 2) is formed extending in the inner layer direction of the wiring board to be formed, but if it is too close to the upper layer conductor, problems such as crosstalk may occur. Therefore, there is a limit to the formation of the wall surface conductor portion in the inner layer direction of the wiring board. Therefore, in order to further increase the contact area between the pad and the dielectric layer, the end of the wall surface conductor portion on the side opposite to the pad body is provided. By extending the conductor portion of the hook-shaped claw portion in the surface direction (in the direction of the side surface of the formed wiring board), the contact area can be further increased. However, if the hook-shaped claw part of the wall surface conductor part (the part extending in the surface direction of the wall surface conductor part) is too close to the exposed surface of the pad, there is a possibility that it is likely to be affected by external electromagnetic influences. Therefore, the formation position needs to be considered.

  Moreover, the wiring board of the present invention may be characterized by not having a core substrate. A wiring board that does not have a core board is characterized by being formed thin. Particularly in such a wiring board, the pad structure having an effect on cracks and peeling is effective in terms of increasing the strength of the wiring board.

In order to solve the above problems, a method for manufacturing a wiring board according to the present invention includes:
A conductor layer and a dielectric layer are laminated so that both main surfaces are composed of dielectric layers without having a core substrate, and formed at the opening of the dielectric layer forming at least one main surface A method of manufacturing a wiring board having a metal terminal pad, wherein a first dielectric layer is formed on a main surface of the support using a support for reinforcement during manufacture, and the first dielectric A metal terminal pad forming step of forming an opening through a predetermined position of the layer and forming a covered conductor portion to be the metal terminal pad so as to cover a region including a wall portion and a bottom portion of the opening; and the first dielectric A via conductor forming step of forming a via conductor connected to a portion covering the bottom of the opening in the covered conductor portion on the second dielectric layer formed on the layer; and a remaining portion to constitute the wiring board A laminating step of laminating a conductor layer and a dielectric layer; After serial laminating step, a support removal step of removing the support, but is characterized by being performed in this order.

  The method for manufacturing a wiring board according to the present invention includes a metal terminal pad forming step for forming a metal terminal pad (consisting of the pad body and the wall surface conductor) of the wiring board according to the present invention. It is. Specifically describing the contents of the metal terminal pad forming step, a first dielectric layer is formed on the main surface of a support for reinforcement during manufacturing, and an opening is provided at a predetermined position of the dielectric layer. A metal terminal pad is formed which includes a pad main body in close contact with the support and a wall surface conductor portion formed along the wall surface of the opening from the pad main body. Hereinafter, an embodiment of a method for manufacturing a wiring board according to the present invention will be briefly described with reference to FIGS.

  First, as shown in FIG. 5, a support body (in the figure, a glass epoxy substrate 2 such as FR-4 and an underlying dielectric layer 3) formed in steps 1 and 2 for reinforcement when the wiring substrates are laminated. The first dielectric sheet 31 to be the first dielectric layer B1 (FIG. 1) is formed in step 3 on the main surface of 9 (consisting of the metal foil adhesion body 5). At this time, the support 9 is intended to be removed after the wiring board is laminated, for example, a support provided with a metal foil adhesion body that can be peeled up and down as shown in the figure, or a metal plate that can be removed by etching. Etc.

  Next, in FIG. 6, an opening for forming a pad is formed in the first dielectric sheet 31 in step 4, and a conductor is formed in step 5 so as to cover the bottom and wall of the opening. By doing so, the covered conductor portion 11a to be the metal terminal pad can be formed. At this time, for example, if the coated conductor portion 11a is formed by electrolytic plating, the pad main body PDa and the wall surface conductor portion PDb (FIG. 2) can be formed at the same time, so that a wiring board can be efficiently manufactured. .

  In step 6, a second dielectric sheet 32 is formed on the coated conductor portion 11a and the first dielectric sheet 31, and an opening for via (hereinafter also referred to as a via opening) is formed in the second dielectric sheet 32. The conductive portion (pad body PDa in FIG. 2) covering the bottom of the opening is formed so as to be exposed. The via opening formed at this time is formed so as to expose the central portion of the pad main body PDa (FIG. 2), and thus from the via conductor 21 and the film conductor portion 11a to be formed in the via opening. The conductor structure can be formed symmetrically with respect to the pad center. Thereby, the internal stress can be prevented from being concentrated locally due to the asymmetry of the structure of the coated conductor portion 11a forming the pad, and the occurrence of cracks and peeling can be prevented.

  In FIG. 7, in steps 7 and 8, the build-up layer 10 is laminated based on a known build-up method, and in steps 9 and 11 of FIG. 7 and steps 10 and 11 of FIG. 8, unnecessary portions of the wiring board including the support are removed. Remove. As a result, the above-described wiring board of the present invention can be formed, and the mass production thereof is also possible. The details of the method for manufacturing the wiring board will be described later.

Moreover, the manufacturing method of the wiring board of the present invention includes:
The metal terminal pad forming step is characterized in that, on the main surface of the first dielectric layer, a region excluding the opening and the vicinity thereof is covered with a mask material, and the coated conductor portion is selectively formed by a plating process. Also good.

  According to this, in the above-described Steps 4 and 5 in FIG. 6, the process of covering the bottom and the wall of the opening for forming the pad with the conductor can be performed by the plating process. Thereby, since the said pad main body and a wall part conductor part can be formed simultaneously, the covering conductor part which should become a metal terminal pad can be formed efficiently. Further, the region not covered with the mask material at this time is the opening for pad formation and the vicinity thereof (the main surface of the first dielectric layer forming the wall of the opening), thereby plating in step 4 shown in FIG. A mask having a pattern such as the resist 6 is formed, and the wall conductor portion of the metal terminal pad of the first dielectric layer can be formed in a bowl shape along the opening surface.

BEST MODE FOR CARRYING OUT THE INVENTION

  FIG. 1 is a diagram showing an outline of a cross-sectional structure of a wiring board 1 of the present invention. The wiring substrate 1 does not have a core substrate and has a laminate in which dielectric layers (B1 to B4) made of a polymer material and conductor layers (M1 to M4) are laminated. The first main surface MP1 of the laminate is a mounting surface on which electronic components are mounted, and a fourth dielectric layer B4 made of a solder resist SR is formed on the main surface. The conductor pattern that forms the conductor layer M4 is exposed. The conductor pattern forms a second metal terminal pad PD2 connected to an electronic component or the like. On the exposed surface, a well-known solder bump FB made of solder for connecting to an electronic component is formed to form a protruding metal terminal. The second main surface MP2 is a connection surface for connecting to a mother board, an external substrate, etc., and a first dielectric layer B1 is formed, and a conductor pattern forming the first metal conductor layer M1 is formed in the opening. Is exposed and forms a first metal terminal pad PD1 that is responsible for connection to an external substrate.

  The first metal terminal pad PD1 has the same conductor structure as the metal terminal pad PD shown in FIG. The metal terminal pad PD includes a pad main body PDa and a wall surface conductor portion PDb extending from the outer edge of the pad main body PDa toward the inner layer of the wiring board and having an end opposite to the pad main body PDa having a bowl shape. It has a conductor structure. This conductor structure is connected to the via conductor VA formed in the upper dielectric layer Bb in FIG. 2 at the center upper portion of the pad body PDa. The lower part of the pad body PDa functions as a pad surface that is responsible for connection to an external substrate.

  Returning to FIG. 1, conductor patterns CL are formed in the metal conductor layers M2 and M3, and via conductors VA for connecting different metal conductor layers are embedded in the dielectric layers B1 to B3. ing. Then, an electrical conduction path (for example, from the solder bump FB to the metal terminal pad PD1) is formed by the conductor pattern CL and the via conductor VA. The dielectric layers B1 to B3 can be made of, for example, a material mainly containing an epoxy resin, and the conductor pattern CL, the via conductor VA, and the metal terminal pad PD are, for example, materials mainly made of copper. Can be configured.

  In the wiring board 1 as described above, as shown in FIG. 3, solder bumps FB are formed on the second metal terminal pads PD2 via the plating surface layer NM, and the wiring board is connected to the electronic component IC via the solder bumps FB. Connected. At this time, the gap under the electronic component IC is filled with the underfill material UF. In addition, a reinforcing frame (stiffener) ST may be provided on the first main surface MP1. Thereby, the wiring substrate 1 shown in FIG. 1 becomes the semiconductor device 100 shown in FIG.

  The first metal terminal pad PD1 (FIG. 1) in the wiring board of the present invention as described above has a side wall conductor portion PDb in addition to the normal metal terminal pad consisting only of the pad body PDa of FIG. It is characterized by comprising a pad conductor structure. According to such a pad conductor structure, the contact surface between the pad and the dielectric layer becomes wider than when a normal pad is formed, and stress concentrated on the pad is dispersed. Therefore, it is possible to effectively prevent cracks and peeling (delamination) occurring from the contact surface between the pad conductor structure and the first dielectric layer. In the case of a normal pad, as shown in FIG. 4, cracks and peeling are likely to occur starting from the interface between the pad PD and the dielectric sheet 30 forming the dielectric layer.

  The present invention is not limited to the wiring board shown in FIG. 1, and various modifications or improvements can be added without departing from the technical scope based on the description of the claims.

  Hereinafter, an example of the manufacturing method of the wiring board which is embodiment of this invention is demonstrated using FIGS. In addition, the manufacturing method of the wiring board of this invention can be applied with respect to the manufacturing method of the wiring board which removes the support substrate used at the time of lamination | stacking after lamination | stacking. The manufacturing method of the present invention described below is based on a manufacturing method of a wiring board having no supporting substrate, wherein the laminate and the supporting substrate are separated by peeling.

  First, as shown in FIG. 5, in step 1, a base dielectric sheet 3 is formed on a support substrate 2 for reinforcement during manufacturing. The support substrate 2 is not particularly limited as long as the underlying dielectric sheet 3 is in close contact with each other. For example, the support substrate 2 is composed of a glass epoxy substrate such as FR-4 (which is a material used for the core substrate as described above). be able to. Also, the underlying dielectric sheet 3 is not particularly limited, but may be made of the same material as a dielectric sheet described later, for example, a material mainly composed of epoxy.

  Next, in step 2, the metal foil adhesion body 5 is disposed on the main surface of the base dielectric sheet 3 so as to be included in the main surface, and the two metal foils 5a and 5b are in close contact with each other. Thereby, the support body 9 at the time of lamination | stacking formation which consists of the support substrate 2, the base dielectric sheet 3, and the metal foil adhesion body 5 is formed. In addition, the metal foil adhesion body 5 can be arranged on the base dielectric sheet 3 in a semi-cured state. Thereby, the adhesiveness of the grade which the lower metal foil 5a of the metal foil adhesion body 5 does not peel from the base dielectric sheet 3 at a subsequent process can be obtained. In addition, as the metal foil adhesion body 5, for example, two copper foils adhered through metal plating (for example, Cr) can be used. Such a metal foil adhesion body 5 can be peeled off.

  In step 3, the first dielectric sheet 31 to be the lower region B1a of the first dielectric layer B1 is formed so as to wrap the metal foil adhesion body 5. The first dielectric sheet 31 is in close contact with the base dielectric sheet 3 in the peripheral region of the metal foil adhesion body 5 together with the metal foil adhesion body 5 (upper metal foil 5b). Seal. The dielectric sheet can be formed using, for example, a well-known vacuum lamination method.

  Next, as shown in FIG. 6, in step 4, a pad opening in which the metal terminal pad PD1 of FIG. 1 is to be formed is formed through the first dielectric sheet 31 by, for example, a known photovia process. In this case, the first dielectric sheet 31 must have at least photosensitivity, and for example, a provi coat film (manufactured by Nippon Paint Co., Ltd.) that is a photosensitive resin film can be used. Further, after the electroless plating layer 11b is formed on the entire exposed surface on the main surface side of the first dielectric sheet 31 by an electroless plating process, a region excluding the pad opening and its peripheral portion as shown in FIG. 6 is formed. Mask with plating resist 6.

  In step 5, the plating resist 6 is used as a mask to perform an electrolytic plating process, and then the plating resist 6 is removed. Then, the electrolytic plating layer is masked with a plating resist (not shown) to remove the unmasked region. The electrolytic plating layer 11b is removed, and the plating resist layer (not shown) is removed. As a result, the conductor pattern 11a having a conductor structure as shown is exposed and formed. The conductor pattern 11a thus formed is formed so as to cover the side surface side and the upper surface side of the wall portion of the pad opening of the first dielectric sheet 31, and the wall surface conductor portion covering this wall portion is It has a mold shape. The conductor structure of the conductor pattern 11a forms the first metal terminal pad PD1 belonging to the first conductor layer M1 in FIG. 1, and the contact surface between the conductor pattern 11a and the upper metal foil 5b shown in step 5 of FIG. However, this is a connection surface for connecting to a mother board or another wiring board.

  In step 6, the second dielectric sheet 32 is laminated (bonded) so as to wrap the conductor pattern 11a. Thereby, a dielectric region to be the first dielectric layer B1 of FIG. 1 formed by the second dielectric sheet 32 and the first dielectric sheet 31 is formed. Further, the second dielectric sheet 32 is formed with a via opening in which the central portion of the conductor structure of the conductor pattern 11a is exposed. The via opening can be formed by, for example, known laser processing. In this case, it is preferable that the dielectric sheet in which the opening for via is formed has at least thermosetting and is subjected to a curing process. Further, as described above, it can be formed by a well-known photo via process.

  Next, as shown in FIG. 7, in step 7, the first via conductor 21 is formed in the via opening and the conductor pattern forming the second conductor layer M <b> 2 (FIG. 1) connected to the first via conductor 21. 12 is formed on the second dielectric sheet. The via conductor can be obtained by filling the formed via opening by, for example, electroless plating in a known semi-additive method. The conductor layer can also be formed by the semi-additive method described above.

  In step 8, the third dielectric sheet 33 to be the second dielectric layer B <b> 2 is formed on the conductor pattern 12, and the via conductor 22 is formed in the third dielectric sheet 33. Next, the third conductor pattern 13, the fourth dielectric sheet 34, the fourth conductor pattern 14, and the fifth dielectric sheet 35 are sequentially stacked on the exposed surface including the third dielectric sheet 33 and the via conductor 22. At this time, the fourth conductor pattern 14 forms the second metal terminal pad PD <b> 2 on the electronic component mounting side shown in FIG. 1, and the via conductor 23 is formed in the fourth dielectric sheet 14. Further, a pad connection opening is formed in the fifth dielectric sheet 35 to expose the fourth conductor pattern 14. These can be performed by a known build-up method or the like, and the laminated sheet body 10 is formed by this step 8. In addition, in this embodiment, although the lamination sheet body 10 is comprised by the metal foil contact body 5 and the dielectric sheets 31-35, the number of dielectric sheets is not restricted to this. As described above, the metal foil adhesion body 5 disposed on the main surface of the base dielectric sheet 3 so as to be included in the main surface, and the metal foil adhesion body 5 formed so as to wrap around the metal foil adhesion body 5 5, a laminated sheet body 10 having a first dielectric sheet 31 that is in close contact with the base dielectric sheet 3 and seals the metal foil adhesive body 5 is formed.

  The dielectric sheets 31 to 35 laminated in the laminating step can be made of, for example, a material mainly composed of epoxy, and the conductor patterns 11a and 12 to 14 and the via conductors 21 to 23 are made of, for example, Copper can be the main component.

  Moreover, in this embodiment, it forms so that the exposed main surface of the upper side of the lamination sheet body 10 may become an electronic component mounting side. Therefore, the dielectric sheet 35 forming the upper main surface of the laminated sheet body 10 is formed of the solder resist SR as shown in FIG.

  After the step 8, before proceeding to the next step 9, the plated surface layer 7 is formed on each exposed surface of the conductor pattern 14 forming the second metal terminal pad, for example, by electrolytic plating. For example, electrolytic Ni—Au plating or electrolytic Sn (solder) plating can be used for the electrolytic plating treatment. Further, since the plating surface layer 7 has resistance to an alkaline etching solution, it is not necessary to form a protective layer or the like for protecting the conductor pattern 14 in the subsequent steps.

  In step 9, the laminated sheet body 10 removes the region other than the corresponding region so that only the region on the metal foil adhesion body 5 becomes the wiring board 1 (see FIG. 1). This removal process is performed, for example, by cutting the base dielectric sheet 3 and the support substrate 2 with, for example, a blade blade in the A1-A1 ′ cross section and the A2-A2 ′ cross section including both ends of the thin metal adhesion body. . Providing such a cut surface and performing the cutting process is effective because the metal thin 5a and the metal thin 5b described later can be easily peeled off. In this way, only the laminated portions (hereinafter also referred to as wiring laminated portions) formed in the upper and lower regions of the metal foil adhesion body 5 remain. As a result, the remaining portions of the dielectric sheets 31 to 35 become the dielectric layers 31 ′ to 35 ′ constituting the wiring laminated portion 10 ′ to be the wiring substrate 1.

  Next, as shown in FIG. 8, in step 10, the two metal foils in the metal foil adhesion body 5 with the wiring laminated portion 10 ′ attached from the support substrate 2 to one metal foil (upper metal foil 5 b). Peel at the interface between 5a and 5b.

  Then, as shown in Step 11, after peeling the wiring laminated portion 10 ′ from the support substrate 2 in Step 10, the metal foil adhered to the main surface formed by the first dielectric sheet 31 of the wiring laminated portion 10 ′. 5b is removed. The exposed conductor pattern 11a (first metal terminal pad PD1 in FIG. 1) becomes a connection terminal as it is. Further, solder bumps FB are formed on the exposed surface of the conductor pattern 14 (second metal terminal pad PD2 in FIG. 1) via the plating surface layer 7. Thereby, the wiring board 1 shown in FIG. 1 is obtained. In the manufacturing method described above, the metal terminal pad side for connection with the mother board or other wiring board is laminated. However, the electronic component IC side may be laminated. In this case, the electronic component mounting surface side In addition, a pad conductor structure like the conductor pattern 11a is formed.

  In step 11, the metal foil 5b can be removed by etching, for example. On the main surface of the first dielectric sheet 31 from which the metal foil 5b has been removed, the first metal terminal pad PD1 appears exposed inside. When the first conductor pattern 11a (first metal terminal pad PD1 in FIG. 1) is formed with Cu as a main component, the surface of the metal foil 5b is slightly etched by etching. That is, the completed wiring board does not have a core substrate, and the dielectric layers 31 ′ to 35 ′ (the dielectric layer shown in FIG. 1) made of a polymer material so that both main surfaces are constituted by dielectric layers. B1a, B1b, B2, B3, B4) and conductor patterns 11a, 12, 13, 14 (conductor layers M1 to M4 in FIG. 1) are stacked, and the first conductor pattern 11a having the above-described pad conductor structure ( In the first metal terminal pad PD1 in FIG. 1, the exposed surface of the conductor pattern 11a is etched on the second main surface side of the first dielectric layer 31 ′ (dielectric layer B1a in FIG. 1) forming the first main surface MP1. A recess (pad opening) is formed on the second main surface of the first dielectric layer 31, and a new exposed surface appearing in the recess is used as a connection terminal pad, and a via is formed on the back surface side of the exposed surface. Conductor 21 (via conductor VA in FIG. 1) and A configuration in which to continue.

  Further, when it is desired to form the main surface of the wiring laminated portion 10 'on the metal thin 5b side as a flat surface without unevenness, for example, the upper metal foil 5b is made of at least one of Ti, Cr, Al, Ag, Sn and the like. You may form as a metal thin film layer which consists of the above metal material. That is, of the two metal foils 5a and 5b forming the metal foil adhesion body 5, when the support substrate 2 is removed (in this case, it is removed by peeling off the two metal foils), it remains attached to the wiring laminated portion. The metal foil 5b may be formed of a metal material different from the first via conductor or the first conductor layer (metal terminal pad). By using a metal thin film layer having an etching selectivity different from that of the first metal terminal pad PD1, in particular, a large one, the surface of the metal terminal pad is not etched when the metal thin film layer is etched. Therefore, the removal surface of the metal thin film layer can be obtained as a complete flat surface. In the case of the said embodiment, the main surface by the side of the metal thin 5b of wiring laminated part 10 'can be formed as a flat surface without an unevenness | corrugation.

  In addition, wiring laminated part 10 'contained in the lamination sheet body 10 shall be a thing with which said wiring laminated part 10' was continuously connected in multiple numbers. Thereby, a some wiring board can be formed simultaneously.

  The present invention is not limited to the wiring board shown in FIG. 1, and various modifications or improvements can be added without departing from the technical scope based on the description of the claims. For example, the present invention can also be applied to a wiring board manufacturing method (for example, Patent Document 1) in which a metal plate is used as a support substrate at the time of lamination and the metal plate is removed after lamination. is there. With the above embodiment as the first embodiment, a method for manufacturing a wiring board according to the present invention when a metal plate is used as a support substrate will be described below as a second embodiment with reference to FIGS. .

  As shown in FIG. 9, a metal plate (for example, a copper plate) as the support substrate 2 is prepared (step 1), a first dielectric layer 31 'is formed immediately above, and a conductor pattern 11a forming a metal terminal pad is formed. (Step 3). At this time, the conductor pattern 11a can be formed by a process similar to the process shown in steps 4 and 5 (FIG. 6) of the first embodiment. Next, in FIG. 10, a via opening for forming the conductor pattern 11a is formed (step 4), the opening is filled with a conductor, a second conductor layer is formed (step 5), and a known build-up method is used. The wiring laminated portion 10 is formed (Step 6). In FIG. 11, first, the support substrate 2 is removed by, for example, wet etching to expose the conductor pattern 11a forming the metal terminal pad (Step 7), and the electronic component formed on the side opposite to the conductor pattern 11a is exposed. Solder bumps FB are formed on the metal terminal pads that serve as connection terminals (step 8). Steps 3 to 6 can be performed in the same process as Steps 5 to 8 in the first embodiment, and a metal terminal pad having the conductor structure shown in FIG. (Support). Therefore, the effect of the present invention can be obtained in the second embodiment as well as the first embodiment.

Schematic which shows position embodiment of the wiring board of this invention. Sectional drawing which shows the conductor structure of the metal terminal pad of this invention. Semiconductor device using wiring board 1 of FIG. Sectional drawing which shows the conductor structure of the conventional metal terminal pad. The figure showing the process of the manufacturing method of the wiring board which is 1st embodiment of this invention. Figure following Figure 5 Figure following Figure 6 Figure following Figure 7 The figure showing the process of the manufacturing method of the wiring board which is 2nd embodiment of this invention. Figure following Figure 9 Figure following Figure 10

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Wiring board 2 Support substrate 3 Base dielectric sheet 5 Metal foil adhesion body 10 Laminated sheet body 11a First conductor pattern 21 First via conductor 31 First dielectric sheet 32 Second dielectric sheet

Claims (2)

A conductor layer and a dielectric layer are laminated so that both main surfaces are composed of dielectric layers, and a wiring having a metal terminal pad formed in an opening of the dielectric layer forming at least one main surface A substrate,
The metal terminal pad has an exposed surface in the opening, and a pad body that is via-connected to the conductor layer inside the wiring board on the back surface of the exposed surface, and an inner layer of the wiring board from an outer edge of the pad body And a wall surface conductor portion formed along the wall portion of the opening in the direction. A conductor layer and a dielectric layer are laminated so that both main surfaces are composed of dielectric layers without having a core substrate, and formed at the opening of the dielectric layer forming at least one main surface A method of manufacturing a wiring board having a metal terminal pad,
Using a support for reinforcement at the time of manufacture, forming a first dielectric layer on the main surface of the support, forming an opening through a predetermined position of the first dielectric layer, and forming a wall portion of the opening And a metal terminal pad forming step for forming a covered conductor portion to be the metal terminal pad so as to cover a region including the bottom portion,
A via conductor forming step for forming a via conductor connected to a portion covering the bottom of the opening in the covered conductor portion on the second dielectric layer formed on the first dielectric layer;
A laminating step of laminating the remaining conductor layer and dielectric layer to constitute the wiring board;
A support removing step for removing the support after the lamination step;
Are performed in this order.

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