1301662 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種封裝基板以及其製作方法，尤指一 種適用於無電鍍導線之封裝基板以及其製作方法。 5 【先前技術】 由於電子產品日趨輕量化、薄型化、小型化、多功能 化#需求’同時帶動積體電路晶片封裝技術的發展，進而 促使晶片封裝朝向多腳化、薄型化、及引腳微細化，甚至 10 無引腳構裝等技術。 為因應輕薄短小的趨勢以及追求封裝的高密度化，目 前球狀陣列封裝（Ball Grid Array)、晶片尺寸型封裝（chip Scale Package)、及覆晶（Flip Chip)技術已成為封裝主流技 術。因此，對於小面積、1/()接腳提高、佈線緻密化、低雜 15訊、產品可靠性、甚至製作成本等需求，已成為封裝基板 製作之重要課題。 封裝基板之製作過程一般需於基板表面形成緻密的電 路圖案，以作為傳輸電子訊號或電源之用。目前業界普遍 使用銅質導線作為電路佈線，故電路佈線的1/〇接點處需鑛 20有鎳金層，其除了可防止銅導線氧化之外，以維持I/O接點 處之電性品質，亦可提升封裝基板與晶片之間進行打金線 時之穩E1性。此外，基板表面尚有—防焊層（s。此麵， 以保護基板表面所形成之電路圖案。 傳統封裝基板製程是先於已形成電路圖案之基板上覆 5 1301662 蓋有一防焊材料後再電鍍形成金屬保護層，其中該金屬保 護層一般係為鎳/金層。因此，未被防焊材料覆蓋之區域（通 奉為I/O接點處）需藉由表面導線電路延伸至基板周圍以形 成一電流傳導路徑，方可進行I/O接點處電鍍鎳金之製程。 5 圖1係為習知具有電鍍導線之封裝基板之剖面示意 圖。為了於基板1表面之I/O接點12處形成金屬保護層13， 則上表面之線路層1〇需另佈設眾多之電鍍導線丨丨，才可傳 導電流至I/O接點12，以進行金屬保護層13之電鍍製程，其 中该金屬保遵層一般係為錄/金層。然而，電鑛金屬保護層 10 13所延伸出的電鍍導線11佔據了基板1表面的佈線空間，因 而無法提升基板電路的佈線密度。此外，相鄰的電鑛導線 彼此間的訊號干擾會造成雜訊產生的問題。儘管，一般已 使用成型機（router)或切割製程（cutting pr〇cess)去除基板表 面之電鍍導線，其電鍍導線所殘留的末端線路仍會在高頻 I5 下產生電性訊號傳輸的干擾’以致電性品質下降的問題。 為解決上述電錢導線所產生的缺點，已有許多研究團 隊發展出無電鑛V線之電鑛金屬保護製程。請參閱圖2&至 圖2d所示’圖2係為習知無電鍍導線封裝基板之製程示音 圖，一般稱為 GPP(g〇ld pattern plating)電鍍製程。 20 如圖2a所示，基板2之上下表面皆形成一完整之導電層 21，隨後於導電層21之表面覆蓋有一圖案化光阻層以，二 顯露出基板2表面欲形成之電路佈線。接著，如圖孔所示， 於顯露之導電層21表面電鍵一金屬保護層23，其中該金屬 保護層一般係為鎳/金層。最後，參閱圖及與圖2d步驟，移 1301662 除圖案化光阻層22後並進行餘刻製程，藉由金屬保護層23 #護其下之導電層21即可完成基板2上下表面之圖案化線 路，以形成一線路層24。 雖然此種GPP電鍍製程無需另設有電鍍導線，但是基 5板2表面的線路層24乃全面性覆有一金屬保護層23〇此種& 程不僅耗費過多鎳/金材料，且僅有表面的線路層以覆有鎳 /金層，該線路層24兩側仍顯露在外並未受保護，因此易發 φ 生線路氧化或打線時晶片與基板間電性耦合不佳的情形: 再者，因材料特性相異而易於導致基板表面覆蓋之防焊層 10不易與線路表面之鎳金材料緊密貼合等問題，將影響產品 的可靠性與其使用壽命。 因此，目前亟需一種無電鍍導線之封裝基板之製作方 法，其可提升電路導線之佈線面積，且能提供晶片與封裝 基板、或封裝基板與電路板間良好的電性連接品質，並降 15 低製作成本。 • 【發明内容】 本發明是提供一種封裝基板，且基板表面無需另外佈 • 設電鍍形成電性連接墊用之電鍍導線，其中封裝基板包 • 20括：一具有一上表面、一下表面、與複數個電鍍導通孔之 基板，且電鍍導通孔貫通於基板上表面與下表面；一金屬 層，其位於電鍍導通孔之一内表面、以及基板之上表面與 下表面；複數個電性連接墊，其位於基板上表面之部分金 屬層表面、以及基板下表面之部分金屬層表面；以及一圖 25案化之防焊層，其覆蓋於基板之最外上下表面，並顯露出 7 1301662 之該些電性連接墊。其中，本發明位於基板上表面 訂表面之金屬層分別形成有—圖案化線路。 10 15 ^本發明封裝基板巾，部分電性連接墊與電鍍導通孔 拉、接且另-部分電性連接墊未與電鑛導通孔電性連 接。一具體實施例中’本發明上表面之電性連接塾為第一 電性連接墊與第二電性連接墊，而第_電性連接塾可舆電 鍍ν通孔電性導通’且第二電性連接塾未與電料通孔電 性導通。另—具體實施例中，本發明下表面之電性連接塾 為第三電性連接塾與第四電㈣純，μ三電性連接塾 可與電料通孔電性導通’且第四電性連接塾未與電鑛導 通孔電性導通。 藉此，本發明封裝基板之線路可不受外界空氣氧化及 外界污染物所污染，且本發明之電性連㈣可提供晶片與 封裝基板、或封裝基板與電路板μ好的電性連接品質， 並且增加基板使用壽命。再者，本發明封裝基板表面無需 另外佈設有電鍍導線’不僅可大幅提升基板電路之佈線面 積’並且可有效地避免傳統基板佈設電料線所造成之雜 訊干擾。 本發明亦關於一種封裝基板之製作方法，其主要可利 2〇用一個別形成於基板上表面與下表面之導電層而傳導電 流，以分別進行基板上下表面之電鍍並且形成電性連接 塾’因此本發明方法所製作之基板為一種無電錄導線之封 裝基板，故其製作時無需另佈設電鍍導線。 本發明更提供一種封裝基板之製作方法，其包含的步 1301662 驟有.（a)提供一具有一上表面、一下表面、複數個貫通該 基板上表面與下表面之電鍍導通孔、與一金屬層之基板， 且金屬層是形成於電鍍導通孔之一内表面以及基板之上表 面與下表面，且位於基板之上表面與下表面之金屬層是分 5別形成一圖案化線路；其中，電鍍導通孔貫通於基板上表 面與下表面，部分上表面之金屬層未與電鍍導通孔電性連 接，且部分下表面之金屬層未與電鍍導通孔電性連接；（七) 形成一第一導電層於基板之上表面，以完全覆蓋上表面與 金屬層；（c)形成一具有圖案化之第一阻層於基板之上表面 10與下表面，其中第一阻層係完全覆蓋下表面之金屬層，並 2露出部分上表面之第一導電層；（d)移除顯露於上表面之 苐‘電層，以顯露出部分上表面之金屬層；（e)形成一具 有圖案化之第二阻層，以覆蓋殘露於第一阻層外之第一導 電層’（f)廷鑛形成一金屬保護層於上表面顯露之金屬層表 15面，（g)移除第一阻層、第二阻層、及第一導電層；（h)形 成具有圖案化之防焊層於基板上下表面，並顯露出上表 面之金屬保護層與部分下表面之金屬層；（丨）形成一第二導 電層於基板之下表面與防焊層表面，以完全覆蓋下表I之 線路層與下表面之防焊層；⑴形成一第三阻層於基板之上 20表面與下表面，並圖案化下表面之第三阻層以顯露出部分 下表面之第二導電層；（k)移除顯露於下表面之第二導電 層’以顯露出部分下表面之金屬層；以及（1)冑鍍形成一金 屬保護層於下表面顯露之金屬層表面。 藉此，本發明封裝基板之製作方法俾能增加基板表面 9 1301662 之電路佈線面積，且能提供晶片與封裝基板、或封裳基板 與電路板間良好的電性連接品質。故，本發明製作之無電 鑛導線封裝基板可具有良好的產品可靠性以及長時間的使 用哥命。 5 本發明封裝基板之製作方法，可更包括一步驟（m)，移 除第三阻層與被第三阻層所覆蓋之第二導電層，即獲得一 完整結構之封裝基板。 於本發明封裝基板之製作方法中，基板上下表面形成的 圖案化線路可與電鍍導通孔内表面之金屬層部分導通。 1〇 一較佳具體實施例中，本發明基板上表面之線路，即 為本毛明所述之金屬層，部分上表面線路（金屬層）未與電鍍 導通孔電性連接，而另一部分上表面之線路（金屬層）是與電 錢導通孔内表面之金屬層電性連接。且，基板下表面線路 之電性連接方式可同理推知而相同於上表面線路之設計。 15 -於本發明封裝基板之製作方法中，㈣⑴所形成之第 三阻層可完全覆蓋基板之上表面防焊層及上表面之金屬保 護層，以保護上表面已完成之線路。 此外，本發明金屬保護層主要用以保護被其所覆蓋之 金屬層不受外界空氣氧化及外界污染物所污染。另該金屬 2〇層可為電性連接墊，以作為晶片與封裝基板之電性耦合 用、或封裝基板與電路板之電性耦合用。且在此所述之& 性連接墊之種類無限制，較佳可為打線式半導體封 與晶片電性耦合用之打線焊墊（wire bonding pad，又為 Fmger)、封裝基板與電路板電性耦合用之接觸墊（〇⑽忪以 1301662 -: Pad或Land)、或其組合。 再者’本發明金屬保護層可為不易氧化之金屬材，較 佳可為金、鎳、鈀、銀、錫、鎳/鈀、鉻/鈦、鎳/金、鈀/金、 鎳/把/金或其組合，最佳可為鎳/金（先上錄後上金）。故此， 5本發明電性連接塾除了有助於打線式封裝基板之電性連接 塾與金線的電性連接，亦可降低外界環境造成電性連接塾 氧化之問題’以提商焊球、或金線等植設於電性連接塾的 _ 導電元件之電性品質。 本發明封裝基板之製作方法可為一種無電鑛導線封裝 10基板之製作方法，主要先藉由第一導電層作為電流傳導路 瓜，以提供一電鍍形成於上表面金屬層表面之金屬保護層 所需之電流，而先形成上表面金屬層之金屬保護層；接著， 再藉由第二導電層作為電流傳導路徑，以提供一電鍍形成 於下表面金屬層表面之金屬保護層所需之電流，最後形成 15下表面金屬層之金屬保護層。因此，本發明封裝基板之製 作方法無需於基板表面另外佈設有電鍍導線，不僅可大幅 I #升基板電路之佈線面積，並且可有效地避免傳統基板佈 設電鐘導線所造成之雜訊干擾。 另外，本發明導電層所使用之材料可為習知任一種可 -20導電之金屬材或導電高分子，較佳可為至少一選自由銅、 錫、鎳、鉻、鈀、鎢、及鈦所組成群組之材料。 本赉明無電鍍導線封裝基板之製作方法中，形成導電 層之製程無限制，較佳可採用有電電鍍、無電解電鍍、化 學氣相沈積、物理氣相沈積、濺鍍、蒸鍍或其述方法組合， 11 1301662 更佳可採用濺鍍、無電解電鍍。 再者，本發明金屬層所使用之材料可為習知任一種可 導電之金屬材，較佳可為一銅金屬材，以作為基板表面之 線路層。 5 本發明適用之基板結構可為單層電路板，還可為已完 成前段線路製程之兩層板或多層電路板，且本發明無電鍍 導線封裝基板之製作方法較佳可運用於打線式（wire bonding)封裝基板。 本發明基板所適用之絕緣材料較佳可為有機薄膜介電 10 材或液態有機樹脂材料所組群組之其中一者；上述材質係 可選自 ABF(Ajinomoto Build-up Film )、 BCB(Benzocyclo-buthene)、LCP(Liquid Crystal Polymer)、 Pl(Poly-imide) 、 PPE(Poly(phenylene ether)) 、 PTFE(Poly(tetra-fluoroethylene)) 、 FR4 、 FR5 、 15 BT(Bismaleimide Triazine)、芳香尼龍（Aramide)等感光或非 感光有機樹脂，或亦可混合環氧樹脂與玻璃纖維等材質所 構成。 再者，本發明中所使用之阻層可為習用微影製程所適 用之阻層材料較佳可為一光感材料，且該光感材料可為乾 20 膜（dry film)、液態光阻或其組合。且，本發明中阻層之形 成無限制，較佳可利用印刷、旋轉塗佈、貼合、化學沈積、 物理沈積、或前述方式之組合。 本發明封裝基板之製作方法是形成上下表面之線路層 後，再藉由基板上下表面分別形成的導電層作為電流傳導 12 1301662 之用，以分別於上表面與下表面形成一金屬保護層，而排 除傳統另設有電鑛導線之線路佈設。故此’本發明導線封 裝基板之製作方法可為一無電鍍導線封裝基板之製程，並 且可滿足「細間距封裝」（fine pitch package)之需求，以製 5 作一高緻密化電路佈線之封裝基板。再者，本發明封裝基 板之製作方法不僅有效地利用錄/金材料並降低製作成 本，並且可提升產品之電性品質，以增加產品之市場競爭 【實施方式】 ~ 請參閱圖4所示，係為本發明一較佳具體實施例之無電 鍵導線之封裝基板示意圖。 本實施例封裝基板3之上表面包含有可與電鍍導通孔 4〇電性連接之第一電性連接墊36卜以及未與電鍍導通孔4〇 15 20 電性連接之第二電性連接墊362。其中，第一電性連接墊36ι 與第二電性連接墊362是位於圖案化之金屬層32表面。第一 電I4生連接墊361的邊緣四周未全部被防焊層37所覆蓋，並且 顯露出大面積的電性連接區，以利於晶片封裝打線之作業。 本實轭例封裝基板3之下表面包含有可與電鍍導通孔 40電f生連接之第三電性連接塾⑹、以及未與電鍍導通孔仙 電性連接之第四電性連接墊364。其中，第三電性連接墊363 與第四電性連接墊364是位於圖案化之金屬層32表面，且第 =電性連接墊363與第四電性連接墊364皆未被防焊層37 ^是盖。料，本例上表面之第二電性連接塾如的周圍係 白被防焊層37所覆蓋。 13 25 1301662 本例中所有電性連接墊361、362、363、364皆為鎳/金 之夕層金屬結構，除了 :有助於打線式封裝基板之電性連接 墊與金線的電性連接，還可增加基板之抗環境影響性。 然而’本發明封裝基板之製作方法可無限制，以下所 5 敘述之方法僅為本發明一較佳具體實施例，並非用以限定 本發明封裝基板之製作方法。 請參閱圖3所示，圖3(a)至圖3(j)為本發明一較佳實施例 無電鍍導線之封裝基板之製程示意圖。 首先，如圖3(a)所示，提供一基板3，且基板3之上表面 1〇 3〇1與下表面302皆形成有一銅箔31，以構成核心基板結 構。本實施例基板3包含有一上表面301、一下表面3〇2、複 數個貫通於基板上下表面之電鍍導通孔4〇及一金屬層32。 其中金屬層32是形成於電鍍導通孔4〇之内表面、以及基板3 之上表面301與下表面302,且位於基板3上表面3〇1與下表 15面302之金屬層32是個別形成一具有圖案化之線路。其中， 該基板3可為單層電路板，還可為已完成前段線路製程之兩 層板或多層電路板。 本實施例基板3表面形成一具有圖案化線路之方法，是 採用圖案化蝕刻製程而得，且本例基板3表面所形成之金屬 20層32即為基板表面的線路。當然，本發明基板表面形成圖 案化線路之方法不限於本例所述方式。在此是採用一銅金 屬作為線路導線。 此外，於本例基板3上表面之線路，即為上表面所形成 之金屬層32所形成，且部分上表面金屬層32(線路）是未與電 1301662 锻導通孔4032電性連接，且另一部分上表面之金屬層32(線 路）是與電鍍導通孔40電性連接。相同地，部分下表面金屬 層32未與電鍍導通孔4〇電性連接，且另一部分下表面金屬 層32是與電鍍導通孔40電性連接。 接著’如圖3(b)所示，形成一第一導電層33於基板3之 上表面’且完全覆蓋基板3上表面3〇1與上表面金屬層32， 以作為後續上表面電鍍製程之電流傳導路徑。其中，該第 導電層33較佳係可採用有電電鍍、無電解電鍍、化學氣 相沈積、物理氣相沈積、濺鍍、蒸鍍或其述方法組合；更 佳可採用濺鍍 '無電解電鍍。 後於基板3之上表面與下表面形成一第一阻層，並 2再藉由圖案化製程以形成一具有圖案化之第一阻層34。 $中’第-阻層34是完全覆蓋下表面之金屬層32，並顯露 出部分上表面之第一導電層33。 15 20 “閱圖3(e)所示，移除上表面所顯露 — 須再要之金屬，故本實施❹ 阻層外的第一導電層33。其『殘露於第- 同第-阻層34之开m 第一阻層35之形成係如 構。 之开/成方法’以提供-如圖柳所示之基板結 然後，如圖3(e)所示 '進行 保護層-上表_露，二-移=表金: 15 13 ο 1662 1 ^ 之第一阻層34、第二阻層35、及第一導電層33，即獲得一 如圖3(f)之基板結構。其中，上表面之金屬保護層％已形 成+，而該金屬保護層36包含有可與電鍍導通孔4〇電性導通 之第一電性連接墊36卜以及電性未導通之第二電性連接墊 5 362(即為本例打線式封裝基板上表面之獨立打線焊墊）。 待基板3上表面完成上述製程後，為了保護基板3上下 表面之銅金屬線路，即形成一防焊層37如綠漆或黑漆材料 • 於基板3之表面，再經圖案化製程以顯露出上表面之金屬保 護層36以及下表面之部分金屬層32，且該基板結構請參閱 1〇圖3(g)所示，而該防焊層Ρ係可以塗佈、印刷或貼覆等方 式，覆蓋於基板上下表面。丨中，了表面所顯露之金屬層 32將作為後續形成下表面之金屬保護層％之區域。 卜接著，進行基板下表面之製程，如圖3(h)所示，形成一 f二導電層38於基板3之下表面與防焊層37表面，且完全覆 15盍住基板下表面與下表面防焊層37，以作為後續下表面電 • 鍍製程之電流傳導路徑。唭中，該第二導電層％較佳係可 採用有電電鍍、無電解電鍍、化學氣相沈積、物理氣相沈 積、濺錄、蒸鍍或其述方法組合；更佳可採用錢鍵、 解電鍍。 “、、电 • 20 之後，形成第三阻層39以覆蓋於基板3之上表面與下表 下表面之第二阻層29並且經過一圖案化製程以顯露出 I表面之部分第二導電層38 ;隨即移除下表面顯露之第二 導電層38 ’即獲得一如圖3⑴所示之基板結構。 進行下表面電鍍製程，係如圖3⑴所示，於下表面顯露 16 1301662 之導電層32區域電鍍形成一鎳/金材之金屬保護層％。 接著，經由前述製程，該形成之金屬保護層36包含有 可與電鑛導通孔40電性導通之第三電性連接墊363、以及電 性未導通之第四電性連接墊364。最後，移除基板上下表面 5之第二阻層39與第三阻層39所覆蓋之第二導電層38，即完 成了本貝施例無電鍍導線封裝基板3之製程，且經由本例製 程所形成之基板結構係如圖4所示。 故此，於本實施例基板3上表面之電路佈線中，金屬保 護層36包含了複數個電性連接墊361、362，且該等電性連 10接墊均用以作為晶片（圖未示）與打線式封裝基板3電性耦合 用之打線焊墊。於本實施例基板3下表面之電路佈線中，金 屬保護層36包含有複數個電性連接墊363、364，且該等電 性連接墊均用以作為封裝基板3與電路板（圖未示）電性耦合 用之接觸墊（contact pad或Land)。 15 除了本實施例所述之電性接觸墊之外，凡基板需進行 電鍍鎳/金製程部分，皆可藉由本發明揭示之方法而形成其 電鍍鎳/金之結構。 八 綜上所述，本發明無電鍍導線封裝基板之製作方法不 僅可降低製作成本且提升產品良率，以增加產品之市場競 2〇肀力。再者，本發明製作方法除了可增加基板電路導線之 佈線面積，無需於整層的線路層表面均鑛有錄金層，如此 可大幅降低電鍍鎳/金之成本，且還可提供晶片與封裝基 板、或封裝基板與電路板間良好的電性連接品質，而免除 導線氧化的問題。 17 1301662 上述實施例僅係為了方便說明而舉例而已，本發明所 主張之權利範圍自應以申請專利範圍所述為準，而非僅限 於上述實施例。 - 5 【圖式簡單說明】 圖1係習知具有電鍍導線之封裝基板之剖面示意圖。 圖2⑷至圖2⑷係習知無電鍍導線之封裝基板之製程示意 圖。 圖3⑷至圖3⑴係本發明-較佳實施例無電鑛導線之封裝基 10 板之製程示意圖。 圖4係本發明一較佳實施例無電錢導線之封裝基板之示音、 圖。 〜 【主要元件符號說明】 1基板 12 I/O接點 21導電層 24線路層 32金屬層 35 第二阻層 38第二導電層 301上表面 10線路層 13金屬保護層 2 2光阻層 3基板 33第一導電層 36金屬保護層 39第三阻層 302下表面 11電鍍導線 2基板 23金屬保護層 31銅箔 34第一阻層 37防焊層 40電鍍導通孔 361第一電性連接墊 363第三電性連接墊 362第二電性連接墊 364第四電性連接墊 18 15[Technical Field] The present invention relates to a package substrate and a method of fabricating the same, and more particularly to a package substrate suitable for an electroless plating wire and a method of fabricating the same. 5 [Prior Art] As electronic products become lighter, thinner, smaller, and more versatile, 'demand' drives the development of integrated circuit chip packaging technology, which in turn drives the chip package toward multi-pin, thin, and pin-out. Micro-fine, even 10 leadless components and other technologies. In order to respond to the trend of thinness and shortness and to pursue high density of packages, current Ball Array Array, Chip Scale Package, and Flip Chip technology have become mainstream technologies for packaging. Therefore, the demand for small area, 1/() pin improvement, wiring densification, low noise, product reliability, and even manufacturing cost has become an important issue in the manufacture of package substrates. The manufacturing process of the package substrate generally requires forming a dense circuit pattern on the surface of the substrate for transmitting electronic signals or power. At present, copper conductors are commonly used in the industry as circuit wiring. Therefore, there is a nickel-gold layer in the 1/〇 junction of the circuit wiring, which not only prevents oxidation of the copper wires, but also maintains the electrical properties at the I/O contacts. The quality can also improve the stability E1 of the gold wire between the package substrate and the wafer. In addition, there is a solder mask layer on the surface of the substrate (s. This surface is used to protect the circuit pattern formed on the surface of the substrate. The conventional package substrate process is performed on the substrate on which the circuit pattern has been formed, and 5 1301662 is covered with a solder resist material. Electroplating forms a metal protective layer, wherein the metal protective layer is generally a nickel/gold layer. Therefore, the area not covered by the solder resist material (which is at the I/O contact) needs to be extended to the periphery of the substrate by the surface lead circuit. In order to form a current conduction path, the process of electroplating nickel gold at the I/O contact can be performed. 5 Fig. 1 is a schematic cross-sectional view of a package substrate having a plated wire. For the I/O contact on the surface of the substrate 1. The metal protective layer 13 is formed at 12 places, and the circuit layer 1 on the upper surface needs to be provided with a plurality of electroplated wires 丨丨 to conduct current to the I/O contact 12 for performing the plating process of the metal protective layer 13, wherein The metal-preserving layer is generally a recording/gold layer. However, the electroplated wire 11 extended by the electrodeposited metal protective layer 10 13 occupies the wiring space on the surface of the substrate 1, and thus the wiring density of the substrate circuit cannot be improved. The signal interference between the electric ore conductors causes problems in the noise. Although it is generally used to remove the plated wire on the surface of the substrate using a router or cutting process, the end of the plated wire remains. The line still generates the interference of the electrical signal transmission under the high frequency I5'. The problem of the deterioration of the call quality. In order to solve the shortcomings caused by the above-mentioned electric money wire, many research teams have developed the electric ore metal of the non-electrical V line. The process is protected. Please refer to FIG. 2 & to FIG. 2d. FIG. 2 is a process diagram of a conventional electroless plating package substrate, generally referred to as a GPP (g〇ld pattern plating) plating process. 20 As shown in FIG. 2a It is shown that a complete conductive layer 21 is formed on the upper surface of the substrate 2, and then a patterned photoresist layer is covered on the surface of the conductive layer 21 to expose the circuit wiring to be formed on the surface of the substrate 2. Then, as shown in Fig. The surface of the conductive layer 21 is electrically connected to a metal protective layer 23, wherein the metal protective layer is generally a nickel/gold layer. Finally, referring to the figure and the step of FIG. 2d, the 1301302 is removed. After the photoresist layer 22 is subjected to a process of engraving, the patterned circuit of the upper and lower surfaces of the substrate 2 can be completed by the metal protective layer 23 to protect the underlying surface of the substrate 2 to form a wiring layer 24. Although the GPP plating process is completed There is no need to provide an electroplated wire, but the circuit layer 24 on the surface of the base 5 plate 2 is completely covered with a metal protective layer 23. This & not only consumes too much nickel/gold material, but only the surface circuit layer is covered. In the nickel/gold layer, the two sides of the circuit layer 24 are still exposed and are not protected, so that the electrical coupling between the wafer and the substrate during the oxidation or wire bonding is prone to occur: Furthermore, the material properties are different. The solder resist layer 10, which tends to cause the surface of the substrate, is not easily adhered to the nickel-gold material of the wiring surface, and will affect the reliability of the product and its service life. Therefore, there is a need for a method for fabricating a package substrate of an electroless plating wire, which can improve the wiring area of the circuit conductor, and can provide a good electrical connection quality between the wafer and the package substrate, or between the package substrate and the circuit board, and is reduced. Low production costs. SUMMARY OF THE INVENTION The present invention provides a package substrate, and the surface of the substrate does not need to be separately plated to form an electroplated wire for forming an electrical connection pad, wherein the package substrate package includes: an upper surface, a lower surface, and a plurality of substrates of the plated vias, wherein the plated vias penetrate the upper surface and the lower surface of the substrate; a metal layer on the inner surface of one of the plated vias, and the upper surface and the lower surface of the substrate; a plurality of electrical connection pads a surface of a portion of the metal layer on the upper surface of the substrate, and a portion of the surface of the metal layer on the lower surface of the substrate; and a solder resist layer of FIG. 25 covering the outermost upper and lower surfaces of the substrate and exposing 7 1301662 Some electrical connection pads. Wherein, the metal layer of the surface of the substrate on the surface of the substrate is respectively formed with a patterned circuit. 10 15 ^ The package substrate towel of the present invention, a part of the electrical connection pad and the plated through hole are pulled and connected, and the other part of the electrical connection pad is not electrically connected to the electric ore conduction hole. In a specific embodiment, the electrical connection between the upper surface of the present invention is a first electrical connection pad and a second electrical connection pad, and the first electrical connection is electrically conductive, and the second via is electrically conductive. The electrical connection is not electrically connected to the electrical via. In another embodiment, the electrical connection between the lower surface of the present invention is a third electrical connection and a fourth electrical (four) pure, and the μ three electrical connection is electrically conductive with the electrical via and the fourth electrical The sexual connection is not electrically connected to the electrical conductivity via. Therefore, the circuit of the package substrate of the present invention can be free from external air oxidation and external pollutants, and the electrical connection (4) of the present invention can provide good electrical connection quality between the wafer and the package substrate, or the package substrate and the circuit board. And increase the life of the substrate. Furthermore, the surface of the package substrate of the present invention does not need to be additionally provided with a plating wire **, which not only greatly improves the wiring area of the substrate circuit and can effectively avoid the noise interference caused by the conventional substrate wiring. The invention also relates to a method for fabricating a package substrate, which can mainly conduct a current by using a conductive layer formed on the upper surface and the lower surface of the substrate to respectively perform electroplating on the upper and lower surfaces of the substrate and form an electrical connection. Therefore, the substrate produced by the method of the present invention is a package substrate without a conductive recording wire, so that it is not necessary to provide another plating wire when it is fabricated. The present invention further provides a method for fabricating a package substrate, comprising the steps 1301662. (a) providing an upper surface, a lower surface, a plurality of plated vias penetrating the upper surface and the lower surface of the substrate, and a metal a substrate of the layer, wherein the metal layer is formed on an inner surface of the plating via and the upper surface and the lower surface of the substrate, and the metal layer on the upper surface and the lower surface of the substrate is formed into a patterned circuit; wherein The electroplating via hole penetrates through the upper surface and the lower surface of the substrate, and the metal layer of the upper surface is not electrically connected to the plating via, and the metal layer of the lower surface is not electrically connected to the plating via; (7) forming a first The conductive layer is on the upper surface of the substrate to completely cover the upper surface and the metal layer; (c) forming a patterned first resist layer on the upper surface 10 and the lower surface of the substrate, wherein the first resist layer completely covers the lower surface a metal layer, and 2 exposing a portion of the upper surface of the first conductive layer; (d) removing the 苐 'electric layer exposed on the upper surface to reveal a portion of the upper surface of the metal layer; (e) forming a The patterned second resist layer covers the surface of the first conductive layer '(f) deposited on the outer surface of the first resistive layer to form a metal protective layer on the upper surface of the metal layer 15 (g) removed a first resist layer, a second resist layer, and a first conductive layer; (h) forming a patterned solder resist layer on the upper and lower surfaces of the substrate, and exposing the metal protective layer of the upper surface and a portion of the lower surface metal layer;丨) forming a second conductive layer on the lower surface of the substrate and the surface of the solder resist layer to completely cover the solder resist layer of the circuit layer and the lower surface of Table I; (1) forming a third resist layer on the surface of the substrate 20 a lower surface, and patterned a third resist layer of the lower surface to expose a portion of the lower conductive layer; (k) removing the second conductive layer exposed to the lower surface to expose a portion of the lower surface of the metal layer; And (1) ruthenium plating forms a metal protective layer on the surface of the metal layer exposed on the lower surface. Therefore, the method for fabricating the package substrate of the present invention can increase the circuit wiring area of the substrate surface 9 1301662, and can provide a good electrical connection quality between the wafer and the package substrate, or between the package substrate and the circuit board. Therefore, the electroless wire package substrate produced by the present invention can have good product reliability and long-term use of life. The method for fabricating the package substrate of the present invention may further comprise a step (m) of removing the third resist layer and the second conductive layer covered by the third resist layer, thereby obtaining a package substrate having a complete structure. In the method of fabricating the package substrate of the present invention, the patterned lines formed on the upper and lower surfaces of the substrate may be electrically connected to the metal layer portion of the inner surface of the plated via. In a preferred embodiment, the circuit on the upper surface of the substrate of the present invention is the metal layer described in the present invention, and some of the upper surface lines (metal layers) are not electrically connected to the plated via holes, and the other portion is electrically connected. The surface line (metal layer) is electrically connected to the metal layer on the inner surface of the money guiding via. Moreover, the electrical connection of the lower surface of the substrate can be similarly inferred and the same as the design of the upper surface. In the manufacturing method of the package substrate of the present invention, the third resist layer formed by (4) (1) can completely cover the surface solder resist layer on the upper surface of the substrate and the metal protective layer on the upper surface to protect the completed circuit on the upper surface. In addition, the metal protective layer of the present invention is mainly used to protect the metal layer covered by it from external air oxidation and external pollutants. In addition, the metal bismuth layer can be an electrical connection pad for electrically coupling the wafer to the package substrate or for electrically coupling the package substrate and the circuit board. The type of the & connection pad described herein is not limited, and it is preferably a wire bonding pad (Fmger) for electrically bonding the wire-type semiconductor package and the chip, and a package substrate and a circuit board. Contact pads for sexual coupling (〇(10)忪1301302 -: Pad or Land), or a combination thereof. Furthermore, the metal protective layer of the present invention may be a metal material which is not easily oxidized, and may preferably be gold, nickel, palladium, silver, tin, nickel/palladium, chromium/titanium, nickel/gold, palladium/gold, nickel/bar/ Gold or its combination, the best can be nickel / gold (first recorded and then gold). Therefore, the electrical connection of the invention not only contributes to the electrical connection between the electrical connection of the wire-type package substrate and the gold wire, but also reduces the problem of the electrical connection 塾 oxidation caused by the external environment. Or the electrical quality of the _ conductive element implanted in the electrical connection. The manufacturing method of the package substrate of the present invention can be a method for manufacturing a substrate of a non-electrical ore wire package 10, which firstly uses a first conductive layer as a current conducting road melon to provide a metal protective layer formed on the surface of the upper surface metal layer by electroplating. Current is required to form a metal protective layer of the upper surface metal layer; then, the second conductive layer is used as a current conducting path to provide a current required for electroplating the metal protective layer formed on the surface of the lower surface metal layer, Finally, a metal protective layer of 15 lower surface metal layers is formed. Therefore, the method for fabricating the package substrate of the present invention does not need to additionally provide a plating wire on the surface of the substrate, which can not only greatly increase the wiring area of the substrate circuit, but also effectively avoid the noise interference caused by the conventional substrate wiring the electric clock wire. In addition, the material used in the conductive layer of the present invention may be any of the -20 conductive metal materials or conductive polymers, preferably at least one selected from the group consisting of copper, tin, nickel, chromium, palladium, tungsten, and titanium. The materials of the group. In the method for fabricating the electroless plating package substrate, the process for forming the conductive layer is not limited, and preferably electroplating, electroless plating, chemical vapor deposition, physical vapor deposition, sputtering, evaporation or The combination of methods, 11 1301662 is better to use sputtering, electroless plating. Further, the material used in the metal layer of the present invention may be any conventional electrically conductive metal material, preferably a copper metal material, as a wiring layer on the surface of the substrate. The substrate structure to which the present invention is applicable may be a single-layer circuit board, or may be a two-layer board or a multi-layer circuit board that has completed the front-end line process, and the manufacturing method of the electroless-plated wire package substrate of the present invention is preferably applied to the wire type ( Wire bonding) The package substrate. The insulating material suitable for the substrate of the present invention may preferably be one of a group of organic thin film dielectric materials or liquid organic resin materials; the above materials may be selected from ABF (Ajinomoto Build-up Film), BCB (Benzocyclo). -buthene), LCP (Liquid Crystal Polymer), Pl (Poly-imide), PPE (Poly (phenylene ether)), PTFE (Poly (tetra-fluoroethylene)), FR4, FR5, 15 BT (Bismaleimide Triazine), aromatic nylon A photosensitive or non-photosensitive organic resin such as Aramide or a mixture of an epoxy resin and a glass fiber. Furthermore, the resist layer used in the present invention may be a resistive layer material suitable for the conventional lithography process, and may preferably be a light-sensitive material, and the light-sensitive material may be a dry film or a liquid photoresist. Or a combination thereof. Further, the formation of the resist layer in the present invention is not limited, and it is preferable to use printing, spin coating, lamination, chemical deposition, physical deposition, or a combination of the foregoing. The package substrate of the present invention is formed by forming a circuit layer on the upper and lower surfaces, and then using a conductive layer formed on the upper and lower surfaces of the substrate as current conduction 12 1301662 to form a metal protective layer on the upper surface and the lower surface, respectively. Exclude the traditional layout of electric wires. Therefore, the method for fabricating the wire package substrate of the present invention can be an electroless-plated wire package substrate process, and can meet the requirements of a "fine pitch package" to form a package substrate for high-density circuit wiring. . Furthermore, the method for fabricating the package substrate of the present invention not only effectively utilizes the recording/gold material and reduces the manufacturing cost, but also improves the electrical quality of the product to increase the market competition of the product [embodiment] ~ Please refer to FIG. A schematic diagram of a package substrate without a key conductor according to a preferred embodiment of the present invention. The upper surface of the package substrate 3 of the present embodiment includes a first electrical connection pad 36 electrically connectable to the plating via 4 and a second electrical connection pad not electrically connected to the plating via 4 〇 15 20 . 362. The first electrical connection pads 36 ι and the second electrical connection pads 362 are located on the surface of the patterned metal layer 32 . The periphery of the edge of the first electrical connection pad 361 is not completely covered by the solder resist layer 37, and a large area of the electrical connection region is exposed to facilitate the operation of the wafer package wiring. The lower surface of the package substrate 3 includes a third electrical connection port (6) electrically connectable to the plated via 40, and a fourth electrical connection pad 364 not electrically connected to the plated via. The third electrical connection pad 363 and the fourth electrical connection pad 364 are located on the surface of the patterned metal layer 32, and the third electrical connection pad 363 and the fourth electrical connection pad 364 are not protected by the solder resist layer 37. ^ is the cover. In this example, the second electrical connection of the upper surface of the example is covered by the solder resist layer 37. 13 25 1301662 All the electrical connection pads 361, 362, 363, and 364 in this example are nickel/gold layer metal structures except for the electrical connection between the electrical connection pads of the wire-bonded package substrate and the gold wire. It also increases the environmental resistance of the substrate. However, the method for fabricating the package substrate of the present invention is not limited, and the method described in the following 5 is only a preferred embodiment of the present invention, and is not intended to limit the method of fabricating the package substrate of the present invention. Referring to FIG. 3, FIG. 3(a) to FIG. 3(j) are schematic diagrams showing the process of a package substrate without a plating wire according to a preferred embodiment of the present invention. First, as shown in Fig. 3(a), a substrate 3 is provided, and a copper foil 31 is formed on both the upper surface 1〇3〇1 and the lower surface 302 of the substrate 3 to constitute a core substrate structure. The substrate 3 of the present embodiment comprises an upper surface 301, a lower surface 3〇2, a plurality of plated vias 4A penetrating through the upper and lower surfaces of the substrate, and a metal layer 32. The metal layer 32 is formed on the inner surface of the plating via 4〇, and the upper surface 301 and the lower surface 302 of the substrate 3, and the metal layer 32 on the upper surface 3〇1 of the substrate 3 and the surface 302 of the lower surface 15 is formed separately. A patterned circuit. The substrate 3 can be a single-layer circuit board, and can also be a two-layer board or a multi-layer circuit board that has completed the front-end line processing. A method of forming a patterned line on the surface of the substrate 3 of the present embodiment is obtained by using a pattern etching process, and the metal layer 32 formed on the surface of the substrate 3 of the present embodiment is a circuit on the surface of the substrate. Of course, the method of forming the patterned circuit on the surface of the substrate of the present invention is not limited to the manner described in this example. Here, a copper metal is used as the line conductor. In addition, the circuit on the upper surface of the substrate 3 is formed by the metal layer 32 formed on the upper surface, and a portion of the upper surface metal layer 32 (line) is not electrically connected to the electric 130162 forged via 4032, and A portion of the upper surface metal layer 32 (line) is electrically connected to the plated via 40. Similarly, part of the lower surface metal layer 32 is not electrically connected to the plating via 4, and another portion of the lower surface metal layer 32 is electrically connected to the plating via 40. Then, as shown in FIG. 3(b), a first conductive layer 33 is formed on the upper surface of the substrate 3 and completely covers the upper surface 3〇1 and the upper surface metal layer 32 of the substrate 3 as a subsequent upper surface plating process. Current conduction path. Wherein, the first conductive layer 33 is preferably a combination of electroplating, electroless plating, chemical vapor deposition, physical vapor deposition, sputtering, evaporation or a combination thereof; more preferably sputtering can be used without electrolysis. plating. A first resist layer is formed on the upper surface and the lower surface of the substrate 3, and then a patterned first process layer 34 is formed by a patterning process. The $ middle-resistive layer 34 is a metal layer 32 that completely covers the lower surface and exposes a portion of the upper surface of the first conductive layer 33. 15 20 "Refer to Figure 3 (e), remove the exposed metal on the upper surface - the first conductive layer 33 outside the resist layer. This is "disposed to the first - the same - The opening of the layer 34 is formed by the first resist layer 35. The opening/forming method is provided to provide a substrate junction as shown in Fig. 3, and then, as shown in Fig. 3(e), the protective layer is formed. _, two-shift = gold: 15 13 ο 1662 1 ^ The first resist layer 34, the second resist layer 35, and the first conductive layer 33, that is, a substrate structure as shown in Fig. 3 (f) is obtained. The metal protective layer % of the upper surface has formed a +, and the metal protective layer 36 includes a first electrical connection pad 36 electrically connectable to the plating via 4 and a second electrical connection electrically non-conductive. Pad 5 362 (ie, the independent wire bonding pad on the upper surface of the wire-bonding package substrate). After the upper surface of the substrate 3 is completed, in order to protect the copper metal lines on the upper and lower surfaces of the substrate 3, a solder resist layer 37 is formed. Green lacquer or black lacquer material • on the surface of the substrate 3, and then patterned to expose the metal protective layer 36 of the upper surface and a portion of the metal layer 32 of the lower surface, For the structure of the substrate, please refer to FIG. 3(g), and the solder resist layer can be coated, printed or pasted to cover the upper and lower surfaces of the substrate. 32 will be used as a region for forming the metal protective layer % of the lower surface. Then, the process of the lower surface of the substrate is performed, as shown in FIG. 3(h), a f-conductive layer 38 is formed on the lower surface of the substrate 3 and solder-proof. The surface of the layer 37 is completely covered with the lower surface of the substrate and the lower surface solder resist layer 37 as a current conduction path for the subsequent lower surface electroplating process. In the crucible, the second conductive layer is preferably used. Electroplating, electroless plating, chemical vapor deposition, physical vapor deposition, sputtering, evaporation or a combination thereof; more preferably, a carbon bond can be used to deplate. ", after the electric 20, a third resistance is formed. The layer 39 covers the second resist layer 29 covering the upper surface of the substrate 3 and the lower surface of the lower surface and is subjected to a patterning process to expose a portion of the second conductive layer 38 of the I surface; then the second conductive layer exposed by the lower surface is removed. Layer 38' obtains a substrate structure as shown in Fig. 3(1)The lower surface plating process is performed as shown in Fig. 3 (1), and a portion of the conductive layer 32 on which the lower surface is exposed 16 1301662 is plated to form a metal protective layer of nickel/gold. Then, through the foregoing process, the formed metal protective layer 36 includes a third electrical connection pad 363 electrically connected to the electric ore via 40, and a fourth electrically conductive pad 364 electrically non-conductive. Finally, the second resist layer 39 of the upper and lower surfaces 5 of the substrate and the second conductive layer 38 covered by the third resist layer 39 are removed, that is, the process of the electroless-plated lead package substrate 3 of the present embodiment is completed, and the process is performed by the example. The substrate structure formed is as shown in FIG. Therefore, in the circuit wiring on the upper surface of the substrate 3 of the present embodiment, the metal protection layer 36 includes a plurality of electrical connection pads 361 and 362, and the electrical connection pads are used as a wafer (not shown). A wire bonding pad for electrically coupling with the wire-type package substrate 3. In the circuit wiring of the lower surface of the substrate 3 of the present embodiment, the metal protection layer 36 includes a plurality of electrical connection pads 363, 364, and the electrical connection pads are used as the package substrate 3 and the circuit board (not shown) A contact pad or land for electrical coupling. In addition to the electrical contact pads described in this embodiment, where the substrate is subjected to electroplating of the nickel/gold process, the structure of the electroplated nickel/gold can be formed by the method disclosed in the present invention. In summary, the method for fabricating the electroless wire-bonding substrate of the present invention not only reduces the manufacturing cost but also improves the product yield, thereby increasing the market competitiveness of the product. Furthermore, the manufacturing method of the present invention can increase the wiring area of the substrate circuit wires, and does not need to deposit a gold layer on the surface of the entire circuit layer, which can greatly reduce the cost of electroplating nickel/gold, and can also provide wafer and package. Good electrical connection quality between the substrate or the package substrate and the circuit board, eliminating the problem of wire oxidation. 17 1301662 The above embodiments are merely examples for the convenience of the description, and the scope of the claims is intended to be limited by the scope of the claims. - 5 [Simplified Schematic Description] Fig. 1 is a schematic cross-sectional view showing a package substrate having a plated wire. 2(4) to 2(4) are schematic diagrams showing the process of a conventional package substrate of an electroless plating wire. 3(4) to 3(1) are schematic views showing the process of the package substrate 10 of the present invention-preferred embodiment. 4 is a sound and diagram of a package substrate without a power wire according to a preferred embodiment of the present invention. ~ [Main component symbol description] 1 substrate 12 I/O contact 21 conductive layer 24 circuit layer 32 metal layer 35 second resist layer 38 second conductive layer 301 upper surface 10 circuit layer 13 metal protective layer 2 2 photoresist layer 3 Substrate 33 first conductive layer 36 metal protective layer 39 third resistive layer 302 lower surface 11 electroplated wire 2 substrate 23 metal protective layer 31 copper foil 34 first resistive layer 37 solder mask 40 plating via 361 first electrical connection pad 363 third electrical connection pad 362 second electrical connection pad 364 fourth electrical connection pad 18 15