TWI307547B - Method for fabricating substrate with plated metal layer over pads thereon - Google Patents

Description

ΛΜ 92115796

1307547 ping, invention description (1) [, the technical field of the invention] The present invention relates to a method for electrically connecting a semiconductor package substrate to a die-die layer, especially when the pad of the substrate for wafer packaging is exposed The surface is plated with a nickel/gold metal layer to provide an electrical connection pad of good quality to the substrate. [Prior Art] A surface of a general semiconductor package substrate is formed with a plurality of conductive lines made of, for example, steel, and is extended to form an electrical connection pad for signal transmission. Generally, in order to smoothly electrically couple conductive elements (such as gold wires, solder bumps or solder balls) to the surface of the wafer or circuit board, a layer such as nickel/gold must be plated on the exposed surface of the electrical connection pad. N丨/AU), nickel/silver' (Ni/Ag) metal layer is used as the bonding layer between the soldering conductive element and the electrical connection port. Conventional electrical connection pads generally include a bump-bonded bump pad and a solder pad (Pres〇lder pa) that provides Flip-chip Package Substrate and wafer electrical coupling. 〇, or a wire bonding pad for wire bonding packages and wafers, or a ball pad for electrically soldering packages and other boards. ^ The nickel/gold metal layer on the surface of the electrical connection pad prevents oxidation of the electrical connection pad and improves the Solder Joint Reliability between the conductive element and the electrical connection pad. The method of forming a nickel/gold metal layer on a pad generally includes an electroless nickel/gold process, an ion splash method, a plasma deposition method, and an electroplated nickel/gold process, etc. The chemical nickel/gold process often occurs, for example, by a number of jump plating. With black pad

1307547 Case No. 92115796, invention description (2) (Black pad), such as poor solderability or insufficient solder joint strength, in which the problem of the money jump is based on the system. Lai Zinc = rest - during the re-production of the period, even if all the working conditions have been reduced: there will be a phenomenon that the electroplating ability is not enough to be fully plated, so that ^: still plated, so the phenomenon of exposed steel occurs; and the black pad problem: open u: When the nickel surface is subjected to immersion gold replacement, the nickel surface is excessively oxidized. = The volume of the gold atom is irregularly heavy. 1 = sparsely porous, causing the bottom nickel to continue to undergo chemical battery effect: promote 匕 = raw Oxidation and the old 4匕' so that the gold surface is produced underneath? However, the continuous production of pad 3 peeling and peeling cannot be electrically coupled to each other. The cost of electropolymerization is too high and does not meet economic benefits. The age of the law or the record of the record: "One: the industry often uses electroplating to form a nickel/gold metal layer on the electrical connection pad. As shown in the figure, the conventional plating / gold / ΙΓΛ front process, for example Line patterning work, lower circuit layer, ^ ^; L, u (such as wire mat or: ball 塾 in the etc.) base = upper plate solder resist layer 15.) The outer surface of the reduced plate 1 is covered with - 1 shows the electrical connection pad i 4 on the substrate. Although it has been disclosed that the electric 5 pad 14 is plated with a nickel/gold metal layer 16 structure, in order to form the junction, a conductive line must be formed on the substrate while being additionally disposed. A plurality of wires 17, and a nickel/gold metal layer 16 is plated on the '* connection pad 14 by means of a plating wire 17. Thus, although the electrical connection 形成 14 is formed,

Page 9 1307547 Deprecation - _92115796

Five inventions description (3) / gold metal layer 1 6, but must also be laid out but 'occupies the wiring area on the substrate 1, ^ a,,, row plating, the antenna effect of the electric ore wire is easy to The second frequency makes Xiaori Temple, because of the multiple engraved way CEtchbaclO can cut off the electric clock guide: '. And if you use the back part of the plated wire. Therefore, the structure of the nickel/gold metal layer is left on the substrate ===, but the inclusion of -4 is formed by the gentleman. Therefore, the problem of the end of the 拉丁 拉丁 σ 堆 堆 堆 堆 堆 堆 堆 堆 堆 堆 堆 堆 堆 堆 堆 堆 堆 堆 堆 堆 堆 堆 堆 堆 堆 堆 堆 堆 堆 堆 堆 堆 堆 堆 堆 堆 堆 堆 堆 堆 堆 堆 堆 堆When the U-noise is coated with the nickel/gold metal layer 16, the surface of the plated wire is also formed with a nickel/gold metal layer, and the subsequent etching must be performed multiple times to remove the plated wire 1 of the helmet circuit. 7 'Therefore, the substrate is seriously scratched. Moreover, in the case where the substrate wiring is complicated and the electrical connection pad is formed with a high density, that is, there is no effective remaining substrate area for additionally providing the plating wire, resulting in the electric clock recording/gold process. The difficulty is increasing. ''' " Another well-known electroplating process is made by Gold Pattern Plating (GPP). Please refer to the 2nd to 2_, the process is first A conductive layer 21 (shown in FIG. 2A) is formed on each of the upper surface and the lower surface of the substrate 2, and a plurality of via holes (PTH) or blind vias (not shown) are formed in the substrate 2. Conductively conducting the conductive layer 21 on the upper and lower surfaces of the substrate. As shown in FIG. 2B, the conductive layer 2i of the substrate 2 covers a photoresist layer 22 (?1: 〇165丨31:), and the photoresist layer 22 is formed with a plurality of openings to expose The conductive layer 2 1 'preparing the wiring region is prepared to be a current conducting path to plate a layer of nickel/gold metal 23 on the portion of the conductive layer 21 that is not covered by the photoresist layer 22.

17228 懋 (Revised). ptc Page 10 Seven gold mi ΪΓΞ shown 'Remove the photoresist layer 22, re-use the town / 2 3 eve: ♦ ; 2 two-resist layer 'Using etching technology to nickel / Gold metal layer

Γ: the conductive line pattern is patterned such that the conductive layer m is formed on the surface of the line pattern 21 a - the zirconium & the core I _ has a nickel/gold metal layer 23, as shown in Fig. 2D ( n 0 This GPP technology uses a wide layer of lead-in & %. _ a instead of a plating wire to provide a zinc/full plating current through the surface of the substrate only for the entire substrate to be recorded/to all conductive lines. Previous:1 (contains electricity: raw connection 塾 and Li Θ main ☆ day ~ send nickel/gold metal layer, its material cost is extremely i Γ it it 路 路 路 surface layer is covered with nickel gold layer, which also leads to the implementation of the substrate Line patterning shovel surname ra „. «Insult to heart α * β $ L In the private time, because the solder resist layer and the nickel gold layer material combination. The test is difficult, can not reach a stable knot, therefore, how to simplify the process Steps, cost less to avoid the flashing and black-free traditional electroplating nickel/gold process derived from the traditional chemical nickel/gold process. 1 .1, 1 exemption [invention] Problem: Providing cloud:: 2 The shortcomings of the prior art, the main purpose of the present invention is: Ϊ = armored substrate: sexual connection The square layer of the metal layer of the electric money is formed, and the right side is applied to the green enamel. The surface of the outer surface is plated with a metal such as nickel/gold coupled to the metal, the solder bump or the solder ball and the wafer or the circuit board. The method of forming the electroplated 塾 body ^ 塾 塾 塾 塾 塾 塾 塾 塾 目的 目的 目的 目的 目的 目的 目的 塾 塾 塾 塾 塾 塾 塾 塾 塾 塾 塾 塾 塾 塾 塾 塾 塾 塾 塾 塾 塾 塾 塾 塾 塾 塾 塾 塾 塾 塾Gold process

17228 懋 (Revised). pt Page 11 1307547 Case No. 92115796 V. Invention Description (5) » The resulting jump plating and ^ The pad of the present invention forms an electroplated cloth to form an electric ore wire to reduce the wiring of the present invention. The cost of forming gold on the entire layer of connection pads forming the plate. * The pads of the present invention form a plating degree. Year" month / / 曰 correction of the black pad and other issues for the purpose of the metal layer, by the large plated wire re-purpose metal layer on the layer of the desired nickel and a metal layer to effectively improve the reliability of the package structure . The invention provides a method for electrically connecting a semiconductor package substrate, which does not need to increase the effective wiring area of the package substrate in the rain of the package substrate, and the noise interference problem is derived. The invention provides a method for electrically connecting a semiconductor package substrate, which can avoid the need for the conventional process to be used in the package base cover '"record/gold metal layer' only in the electrical/gold metal layer, thereby effectively reducing the plating record/system supply. The invention relates to a method for electrically connecting a semiconductor package substrate, which is used for increasing the thickness of the circuit on the substrate, and has a plurality of conductive lines, wherein the surface of the substrate covers less than one opening, and the invention provides a method The method includes the steps of: providing a semi-conductive first resistive layer with an electrical connection pad; and connecting the adjacent vias to adjacent to form an electrical connection pad for at least one surface specific package substrate; and further comprising a resistive layer Forming a conductive line on the conductive layer; forming an electrically conductive film in the opening, so that the conductive film is electrically connected to the adjacent conductive line and the electrical connection pad; the first resistive layer on the surface of the substrate After the removal, a second resist layer is disposed on the substrate, and the second resist layer is formed with a plurality of openings to expose the electrical connection pads; and then an electroplating process is performed to make the electricity Sook electrically connected to the exposed surface of the bond to be formed with a metal layer such as a nickel / gold, and then sequentially the second barrier layer formed on the substrate and the conductive film is removed; ^ can then be formed on the surface of a package substrate table repellent

17228 Full Punishment (Revised Edition).ptc Page 12

1307547 —-^Z1 Case No. 92115796 g, invention description (6) __ fresh layer 'and the solder resist layer has a plurality of open lip layer electrical connection pads, and the solder resist layer has been completed The size of the electrical connection. The opening aperture can be larger or smaller than the semiconductor 4 of the semiconductor package substrate of the present invention, and can not only provide an electrical connection, but also electrical coupling with the wafer or the circuit board; It can also avoid the oxidation of s fresh balls, and avoid the problems of flash plating and black mats which are generated when chemical nickel/gold is known, which can effectively improve the sealing performance; at the same time, electroplating nickel/gold There is no need to lay an electric ore wire on the surface of the package substrate, so as to greatly increase the effective wiring area of the package substrate, and reduce the noise interference caused by the plating of the electroplated wire; furthermore, it can also avoid the electric nickel ore. In the gold process, a nickel/gold metal layer is required to be coated on the entire circuit layer of the package substrate, which can effectively reduce the cost of electroplating nickel/gold. The invention is further illustrated by the following examples, but the invention is not limited by the examples. In particular, the electroplated metal layer of the electrical connection pad of the present invention can be widely applied to a general package substrate. The drawings and the description illustrate the implementation of the flip chip package substrate, but this is not intended to limit the scope of application of the present invention. To be stated. [Embodiment] Please refer to Fig. 3, which is a schematic cross-sectional view showing an electrical connection of a metallization layer of a semiconductor package substrate to which the present invention is applied. The package substrate 4 is a flip-chip ball grid array type (F 1 i p c h i p b a 11 grid array) package substrate, which includes a plurality of insulating layers 4 and

17228 懋 (Revised). ptc Page 13 Case No. 92115796 Leap year; Month "η 1307547 Correction +, invention description (7) Conductive line 42 of edge β layer interleaved, through the insulation layer 4 1 A via 43 for electrically connecting the conductive trace 42 and a solder resist layer 48 for covering the surface of the substrate are provided. The insulating layer 41 of the substrate 4 may be made of an organic material, a fiber-reinforced organic material, or a particle-reinforced organic material, such as an Epoxy resin. Amine (p〇iyimide), cis-bis-succinic acid-imide/trinitrogen trap ("3111&1 to 11^(^1:]^&2;11^_!^36(1) resin, cyanide The conductive line 42 is formed by forming a metal conductive layer, for example, a copper layer, on the insulating layer 41, and forming a line patterned conductive line 42 by using an etching technique. The line 42 can also form a fine circuit in a patterned electro-mineral resist layer, and the conductive line 42 on the second surface 4b of the first surface of the second surface: the second surface 4b is connected to the crucible 44', for example, in the first The two bumps on the surface 4a or the pre-solder solder bumps 1 are provided to the J-shaped Flip chiP semiconductor wafer 50, which can be made by a bump, and a solder bump (Solder bump) 49a The electrical connection on the 4th side of the slab is 4, and in the second base, the buddy pad (Bau _) is used to connect::=1)49b Providing the completed flip chip packaging process; the conductor 曰: 'sexually connected to an external device (not shown), such as solder bonding to the first surface of the substrate due to the conductive line 42 and the electrical connection J 44 J And the second surface: genus _ ___ 虱 or effective and solder 17228 懋 (amendment) page 14 correction 1307547 case number 92915796_Ο year > month / / η i, invention description (8) Λ & block 4 9 a or solder ball 4 9 b bonding ability, will be exposed in the electrical connection 塾 4 4 > surface electrical chain has a metal layer 44 a as a metal barrier layer, the general metal resistance I1 early layer contains the town a layer and a gold protective layer formed on the electrical connection pad 44. However, the barrier layer can also be electroplated by electroless plating or physical vapor deposition (Electroless plating or physical vapor deposition) Any of a group of materials such as gold, nickel, palladium, silver, tin, nickel/ki, niobium/titanium, niobium/gold or nickel/palladium/gold deposited by a method such as physical vapor deposition ion. Forming a solder resist layer 48 to cover the surface of the substrate 4, and the solder resist layer is formed with a plurality of openings for electrically connecting The pad is exposed to the opening of the solder resist layer, wherein at least one of the electrical connection pads 44 is not in communication with any of the key wires. 4A to 4th, FIG. 4 is a semiconductor package substrate property of the present invention. A schematic diagram of a method of forming a metallization layer by a bond pad.

As shown in FIG. 4A, a package substrate 4 is first provided, which may be a flip chip package substrate as shown in FIG. 3 or a wire bonding package substrate. The package substrate 2 requires a prior process, for example, a plurality of vias (ρτΗ) or blind vias YV/a) (not shown) are formed therein, and the package substrate has a line patterned conductive line 4 2 , the plurality of electrical connections 塾 44 are guided. About line patterning technology $ = : The well-known process technology, which is not the technical characteristics of this case, so J = as shown in Figure 4, or covered or taped, etc. The surface of the substrate 4 is printed on the surface of the substrate 4 without being printed or spin-coated. The first p and the layer 4 5 may be a dry film

乃年年月// a 5. Invention Description (9) ~ ~~ As shown in Figure 4C, the first resistive layer 45 is laser-fired or exposed by exposure to at least one opening. 4 5 a, and the opening 4 5 a is connectable to the adjacent conductive line 42. An electrically conductive film 46' is formed in the first resistive opening 45a, as shown in FIG. 4D, so that the conductive film 46 is electrically connected to the adjacent conductive line 4 2 and the electrical connection pad. 4 4. The conductive film 46 is mainly composed of a metal, an alloy or a plurality of stacked metal layers, which may be selected from the group consisting of copper, tin, copper, titanium, copper-chromium alloy. And a group formed by a tin-alloy alloy. However, according to actual experience, the conductive film 46 is composed of copper or palladium particles (especially electroless plating), etc. By physical vapor deposition (PVD), chemical vapor deposition (CVD), electroless plating, or any physical 'deposition, such as sputtering, evaporation, arc vapor deposition (Arc vapor deposition), ion beam sputtering (Ion beam sputtering), laser ablation deposition, plasma-promoted chemical vapor deposition, or chemical vapor deposition of an organic metal, formed on the substrate In the first resistive layer opening 45a. As shown in FIG. 4E, the first layer of the substrate surface is then removed by chemical means (such as etching) or by physical tearing or laser removal. 4 5. The conductive film 46 is exposed on the substrate to serve as a current conduction path required for plating the metal layer on the electrical connection pad as will be described later. As shown in FIG. 4F, printing and spinning are further performed on the substrate. The second resist layer 47 is applied by coating or laminating, and the second resist layer 47 is formed with a plurality of openings

17228 懋 (Revised). ptc Page 16 mwu ^11ϋΥί)6

Hand, invention description (10) 4 7 a to reveal the electrical connection pad 4 4 . As shown in FIG. 4G, the package substrate 4 is then plated with a metal layer by electroplating (EleCtroplating), which may be gold, nickel ' & silver, tin, recorded / her, chrome / Titanium 'records / gold, Ji / Jin or recorded ^ Ba / gold, etc. formed by the group. By virtue of the conductive property of the conductive film 46, the crucible can be used as a current conduction path during electroplating, preferably by electroplating a nickel/gold metal layer, which is first plated with nickel, and then electroplated = layer of gold, nickel The gold metal can be electroplated on the surface of the electrical connection via the conductive film 46. The exposed surface of the electrical connection pad 44 is covered with electricity, and the metal layer 44a's the selection of the plated metal material of the present invention. It can be only 1;! The description of the record, gold or other metal is directly linked to the exposed surface of the electric electricity I1 in the electric power I1, and the exchange surface is @@明 implementation H Ί间早之(四), all belong to The present invention: after the completion of the plating/gold metal layer 44a on the exposed surface of the electrical connection pad 44, the second resist layer 47 is removed first, and then, Ϊ: dry etching or wet etching The electro-optical film 46 previously used as the electroplating current conducting path is removed, that is, the exposed metal layer 44& is covered to cover the exposed surface of the electrical connecting port. Rejected: No.: What? Then, the surface of the package substrate 4 is covered with - ίίΛ二1^48', such as green lacquer, to protect the sealant base = environmental pollution damage, the solder resist layer 48 is formed with a plurality of = 2% electric clock metal layer 4 "Electrical connection pad" is capable of forming a hole 48a' of the layer, wherein 'the solder mask opening 48 can be = the size of the electrical connection 44' to form - the solder mask is defined ((4) Her mask defined) Connecting the pad, or the repellent layer opening,

Method of genus layer body package substrate electrical connection pad to form electroplated gold can provide electrical connection 塾 exposed table ® coated with - with dart / gold metal layer said $ equal 盥 a κ red two effective Lu gold wire, welding钖 bumps, or solder balls 2 = boundary; secondly, the electrical connection; can also avoid the jump caused by the electrical connection pad process: = caused by sputum, and avoid the chemical nickel / gold trust Sexuality; $hours in electricity: 3 black mats and other issues, can effectively improve the package structure plating wire, so that it is large. In the case of gold, it is not necessary to arrange the plating wires on the surface of the package substrate, (3) the effective wiring area of the package substrate, and reduce the noise interference problem of the conventional electroplated nickel/gold potential #何^; Nickel/gold containing: ¥, must be on the entire circuit layer of the package substrate. The metal layer' can effectively reduce the cost of electroplating nickel/gold. The electric limb package substrate electrical connection pad described in the method of the invention is formed into a plated metal layer pad, a bump pad, a pre-connection, for example In the package substrate, the wire-separating connection pad is a coin or a solder ball pad. The previous pattern is only used for the current conduction path when the part is plated, and the number of the electrical connection pads is a. The design and division of the mask and the mask layer are performed on the substrate surface according to the actual process, and the process can be implemented on the substrate and the effect of the above, instead of using the carcass embodiment. The invention is only intended to be illustrative of the features of the invention, and without departing from the invention.

1307547 Case No. 92115796; Month/f 曰 Amendment _ Lan, Invention Description (12) ·» In the spirit and technology of the invention, any equivalent changes and modifications made by the use of the invention disclosed herein, All should still be covered by the scope of the patent application below.

17228 全懋 (Revised).pic Page 19 more than a month ί /曰Amendment No. 92115796 1307547 Illustration 'Simple description ・4 [Simple diagram] \ Figure 1 shows the use of electroplated wires on the semiconductor package substrate A schematic diagram of a nickel/gold metal layer formed on the electrical connection pad; 2A to 2D are printed on the electrical connection of the semiconductor package substrate by a gold layer patterned plating (GPP) process. FIG. 3 is a cross-sectional view of a substrate in which an electroplated metal layer is formed on an electrical connection pad of a semiconductor package substrate according to the present invention. FIGS. 4A to 4I are semiconductors of the present invention. A schematic diagram of a method of forming a plated metal layer on a package substrate. [Main component symbol description] 1·, 2, 4 substrate 4a I·− surface 4b second surface 11 upper wiring layer 12 lower wiring layer 13 via hole 14, 44 electrical connection 塾1 5, 48 solder resist layer 16, 23, 44a metal layer 17 electroplated wire 21 conductive layer 21a circuit pattern 22 photoresist layer 46 conductive film 41 insulating layer 42 conductive line 43 through hole 45 first resist layer 45a first resistive layer opening 47 second resistive layer 4 7a second Resistance layer opening 4 8a solder resist layer opening 4 9a solder bump 49b solder ball 50 semiconductor wafer

17228 懋 (Revised). ptc Page 20

Claims (1)

1307547 Case No. 92115796 bu , I „ ----------a__j^sL Six' Patent Application Scope ----- .h.—Electrical connection pads for semiconductor package substrates form electroplated metal-methods, The step includes: providing a semiconductor package substrate having at least one surface formed with a plurality of conductive lines and electrical pads; the first resistive layer is covered on the surface of the substrate, and at least one opening is formed in the first resist And the opening is connected to the adjacent conductive 4 channel; forming a conductive film in the first resistive layer opening, so that the conductive film is electrically connected to the adjacent conductive line and the electrical connection; a resist layer, and a second dance is laid on the substrate - and the second resist layer is formed with a plurality of openings to expose the electrical connection; the substrate is subjected to a key process to make the electrical connection The exposed surface is plated with a metal layer; the second resist layer on the substrate is removed from the conductive film; and a solder resist layer is formed on the surface of the package substrate, and the anti-corrosion layer is formed with a plurality of openings to reveal the completed Electroplated metal layer electrical ^ pads. A method for electrically connecting a semiconductor package substrate of the first application of the patent scope to a metal plating layer, wherein 'the hole of the solder resist layer is larger than ^ is smaller than the size of the electrical connection pad' - 3. The method for forming a plated metal layer by electrically connecting the semiconductor package substrate of the first aspect of the patent, wherein the solder resist layer is a green paint. 乂4. The electrical connection of the semiconductor package substrate according to claim 1 of the patent scope 塾shape 1307547 Case No. 92115796 Amendment Six Circumference ί $ Liqin #·Electricity Please, the application of the crystal cladding 1 is the plate base of the method of the layer 5 of the method of the French side. The special plate of the special plate is required to be plated with a power-on seal, such as a pad-shaped pad, and the base plate of the package is guided by a half-shaped wire. The plate is mounted on the base of the method. The special plate of the special plate is required to be plated with a power seal such as a forming pad. The base of the package is connected to the middle of the package. The solder bump is convexly connected to the illuminator. The pad is connected to the il board. The basic package is in the middle of the package. The 1J method is the first layer of the prescription. Please apply the plating to the pad. The ball is soldered to the pad - l8c il. The electricity is 8. The application scope is the first item. The method for forming a plated metal layer by the electrical connection pad of the semiconductor package substrate, wherein the electrical connection pad is a wire bonding pad 0. 9. The method for forming a plated metal layer according to the electrical connection pad of the semiconductor package substrate of claim 1 Wherein, the plated metal layer is formed by any one of a group consisting of gold, nickel, kiln, silver, tin, nickel/ki, chrome/titanium, recorded/gold,: ίε/gold, and nickel/palladium/gold. . The method for forming a plated metal layer of the semiconductor package substrate electrical connection pad according to claim 1, wherein the conductive film is selected from the group consisting of copper, tin, nickel, chromium, titanium, copper-chromium alloy and tin-lead Formed by any of the groups of alloys. 11. The method of forming a metallization layer by a semiconductor package substrate electrical connection pad according to claim 1, wherein the conductive film is sputtered 17228 懋 (Revised). ptc Page 22 1307547 Case No. 92115796 彳〇 彡 / / / 曰 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ (Deposition) is formed in any way. A method of forming a metal plating layer by a semiconductor package substrate electrical connection pad according to claim 1, wherein the first barrier layer is a dry film or tape. A method of forming a metallization layer by a semiconductor package substrate electrical connection pad according to claim 1, wherein the first barrier layer is formed with at least one opening by any of laser and exposure development. A method of forming a metal plating layer by a semiconductor package substrate electrical connection pad according to claim 1, wherein the conductive film is removed from the substrate surface by an etching method. 17228 all thoughts (amendment).ptc Page 23 1307547 Case number two - , ^ ^ απ Λ -------- Dry, 丨 I Η _ correction strict * (Invention name: semiconductor package substrate electrical connection The method of forming a metallized layer by a pad) 921157% 3J 岑月I丨曰----. 法法; Ή ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成And opening the opening to the adjacent conductive line; forming a conductive film (Elec忖icany conductive f 1 1 m) in the opening, so that the conductive film is electrically Leading adjacent conductive lines and pads, removing the first resist layer on the surface of the substrate, and then laying a second resist layer on the substrate, and the second resist layer is formed with a plurality of openings to expose the Electrically connecting the pad; then performing an electroplating process on the substrate, forming a metal layer on the exposed surface of the electrical connection pad, and removing the second resist layer on the substrate, and then coating the surface of the substrate The solder resist layer 'and the solder resist has a plurality of openings to reveal the completed metallization layer Electrical connection pad. The substrate is formed with a plate of metal plate over formed with a plurality of traces and pads on at least a surface thereof, and a first resist layer is formed on The surface of the substrate with at least one opening contacted to the traces. A conductive film is formed on the opening of the first resist layer to ]7228 全愁(Revised).ptc Page 4 1307547 —-- Plug number 921157QR_年子月II 曰__ p, Chinese invention summary (Invention name: semiconductor package substrate electrical connection pad to form a plated metal layer) 44 electrical connection pad 44a metal layer 46 conductive film 4 7 second resistance layer 4 7 a second resistance layer opening 6. Abstract: invention name: METHOD FOR FABRICATING SUBSTRATE WITH PLATED METAL LAYER OVER PADS THEREON) connect the Traces and pads. Then, the first resist layer is removed and a second resist layer is formed on the substrate with a plurality of openings to expose the pads. After a metal layer is deposited on the pads by a electroplating method, the second resist layer And the conduct ive film are removed. Finally, a solder mask is applied on the surface of the substrate and formed with a 17228 懋 (Revised). Ptc Page 5