1310589 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種封裝基板表面結構及其製作方法， 尤指一種適用於縮短線寬及線距之封裝基板表面結構及其 5 製作方法。 【先前技術】 隨著電子產業的蓬勃發展，電子產品亦逐漸進入多功 能、高性能的研發方向。為滿足半導體封裝件高積集度 1〇 (Integration)以及微型化（Miniaturization)的封裝要求，提供 多數主被動元件及線路連接之電路板，亦逐漸由雙層板演 變成多層板，以使在有限的空間下，藉由層間連接技術 (Interlayer connection)擴大電路板上可利用的佈線面積而 配合高電子密度之積體電路（Integrated circuit)需求。 15 惟一般半導體裝置之製程，首先係由晶片載板製造業 者生產適用於該半導體裝置之晶片載板，如基板或導線 架。之後再將該些晶片載板交由半導體封裝業者進行置 晶、壓模、以及植球等製程。 半導體封裝結構是將半導體晶片黏貼於基板頂面，進 20 行打線接合（wire bonding)或覆晶接合（Flip chip)封裝，再於 基板之背面植以錫球以進行電性連接。因此，習知的封裝 基板表面結構請參考圖1A至1B，如圖1A所示，其包括一封 裝基板11以及複數個金屬墊14。此封裝基板11的表面具有 一電性連接墊12且具有一圖案化之防焊層13，此圖案化的 5 1310589 防焊層顯露出電性連接墊12。同時，於此電性連接塾12表 面利用電鍍或無電電鍵的方式形成金屬墊14，此金屬塾14 的材料可為錫或錦/金等等。接著，再如_所示，於金屬 塾14表面經由印刷或電鐘形成銲錫材料，再經迴焊形成一 預銲錫凸塊15(pres〇lder bump)。最後再經由此—預鲜錫凸 塊15而可與一晶片接合。 15 此種結構及製程雖可達到電性連接的目的。然而，此 種習知封裝基板的表面結構，由於迴焊過程㈣叫中金屬 塾14與預銲錫凸塊15之界面產生反應，並形成介金屬化合 物（Intermetallic compound)，此外，若電性連接墊^未形成 金屬墊14㈣直接與預銲錫凸塊15接觸，電性連接塾⑽ 直接預銲錫凸塊15界面亦會產生介金屬化合物。因介金屬 化合物係屬於脆性材料’而在可#度測試時極㈣成裂纹 d’因此裂紋之形成，將使由電性連接塾12、金屬塾 14與預銲錫凸塊15所構成之電性連接結構劣化，植覆上去 的預録錫凸塊15也容^掉落。其機械性f的應力變差，會 使得接點（joint)的品質變差，而降低了基板的可二 者，因該金屬墊14與預銲錫凸塊15之界面係為平面二的接 觸’-旦形成狀則該錢極胃延著該金屬墊丨 凸塊15之界面傳播，使該電性連接結構劣化程度i劇^ +導體封裝基板表面結構線寬及線距之縮短之趨勢 屬塾14與預銲錫凸塊15或電性連接塾12與預銲錫凸塊⑽ 接觸面積亦會變小，此時裂紋傳播的影響更加顯著，因此 有必要藉由改變該電性連接結構之幾何軸，抑制 20 1310589 播’強化基板電性連接結構的可靠度。 【發明内容】[Technical Field] The present invention relates to a surface structure of a package substrate and a method of fabricating the same, and more particularly to a surface structure of a package substrate suitable for shortening line width and line pitch, and a method of fabricating the same. [Prior Art] With the rapid development of the electronics industry, electronic products have gradually entered the direction of multi-functional and high-performance research and development. In order to meet the packaging requirements of semiconductor package high integration and miniaturization, most active and passive components and circuit-connected circuit boards are also gradually evolved from double-layer boards into multi-layer boards to enable In a limited space, the interlayer area is used to expand the available wiring area on the board to meet the high electron density integrated circuit requirements. 15 However, the general semiconductor device process is firstly produced by a wafer carrier manufacturer for a wafer carrier, such as a substrate or a lead frame, suitable for the semiconductor device. The wafer carriers are then transferred to a semiconductor package manufacturer for crystallization, stamping, and ball placement. In the semiconductor package structure, the semiconductor wafer is adhered to the top surface of the substrate, and 20 rows of wire bonding or Flip chip packages are placed, and then solder balls are implanted on the back surface of the substrate for electrical connection. Therefore, the conventional package substrate surface structure is described with reference to Figs. 1A to 1B. As shown in Fig. 1A, it includes a package substrate 11 and a plurality of metal pads 14. The surface of the package substrate 11 has an electrical connection pad 12 and has a patterned solder mask layer 13. The patterned 5 1310589 solder mask reveals the electrical connection pads 12. At the same time, the metal pad 14 is formed by electroplating or electroless bonding on the surface of the electrical connection 12, and the material of the metal crucible 14 may be tin or brocade/gold or the like. Next, as shown in Fig., a solder material is formed on the surface of the metal crucible 14 via a printing or electric clock, and a pre-solder bump 15 is formed by reflow soldering. Finally, it is possible to bond to a wafer via the pre-storing tin bumps 15. 15 This structure and process can achieve the purpose of electrical connection. However, the surface structure of the conventional package substrate is due to the reflow process (4), which is called the interface between the metal crucible 14 and the pre-solder bump 15 to form an intermetallic compound, and if the electrical connection pad is used. ^Unformed metal pad 14 (4) is directly in contact with the pre-solder bump 15 and electrically connected to the 塾 (10). The interface of the direct pre-solder bump 15 also produces a intermetallic compound. Since the intermetallic compound is a brittle material, the electrode (4) is cracked d' and thus the crack is formed during the test, and the electrical connection between the electrical connection 12, the metal crucible 14 and the pre-solder bump 15 is made. The connection structure is deteriorated, and the pre-recorded tin bumps 15 that have been implanted are also allowed to fall. The stress of the mechanical f is deteriorated, which deteriorates the quality of the joint, and reduces the both of the substrates, because the interface between the metal pad 14 and the pre-solder bump 15 is a plane two contact' When the shape is formed, the money is spread by the interface of the metal pad bump 15 to deteriorate the degree of deterioration of the electrical connection structure. The tendency of the surface line width and the line pitch of the conductor package substrate is shortened. 14 The contact area with the pre-solder bump 15 or the electrical connection 塾12 and the pre-solder bump (10) is also small, and the influence of crack propagation is more significant, so it is necessary to change the geometric axis of the electrical connection structure. Suppresses the reliability of 20 1310589 broadcast 'enhanced substrate electrical connection structure. [Summary of the Invention]
有鑑於此，本發明係提供一種封裝基板表面結構，其 包括：一封裝基板以及複數個蕈狀之金屬柱。在封裝基板 的表面具有複數個電性連接墊及一圖案化之防焊層，=圖 案化之防焊層係顯露出電性連接墊。蕈狀之金屬柱係配置 對應於電性連接墊的表面。 在本發明的封裝基板表面結構上，於蕈狀之金屬柱表 面復可包括一預銲錫凸塊。 本發明的封裝基板表面結構中，蕈狀之金屬柱及預銲 錫凸塊間復可配置有-黏著層。此黏著層使用的材料係可 使用有機材料或金屬材料。有機材料較佳可為為有機保焊 劑（Organic Solderability Preservadves ; 〇sp)，而金屬材料 較佳則可為錫、銀、錄、錄/金及錫/錯等材料所組成之群組 之一者。黏著層主要的功能在於用以接合預銲錫凸塊以及 蕈狀之金屬柱，同時，具有保護以及防止蕈狀之金屬柱氧 化的作用。 在本發明中’蕈狀之金屬柱與電性連接墊之間復可包 20括-導電層（seedlayer)。此導電層係可為銅、錫、錄、絡、 鈦、銅-鉻合金以及錫-鉛合金中所組成之群組之一者，較佳 則可為銅。 在本發明中’蕈狀之金屬柱係可完全填滿或不完全填 滿於封裝基板上所顯露出來之電性連接墊。而蕈狀之金屬 7 '1310589 柱使用的材料係可為銅、錄、鉻、鈦、銅/鉻合金以及錫/ 釓s金所組成之群組之—者，較佳可為銅。 、此外，在本發明中的封裝基板之電性連接墊，其材料 可為銅、錫、鎳、鉻、鈦、銅·絡合金以及錫·錯合金中所組 、群、'且之者，較佳則可為銅。而封裝基板的防焊層係 可為綠漆或黑漆。防焊層主要在用於保護基板的線路之 用又，本發明的封裝基板係可為一雙層或多層的電路板。 依據上述本發明之封裝基板表面結構，例如可由下述 但不限於此之步驟製作。 10 15 20 本發明更提供-種封裝基板表面結構之製作方法，其 2包括.百先，提供—封褒基板，其表面具有複數個電 接塾及-防焊層，此防焊層具有複數個防焊層開口以 :露出電性連料。接著，於此封裝基板表面形成一導電 :阻2此導電層表面形成—阻層，在阻層中可形成複數 «肩口，此等阻層開口係對應於防焊層開口。然後， =層開π及阻層表面形成—具有蕈狀之金屬柱 移除阻層及其所覆蓋之導電層。 面妙發明的製作方法中，復可包括該蕈狀之金屬柱表 r錫λ[刷或電链形成銲錫材料，再經迴焊製程形成一預 ==塊’該預銲錫凸塊係可為锡、錫/船、錫/銀、錫/銅 於了二/鋼所組成之群組之—者。預銲錫凸塊的功能主要在 於可使封裝基板與—晶片連接。 长 在本發明的製作方 形成—黏著層再於狀之㈣柱表面先 考層表面經由迴焊形成預銲錫凸 8 1310589 -、、A。而此黏著層係可以㈣、蒸鐘及無電電鍍(或稱為化學 乂積）之一者形成’較佳係以無電電鍍的方式形成。 4在本毛月的製作方法中，其所使用的導電層係可以濺 、Γ、热鑛及無電钱（或稱為化學沈積）之-者形成，較佳地 5 =以無電電鑛的方式。此導電層主要可作為後述進行電鑛 衣程所需之電流傳導路徑。 在本發明中係可使用乾膜或液態光阻作為阻層。同時 • 目案化此阻層而使阻層形成一阻層開口，其可利用一微影 f術形成’即利用曝光以及顯影的方式形成阻層開口。同 10時，在形成阻層開口時可控制阻層開口的大小，在本發明 中，此等阻層開口係可略等或小於防焊層開口。 ▲在本發明的蕈狀之金屬柱，主要係以電鑛方式形成， 紹土則可利用電鍍的方式形成。而此種蕈狀之金屬柱可刑 成的原因主要在於在形成金屬柱時，此金屬柱超出阻層: 15後’電、流會有等向性（isotr〇Pic)的發展，而產生-類似蕈狀 之金屬柱。 ' 狀 鲁本發明中，此種在表面具有蕈狀之金屬柱的封裝其 板’可改變電性連接塾、金屬柱與預銲錫凸塊所構成之^ 性連接結構的幾何形狀，而在可靠度測試時，既使形成炉 功紋亦可增長裂紋的傳播路徑’而可有效抑制裂紋傳播，強 化基板電性連接結構的可靠度，加強電性連接塾與預料 凸塊間的接合，增加接點之機械強度以及抗疲勞伽 性質。如前所述，當半導體封裝基板表面結構線寬及線距 縮短時，裂紋傳播的影響更加顯著，本發明中可有效抑制 9 1310589 裂紋傳播，因此適用於縮短線寬及線距之封裝基板表面結 構0 【實施方式】 5 以下係藉由特定的具體實施例說明本發明之實施方 式，熟習此技藝之人士可由本說明書所揭示之内容輕易地 了解本發明之其他優點與功效。本發明亦可藉由其他不同 ^ 的具體實施例加以施行或應用，本說明書中的各項細節亦 可基於不同觀點與應用，在不悖離本發明之精神下進行各 10 種修飾與變更。 本發明之實施例中該等圖式均為簡化之示意圖。惟該 2圖示僅顯示與本發明有關之元件，其所顯示之元件非為 實際實施時之態樣’其實際實施時之元件數目、形狀等比 例為一選擇性之設計，且其元件佈局型態可能更複雜。 15 實施例1 明參考圖2A至2F，係為本實施例之封裝基板表面結構 製作流程剖視圖。 百先，如圖2A所示，係提供一封裝基板21，此封裝基 板21表面具有複數個電性連接墊22及一防焊層，此防焊 2〇層23具有複數個防焊層開口 23a以顯露出電性連接墊22。其 中電性連接墊22可為一銅墊，防焊層23係可為一綠漆。 而防焊層Μ 口 23a係經由曝光以及顯影的方式形成。 接者，如圖2B所示，於圖2A中的A區域放大來看，其餘 防知層開口 23a的電性連接墊22表&的結構皆與其相同。於 1310589 2基板21表㈣成—導電層24。此導電層24可使用的材 料為銅、錫、鎖、枚 "'13 、太' 銅-鉻·合金以及錫-錯合金中所έ且 成之群組之一者，，士 6 社本貫施例中則使用銅，並且以無電電 二勺方式φ成。⑦成導電層24之後再於其表面形成一阻層 4阻層25的㈣係可為乾膜或液態錄以曝光及顯^ =方式形成阻層開Π 2 5 a，此阻層開σ 2 5 a的大小約等於防 綷層開口 23a。 _ J後如圖2C所不，於阻層開口…及阻層25的表面藉 由電鍍的方式形成一具有蕈狀之金屬柱施。此蕈狀之金』 主26a使用的材料係可為钢、鎳、鉻、鈦銅/鉻合金以及錫 /船合金所組成之群組之一者，在本實施例中則使用銅。 再如圖2D所示，移除阻層25及其所覆蓋之導電層心 而得到本發明之一封裝基板的表面結構。 接著，如圖2E所示，於此蕈狀之金屬柱旅表面利用幾 15鑛、蒸鑛及無電電鑛之-者形成—黏著層27,在本實施例 巾則使用無電電㈣方式形成。而黏著層27的材料可為有 機保焊劑、錫、銀、鎳、錦/金及錫/錯等材料所組成之群组 之一者，本實施例則使用有機保焊劑。 最後，再於此黏著層27表面於具有此種蕈狀之金屬柱 26a的電性連接墊22上經由印刷及迴烊製程形成一預鲜錫 凸塊28a，此外，亦可於先前圖2〇所述之製程完成後，於蕈 狀之金屬柱26a繼續電鍍形成銲錫材料（圖未示），再移除阻 層25及其覆蓋之導電層24，再以迴蟬製程形成一預鲜錫凸 塊28a ’該預銲錫凸塊28a係可為錫、錫/鉛、錫/銀、錫/鋼 Ι31Ό589 及錫/銀/鋼所組成之群組之—者，而完成一封裝基板表面結 構及及其製作方法。封裝基板表面結構的功能主要在於可 使封裝基板與一晶片連接，前述黏著層及預銲錫凸塊則可 依製程需要，選擇性地形成於封裝基板表面。In view of the above, the present invention provides a package substrate surface structure comprising: a package substrate and a plurality of braided metal posts. A plurality of electrical connection pads and a patterned solder mask are formed on the surface of the package substrate, and the patterned solder resist layer exposes the electrical connection pads. The braided metal column configuration corresponds to the surface of the electrical connection pad. In the surface structure of the package substrate of the present invention, a pre-solder bump may be included on the surface of the metal post of the braid. In the surface structure of the package substrate of the present invention, an adhesive layer may be disposed between the domed metal pillars and the pre-soldered tin bumps. The material used for this adhesive layer can be an organic material or a metal material. The organic material may preferably be an organic solder retainer (Organic Solderability Preservadves; 〇sp), and the metal material may preferably be one of a group consisting of tin, silver, recording, gold/tin and tin. The primary function of the adhesive layer is to bond pre-solder bumps and braided metal posts while protecting and preventing the oxidation of the braided metal pillars. In the present invention, a "single layer" may be included between the metal pillars of the braided shape and the electrical connection pads. The conductive layer may be one of a group consisting of copper, tin, magnet, titanium, copper-chromium alloy and tin-lead alloy, preferably copper. In the present invention, the "ruthless metal pillars" may completely fill or not completely fill the electrical connection pads exposed on the package substrate. The material of the braided metal 7 '1310589 column may be a group consisting of copper, chrome, chromium, titanium, copper/chromium alloy and tin/bis gold, preferably copper. In addition, the electrical connection pads of the package substrate in the present invention may be made of copper, tin, nickel, chromium, titanium, copper alloy, and tin/stall alloy. Preferably, it can be copper. The solder mask of the package substrate can be green or black lacquer. The solder resist layer is mainly used for the circuit for protecting the substrate. Further, the package substrate of the present invention may be a two-layer or multi-layer circuit board. The surface structure of the package substrate according to the present invention described above can be produced, for example, by the following steps, but not limited thereto. 10 15 20 The present invention further provides a method for fabricating a surface structure of a package substrate, wherein the method comprises the following steps: providing a sealing substrate having a plurality of electrical interfaces and a solder mask layer on the surface thereof, the solder resist layer having a plurality of layers The solder mask is opened to expose the electrical material. Then, a conductive layer is formed on the surface of the package substrate: a resist layer is formed on the surface of the conductive layer, and a plurality of “shoulders” are formed in the resist layer, and the resist layer openings correspond to the solder resist opening. Then, the layer is opened π and the surface of the resist layer is formed - a metal pillar having a meandering shape to remove the resist layer and the conductive layer covered thereby. In the manufacturing method of the invention, the composite may include the metal column of the crucible, r tin λ [brush or electric chain forming a solder material, and then forming a pre-= block by a reflow process]. The pre-solder bump may be Tin, tin/ship, tin/silver, tin/copper are in the group of two/steel. The function of the pre-solder bumps is mainly to connect the package substrate to the wafer. In the fabrication of the present invention, the adhesive layer is formed on the surface of the (4) column surface to form a pre-solder bump 8 1310589 -, A by reflow. The adhesive layer can be formed by electroless plating (4), steaming, and electroless plating (or chemical enthalpy). 4 In the production method of this month, the conductive layer used can be formed by splashing, sputum, hot minerals and no electricity (or chemical deposition), preferably 5 = in the form of electroless ore. . This conductive layer can be mainly used as a current conduction path required for the electric ore course to be described later. In the present invention, a dry film or a liquid photoresist can be used as the resist layer. At the same time, the resist layer is formed to form a resistive opening, which can be formed by a lithography, that is, the resist opening is formed by exposure and development. At the same time as 10, the size of the opening of the resist layer can be controlled when forming the opening of the resist layer. In the present invention, the opening of the resist layer can be slightly equal or smaller than the opening of the solder resist layer. ▲ In the present invention, the metal pillars are formed mainly by electric ore, and the soil can be formed by electroplating. The reason why such a braided metal column can be severed is that when the metal column is formed, the metal column exceeds the resist layer: after 15, the electric and the flow will have an isotropic (isotr〇Pic) development, and A metal column resembling a braid. In the invention, the package of the metal plate having a meandering shape on the surface can change the geometry of the connecting structure formed by the electrical connection 金属, the metal post and the pre-solder bump, and is reliable. In the degree test, even if the furnace work pattern is formed, the propagation path of the crack can be increased, the crack propagation can be effectively suppressed, the reliability of the electrical connection structure of the substrate can be strengthened, the joint between the electrical connection and the expected bump can be strengthened, and the connection can be increased. The mechanical strength of the point and the anti-fatigue gamma property. As described above, when the line width and the line pitch of the surface of the semiconductor package substrate are shortened, the influence of the crack propagation is more remarkable. In the present invention, the crack propagation of 9 1310589 can be effectively suppressed, so that the surface of the package substrate is shortened for the line width and the line pitch. Structure 0 [Embodiment] The following describes the embodiments of the present invention by way of specific embodiments, and those skilled in the art can easily understand other advantages and effects of the present invention from the disclosure of the present specification. The present invention may be embodied or applied in various other specific embodiments, and various modifications and changes can be made without departing from the spirit and scope of the invention. The drawings in the embodiments of the present invention are simplified schematic diagrams. However, the 2 diagrams only show the components related to the present invention, and the components shown therein are not in actual implementation. The actual number of components in the actual implementation is a selective design and the component layout. The pattern may be more complicated. 15 Embodiment 1 Referring to Figs. 2A to 2F, a cross-sectional view showing a process of fabricating a surface structure of a package substrate of the present embodiment. As shown in FIG. 2A, a package substrate 21 is provided. The surface of the package substrate 21 has a plurality of electrical connection pads 22 and a solder mask. The solder resist layer 23 has a plurality of solder mask openings 23a. To expose the electrical connection pads 22. The electrical connection pad 22 can be a copper pad, and the solder resist layer 23 can be a green lacquer. The solder resist layer opening 23a is formed by exposure and development. As shown in Fig. 2B, in the enlarged view of the area A in Fig. 2A, the structures of the electrical connection pads 22 of the remaining prevention layer openings 23a are the same. On the 1310589 2 substrate 21 table (four) into a conductive layer 24. The material that can be used for the conductive layer 24 is one of a group of copper, tin, lock, a "'13, a too copper-chromium alloy, and a tin-alloy alloy, and a group of 6 Copper is used in the examples, and is formed in the form of two spoons without electricity. After the conductive layer 24 is formed, a resist layer 4 is formed on the surface thereof, and the (4) layer of the resist layer 4 can be formed into a dry film or a liquid film to form a resist layer opening 25 5 a. The resist layer is opened σ 2 The size of 5 a is approximately equal to the anti-mite layer opening 23a. After _J, as shown in Fig. 2C, the surface of the resist layer and the surface of the resist layer 25 are formed by electroplating to form a metal pillar having a meandering shape. The material used for the main 26a may be one of a group consisting of steel, nickel, chromium, titanium copper/chromium alloy, and tin/ship alloy. In the present embodiment, copper is used. Further, as shown in Fig. 2D, the resist layer 25 and the conductive layer core it covers are removed to obtain the surface structure of a package substrate of the present invention. Next, as shown in Fig. 2E, the surface of the metal pillar of the braided shape is formed by using a few ore, a steamed ore and an electroless ore-free adhesion layer 27, and in this embodiment, an electric-free (four) method is used. The material of the adhesive layer 27 may be one of a group consisting of machine flux, tin, silver, nickel, brocade/tin and tin/error. In this embodiment, an organic solder resist is used. Finally, a pre-tin solder bump 28a is formed on the surface of the adhesive layer 27 on the electrical connection pad 22 having the metal post 26a having such a meander shape via a printing and returning process, and may also be in the previous FIG. After the process is completed, the solder material (not shown) is further electroplated on the metal pillar 26a, and the resist layer 25 and the conductive layer 24 covered thereon are removed, and a pre-precision tin bump is formed by the return process. Block 28a' the pre-solder bump 28a can be a group of tin, tin/lead, tin/silver, tin/steel Ι31Ό589, and tin/silver/steel, and complete the surface structure of a package substrate and Its production method. The function of the surface structure of the package substrate is mainly to connect the package substrate to a wafer, and the adhesive layer and the pre-solder bump can be selectively formed on the surface of the package substrate according to the process requirements.
5 因此，本實施例可提供一封裝基板表面結構。如圖2D 所示係包括了一封裝基板21，其表面具有電性連接塾22 及圖案化之防焊層23，此圖案化之防焊層23係具有複數 個開口顯露出電性連接墊22。此外，在對應於電性連接墊 22的表面係配置有蕈狀之金屬柱26a。其中，此種蕈狀之金 10 屬柱係完全填滿於電性連接墊22的表面。 實施例2 ,請參考圖3A至3E，係為本實施例之封裝基板表面結構 製作流程剖視圖。其中，本實施例使用的材料以及形成的 方式與實施例1大致相同。並且提供如實施例中圖2 A的一封 15 裝基板21。接下來的製程則與實施例一不相同。 首先，如圖3A所示，如實施例丨相同，於封裝基板21表 面形成一導電層24，並且於此導電層24表面形成一阻層 25，此時，阻層25係使用液態光阻。再於此阻層25係形成 阻層開口 25b。然而’此阻層開口 25b的大小則小於防焊 20 層開口。 接著，如圖3B所示’於此阻層開口 25b及阻層25的表面 形成一簟狀之金屬柱26b。再如圖3C所示，移除阻層25及其 覆蓋之導電層24。 然後，如圖3D所示，於此種蕈狀之金屬柱2615表面形成 12 1310589 一黏著層27 ^最後，如圖3E所示，依製程需要，於具有此 種簟狀之金屬柱26b的電性連接塾22上經由印刷及迴焊製 程形成一預銲錫凸塊28b，此外，亦可於先前圖3B所述之製 程完成後，於簟狀之金屬柱26b繼續電鍍形成銲錫材料（圖 5 未示）’再移除阻層25及其覆蓋之導電層24 ’再以迴焊製程 形成一預銲錫凸塊28b，該預銲錫凸塊281)係可為錫、錫/ 錯、錫/銀、錫/銅及錫/銀/銅所組成之群組之一者，而完成 一封裝基板表面結構及及其製作方法。封裝基板表面結構 1 的功能主要在於可使封裝基板與一晶片連接，前述黏著層 10及預銲錫凸塊則可依製程需要，選擇性地形成於封裝基板 表面。 本貫施例的結構與實施例1大致上相同，但不同的是， 如圖3C所示，此種蕈狀之金屬柱26b係不完全填滿於電性連 接塾22的表面。 15 本發明所揭示在表面上具有蕈狀之金屬柱之封裝基板 的結構及製程，可有效抑制裂紋傳播，加強接點的機械強 • 度，使得接點的品質變佳，而增加了基板的可靠度。特別 是，當半導體封裝基板表面結構線寬及線距縮短時，裂紋 傳播的影響更加顯著，本發明中可有效抑制裂紋傳播，因 20 此適用於縮短線寬及線距之封裝基板表面結構。 上述實施例僅係為了方便說明而舉例而已，本發明所 主張之權利範圍自應以申請專利範圍所述為準，而非僅限 於上述實施例。 13 '1310589 【圖式簡單說明】 圖1A至1⑽習知之封裝基板表面結構剖視圖。 =2A至戰本發明—較佳實_之封裝 製作流程剖視圖。 構 圖3A至_本發明另—較佳實施例之封裝基板表面結 構製作流程剖視圖。 % 【主要元件符號說明】 12,22 14 23a 25 26a,26b 28a,28b 電性連接塾 金屬塾 防焊層開口 阻層 蕈狀之金屬柱 預銲錫凸塊 U’21封褒基板 13,23 防焊層 15 從h 預銲锡凸塊 24 ^ 導電層 25a，25b 阻層_ 黏著層5 Therefore, this embodiment can provide a package substrate surface structure. As shown in FIG. 2D, a package substrate 21 having an electrical connection port 22 and a patterned solder resist layer 23 having a plurality of openings to expose the electrical connection pads 22 is provided. . Further, a metal pillar 26a having a meandering shape is disposed on the surface corresponding to the electrical connection pad 22. Among them, the skeleton of the gold-like 10 is completely filled on the surface of the electrical connection pad 22. Embodiment 2, please refer to Figs. 3A to 3E, which are cross-sectional views showing the process of fabricating the surface structure of the package substrate of the present embodiment. Here, the materials used in the present embodiment and the manner of formation are substantially the same as those in the first embodiment. And a 15 substrate 17 as shown in Fig. 2A in the embodiment is provided. The next process is different from the first embodiment. First, as shown in FIG. 3A, as in the embodiment, a conductive layer 24 is formed on the surface of the package substrate 21, and a resist layer 25 is formed on the surface of the conductive layer 24. At this time, the resist layer 25 uses a liquid photoresist. Further, the resist layer 25 is formed with a resist opening 25b. However, the size of the resist opening 25b is smaller than that of the solder resist 20 layer. Next, as shown in Fig. 3B, a metal pillar 26b having a meander shape is formed on the surface of the resist layer opening 25b and the resist layer 25. As further shown in Figure 3C, the resist layer 25 and its conductive layer 24 are removed. Then, as shown in FIG. 3D, 12 1310589 an adhesive layer 27 is formed on the surface of the braided metal pillar 2615. Finally, as shown in FIG. 3E, according to the process, the electricity of the metal pillar 26b having such a braid is formed. A pre-solder bump 28b is formed on the bonding port 22 via a printing and reflow process. Further, after the process described in FIG. 3B is completed, the soldering material is further formed on the metal post 26b of the braided shape (FIG. 5 And then removing the resist layer 25 and the conductive layer 24' it covers, and forming a pre-solder bump 28b by a reflow process, the pre-solder bump 281) being tin, tin/wrong, tin/silver, One of the groups consisting of tin/copper and tin/silver/copper completes the surface structure of a package substrate and a method of fabricating the same. The function of the surface structure 1 of the package substrate is mainly to connect the package substrate to a wafer, and the adhesive layer 10 and the pre-solder bumps can be selectively formed on the surface of the package substrate according to the process requirements. The structure of the present embodiment is substantially the same as that of the first embodiment, but the difference is that, as shown in Fig. 3C, the beak-shaped metal post 26b is not completely filled on the surface of the electrical connecting port 22. The structure and process of the package substrate with the metal pillars on the surface of the invention are disclosed, which can effectively suppress crack propagation, strengthen the mechanical strength of the joint, and improve the quality of the joint, thereby increasing the substrate. Reliability. In particular, when the line width and the line pitch of the surface of the semiconductor package substrate are shortened, the influence of crack propagation is more remarkable, and the crack propagation can be effectively suppressed in the present invention, which is suitable for shortening the surface structure of the package substrate with line width and line pitch. The above-described embodiments are merely examples for the convenience of the description, and the scope of the claims is intended to be limited by the scope of the claims. 13 '1310589 BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A to FIG. 1(10) are cross-sectional views showing the surface structure of a package substrate. = 2A to the invention of the invention - better _ package production process cross-sectional view. 3A to 3D are cross-sectional views showing a process of fabricating a surface structure of a package substrate according to another preferred embodiment of the present invention. % [Main component symbol description] 12,22 14 23a 25 26a,26b 28a,28b Electrical connection 塾metal 塾 solder mask open resistance layer 金属-shaped metal pillar pre-solder bump U'21 sealing substrate 13,23 Solder layer 15 from h pre-solder bump 24 ^ conductive layer 25a, 25b resist layer _ adhesive layer