TWI783235B - Circuit board structures and methods of forming the same - Google Patents

Abstract

A method of fabricating a circuit board structure is provided. The method includes: providing a substrate; forming a contact pad on the substrate; forming a solder resist layer overlying the substrate and the contact pad; patterning the solder resist layer to form a first opening exposing a portion of the contact pad; forming a nickel layer on the portion of the contact pad exposed by the first opening; forming a copper layer overlying the patterned solder resist layer and the nickel layer; forming a mask layer overlying the copper layer; patterning the mask layer to form a second opening above the contact pad and exposing a portion of the copper layer; forming a tin layer on the portion of the copper layer exposed by the second opening; removing the patterned mask layer and the copper layer on the upper surface of the patterned solder resist layer; and reflowing the tin layer and the remaining copper layer into a bump, wherein the bump does not cover the upper surface of the patterned solder resist layer.

Description

Circuit board structure and method of forming the same

The invention relates to a circuit board structure, in particular to a circuit board structure with bumps and a forming method thereof.

The circuit board is the base for electronic components such as active and passive components. It has a wide range of applications, including: motherboards for desktop and notebook computers, home appliances, smart phones, handheld game consoles, automotive electronics, etc. . In line with the design of electronic products that are thin, light, multi-functional, and emphasizing low power consumption, in order to meet these requirements, the volume of the chip needs to be shrunk and the number of I/Os needs to be more, which means that the circuit board needs to be reduced to a micro-bump pitch ( bump pitch) development.

In the aforementioned development, the circuit board has entered the production technology of tin bump pitch less than 100μm, and the traditional solder paste printing and micro-ball printing technology has been replaced by plating tin technology. However, limited by the alignment technology in the manufacturing process, the electroplated tin bumps have a shoulder structure, which increases the possibility of solder bridges during packaging, increases the risk of short circuits, and also limits the pitch of tin bumps miniaturization development.

An embodiment of the present invention provides a method for forming a circuit board structure, including: providing a substrate; forming a contact pad on the substrate; forming a solder resist layer covering the substrate and the contact pad; patterning the solder resist layer to forming a first opening, which exposes a part of the contact pad; forming a nickel layer on the part of the contact pad exposed by the first opening; forming a copper layer, covering the patterned solder resist layer and The nickel layer; forming a mask layer to cover the copper layer; patterning the mask layer to form a second opening, the second opening is located above the contact pad and exposes a part of the copper layer; forming a tin layer on the portion of the copper layer exposed by the second opening; removing the patterned mask layer and the copper layer on the upper surface of the patterned solder resist layer; and performing a reflow process to the The tin layer and the remaining copper layer form a bump, and the bump does not cover the upper surface of the patterned solder resist layer.

An embodiment of the present invention provides a circuit board structure, including: a base and a contact pad located on the base; a patterned solder mask covering the base and having an opening, the opening exposes a part of the contact pad; a nickel layer on the portion of the contact pad exposed by the opening; and a bump on the nickel layer, the bump not covering the upper surface of the patterned solder resist layer.

The following disclosure provides a number of embodiments, or examples, for implementing different elements of the provided subject matter. Specific examples of each component and its configuration are described below to simplify the description of the embodiments of the present invention. Of course, these are just examples, not intended to limit the embodiments of the present invention. For example, if a description mentions that a first element is formed on a second element, it may include an embodiment in which the first and second elements are in direct contact, or may include an additional element formed between the first and second elements , so that they are not in direct contact with the example. In addition, the embodiments of the present invention may repeat reference numerals and/or letters in various examples. This repetition is for the sake of brevity and clarity and not to show the relationship between the different embodiments and/or configurations discussed.

Furthermore, terms relative to space may be used, such as "below", "below", "lower", "above", "higher", etc., for the convenience of description The relationship between one component or feature(s) and another component(s) or feature(s) in a drawing. Spatially relative terms are intended to encompass different orientations of the device in use or operation, as well as orientations depicted in the drawings. When the device is turned to a different orientation (rotated 90 degrees or otherwise), the spatially relative adjectives used therein shall also be interpreted in accordance with the turned orientation.

The term "about" is used herein to indicate that a given quantity may vary based on the particular technology node associated with the target board configuration. In some embodiments, based on a specific technology node, the term "about" can mean that a given quantity is in the range of, for example, 10% to 30% of the value (for example: ±10%, ±20%, or ± 30%).

According to some embodiments of the present invention, a method for forming a circuit board structure is provided, and the bumps in the formed circuit board structure will not have a shoulder structure after a reflow process. According to some embodiments of the present invention, a circuit board structure without a shoulder structure is provided, which can reduce the risk of short circuit and further reduce the bump pitch.

FIG. 1 illustrates initial steps of a method for forming a circuit board structure according to some embodiments of the present invention. Firstly, a substrate 100 is provided. In some embodiments, the substrate 100 may include: paper phenolic resin, composite epoxy, polyimide resin, glass fiber, other suitable insulating materials The material, or a combination of the foregoing, has a thickness of about 20 μm to about 3000 μm. Next, contact pads 102 are formed on the substrate 100 . In some embodiments, the contact pad 102 may include: copper, tungsten, silver, tin, nickel, cobalt, chromium, titanium, lead, gold, bismuth, antimony, zinc, zirconium, magnesium, indium, tellurium, gallium, other suitable The metal material, the aforementioned alloy, or the aforementioned combination, and its thickness may be about 5 μm to about 50 μm, such as 10 μm to 30 μm. The contact pads 102 can be formed on the substrate 100 by suitable methods, such as sputtering, lamination, coating, other suitable methods, or a combination of the foregoing.

Referring to FIG. 2 , a solder resist layer 104 is formed to cover the substrate 100 and the contact pads 102 . In some embodiments, the solder resist layer 104 can be a photosensitive material (such as an ultraviolet photosensitive material), a heat sensitive material (such as a thermosetting heat sensitive material), other suitable materials, or a combination thereof. For example, the solder resist layer 104 can be epoxy resin, urethane resin, ethyl resin, or similar materials. The solder resist layer 104 can be formed by coating or dry film lamination.

Then the solder resist layer 104 is subjected to _a patterning process to form a patterned solder resist layer 104A as shown in FIG. For example, 10 μm to 50 μm, and the opening 106 exposes part of the contact pad 102 . In some embodiments, the process steps of patterning the solder resist layer 104 may sequentially include: using a photomask to expose the solder resist layer 104, and then developing the exposed solder resist layer 104 to form a patterned solder resist layer. layer 104, and then bake the solder resist layer 104 to cure the solder resist layer 104.

Then referring to FIG. 4 , a nickel layer 108 is formed on the part of the contact pad 102 exposed by the opening 106 . The width W _Ni of the nickel layer 108 may be about 5 μm to about 60 μm, for example, 10 μm to 50 μm. For example, the nickel layer 108 can be formed by physical vapor deposition (such as sputtering), chemical vapor deposition, electroplating, coating, electroless plating, other suitable methods, or a combination thereof. In some embodiments, the nickel layer 108 can be used as a buffer layer between the contact pad 102 below it and the components to be formed on it later, so as to avoid voids. In a specific embodiment, the nickel layer 108 can be selectively formed on the portion of the contact pad 102 exposed by the opening 106 through an electroless plating technique. In some embodiments where the nickel layer 108 is formed by an electroless plating technique, the thickness of the nickel layer 108 is about 1 μm to about 10 μm, such as 3 μm to 6 μm. In some embodiments, the upper surface of the nickel layer 108 is lower than the upper surface of the patterned solder resist layer 104A.

Referring to FIG. 5 , a copper layer 110 is formed covering the patterned solder mask layer 104A and the nickel layer 108 . In some embodiments, the forming method of the copper layer 110 includes: physical vapor deposition (such as sputtering), chemical vapor deposition, electroplating, coating, electroless plating, other suitable methods, or a combination thereof. In a specific embodiment, the copper layer 110 is formed by electroless plating. In some embodiments where the copper layer 110 is formed by an electroless plating technique, the thickness of the copper layer 110 is about 0.1 μm to about 3 μm, for example, 0.5 μm to 1 μm.

Referring to FIG. 6 , a mask layer 112 is formed to cover the copper layer 110 . The material of the mask layer 112 may include: dry film, liquid photoresist, other appropriate materials, or a combination thereof, and may be formed by printing, spin coating, lamination, other appropriate methods, or a combination thereof.

Then the mask layer 112 is patterned to form a patterned mask layer _112A as shown in FIG. 90 μm, such as 20 μm to 80 μm, and the opening 114 is located above the contact pad 102 and exposes part of the copper layer 110 . In some embodiments, the process steps of patterning the mask layer 112 are similar to the process of patterning the solder resist layer 104 described above, and will not be repeated here. The material of the mask layer 112 in the embodiment of the present invention is different from the mask material layer used in the process of patterning it. In a specific embodiment, the mask layer 112 is a dry film, and the mask layer 112 can be exposed directly, and then the exposed mask layer 112 can be developed to be patterned. In some embodiments, the width W ₂ of the opening 114 of the patterned mask layer 112A is greater than the width W ₁ of the opening 106 of the patterned solder resist layer 104A, as shown in FIG. 7 .

Referring to FIG. 8 , a tin layer 116 is formed on the portion of the copper layer 110 exposed by the opening 114 . In some embodiments, the formation method of the tin layer 116 may include: physical vapor deposition (such as sputtering), chemical vapor deposition, electroplating, coating, electroless plating, or a combination thereof. In a particular embodiment, the tin layer 116 is formed by electroplating. For example, the copper layer 110 can be used as a seed layer to perform an electroplating process to form the tin layer 116 on the portion of the copper layer 110 exposed by the opening 114 .

Then remove the copper layer 110 on the upper surface of the patterned mask layer 112A and the patterned solder resist layer 104A, as shown in FIG. 9 . In some embodiments, two wet etching processes are used to remove the copper layer 110 on the upper surfaces of the patterned mask layer 112A and the patterned solder resist layer 104A, respectively. In an embodiment where the patterned mask layer 112A is removed using a wet etching process, an appropriate etchant may be used to remove the patterned mask layer 112A, such as sodium hydroxide solution, potassium hydroxide solution, amine solution, or other suitable solutions. In an embodiment where a wet etching process is used to remove the copper layer 110 on the upper surface of the patterned solder resist layer 104A, an appropriate etchant may be used to remove the copper layer 110 on the upper surface of the patterned solder resist layer 104A, For example: sulfuric acid-hydrogen peroxide solution, sodium chlorate solution, or other suitable solutions. According to some embodiments of the present invention, removing the copper layer 110 on the upper surface of the patterned solder resist layer 104A includes removing the copper layer 110 between the tin layer 116 and the upper surface of the patterned solder resist layer 104A, so that the patterned solder resist layer 104A Solder layer 104A has no copper on its upper surface. In some embodiments, the patterned mask layer 112A can be removed by a dry etching process (eg reactive ion etching (RIE)), other suitable etching and/or stripping processes. In other embodiments, after removing the patterned mask layer 112A, a quick etching process with high etch selectivity to the copper layer 110 may be performed to remove the copper on the upper surface of the patterned solder resist layer 104A. Layer 110 is removed. In some embodiments, after removing the copper layer 110 on the upper surface of the patterned solder resist layer 104A, the bottom width of the remaining copper layer 110 is not greater than the width W ₁ of the opening 106 .

Referring to FIG. 10 , a reflow process is performed under proper conditions (for example, at a temperature of about 210° C. to about 280° C. for about 400 seconds) to form the tin layer 116 and the remaining copper layer 110 into bumps 118 . During the reflow process, the tin layer 116 interpenetrates with the remaining copper layer 110 at the interface to form a tin-copper alloy structure, thereby forming the bump 118 . Since there is no copper on the upper surface of the patterned solder resist layer 104A, the tin-copper alloy structure in the reflow process is only formed on the nickel layer 108, so as shown in FIG. 10, the formed bump 118 does not cover the patterned The upper surface of the solder resist layer 104A, that is, the bump 118 does not have a shoulder structure. In some embodiments, the thickness of the bump 118 is about 10 μm to about 70 μm, such as 15 μm to 55 μm. According to some embodiments of the present invention, the bump 118 is substantially composed of tin and copper, that is, tin and copper account for more than 99 wt% of the bump 118, wherein the proportion of tin is about 95wt% to about 99.5wt% and copper The proportion is about 0.05wt% to about 4wt%. For example, the proportion of tin is 97wt% to 99wt% and the proportion of copper is 0.5wt% to 2wt%. In some embodiments, the maximum width W _b of the bump 118 is not greater than the width W _Ni of the nickel layer 108 . Compared with the prior art in which the bump has a shoulder structure in the circuit board structure, the horizontal position of the maximum width W _b of the bump 118 in the embodiment of the present invention is not higher than the upper surface of the patterned solder resist layer 104A. Except that the protrusion 118 does not have a shoulder structure, in other embodiments of the present invention, the maximum width W _b of the protrusion 118 is not greater than the width W ₁ of the opening 106 . In some embodiments, the thickness ratio of the bump 118 to the nickel layer 108 is about 10 to about 20.

According to some embodiments of the present invention, the bumps in the formed circuit board structure do not have a shoulder structure due to the limitation of alignment technology, which can improve the short circuit problem of adjacent bumps during packaging, increase product yield, and The distance between adjacent bumps can be further reduced, and the miniaturization of the pitch between bumps can be realized. For example, without the shoulder structure of about 20 μm to about 30 μm, the distance between adjacent bumps in the circuit board structure can be further developed below 70 μm.

It should be noted that, for the purpose of simplicity and clarity, the embodiment of the present invention only shows a part of the structure of the circuit board as a schematic diagram. However, those skilled in the art to which the present invention pertains should understand that some of the circuit board structures shown in the embodiments of the present invention may include other similar or identical structures and/or components, or The upper or lower layers of some circuit board structures shown may also include other similar or identical structures and/or components. For example, the aforementioned other components include: metal wires, metal layers, solder mask layers, bumps, or combinations thereof, and the aforementioned other structures include structures formed by the aforementioned components.

The features of several embodiments are summarized above, so that those skilled in the art of the present invention can better understand various aspects of the present invention. Those who have ordinary knowledge in the technical field of the present invention should understand that they can easily use the present invention as a basis to design or modify other processes and structures to achieve the same purpose and/or advantages as the embodiments described herein . Those with ordinary knowledge in the technical field of the present invention should also understand that such equivalent structures do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and substitutions can be made here without departing from the present invention. spirit and scope.

100: substrate 102: contact pad 104: solder resist layer 104A: patterned solder resist layer 106: opening 108: nickel layer 110: copper layer 112: mask layer 112A: patterned mask layer 114: opening 116: tin layer 118 : bump W ₁ : width W ₂ of opening 106 : width W _b of opening 114 : maximum width W of bump _Ni : width of nickel layer 108

Embodiments of the present invention are best understood from the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily expanded or reduced to clearly illustrate the features of the embodiments of the invention. FIG. 1 is a schematic cross-sectional view illustrating a circuit board structure according to some embodiments of the present invention. 2-9 are schematic cross-sectional views illustrating various intermediate stages of forming a circuit board structure according to some embodiments of the present invention. FIG. 10 is a schematic cross-sectional view illustrating a circuit board structure according to some embodiments of the present invention.

100: base

102: Contact pad

104A: Patterned solder mask

108: nickel layer

110: copper layer

118: Bump

W _b : The maximum width of the bump

Claims (20)

A method for forming a circuit board structure, comprising: providing a substrate; forming a contact pad on the substrate; forming a solder resist layer covering the substrate and the contact pad; patterning the solder resist layer to form a first opening , the first opening exposes a part of the contact pad; forming a nickel layer on the part of the contact pad exposed by the first opening; forming a copper layer covering the patterned solder resist layer and the nickel layer; forming a mask layer covering the copper layer; patterning the mask layer to form a second opening, the second opening is located above the contact pad and exposes a part of the copper layer; forming a tin layer on the second opening On the portion of the exposed copper layer; remove the patterned mask layer and the copper layer on the upper surface of the patterned solder mask layer to form a notch in the tin layer and the patterned mask layer between the soldering layers; and performing a reflow process to form the tin layer and the remaining copper layer into a bump, the projected area of the bump on the base is not larger than the projected area of the nickel layer on the base. The method for forming a circuit board structure according to claim 1, wherein the nickel layer is formed by electroless plating. The method for forming a circuit board structure according to claim 2, wherein the upper surface of the nickel layer is lower than the upper surface of the patterned solder resist layer. The method for forming a circuit board structure according to claim 1, wherein the copper layer is formed by electroless plating. The method for forming a circuit board structure according to claim 4, wherein the copper layer is a seed layer used for forming the tin layer. The method for forming a circuit board structure according to claim 1, wherein the second opening is larger than the first opening. The method for forming a circuit board structure according to claim 1, wherein the tin layer is formed by electroplating. The method for forming a circuit board structure as claimed in claim 1, wherein removing the patterned mask layer and the copper layer on the upper surface of the patterned solder resist layer uses two wet etching processes, respectively removing the The patterned mask layer and the copper layer on the upper surface of the patterned solder resist layer. The method for forming a circuit board structure according to claim 1, wherein removing the copper layer on the upper surface of the patterned solder resist layer comprises removing the copper between the tin layer and the upper surface of the patterned solder resist layer Floor. The method for forming a circuit board structure according to claim 1, wherein after removing the copper layer on the upper surface of the patterned solder mask layer, the width of the bottom of the remaining copper layer is not greater than the width of the first opening. The method for forming a circuit board structure according to claim 1, wherein the maximum width of the bump is not greater than the width of the nickel layer. The method for forming a circuit board structure according to claim 1, wherein the horizontal position of the maximum width of the bump is not higher than the upper surface of the patterned solder resist layer. The method for forming a circuit board structure according to claim 1, wherein the maximum width of the bump is not greater than the width of the first opening. A circuit board structure, comprising: a base and a contact pad located on the base; a patterned solder mask covering the substrate and having an opening exposing a portion of the contact pad; a nickel layer on the portion of the contact pad exposed by the opening; and a bump formed by reflow Formed and located on the nickel layer, the projected area of the bump on the substrate is no larger than the projected area of the nickel layer on the substrate. The circuit board structure according to claim 14, wherein the upper surface of the nickel layer is lower than the upper surface of the patterned solder resist layer. The circuit board structure according to claim 14, wherein the maximum width of the bump is not greater than the width of the nickel layer. The circuit board structure according to claim 14, wherein the horizontal position of the maximum width of the bump is not higher than the upper surface of the patterned solder resist layer. The circuit board structure according to claim 14, wherein the maximum width of the bump is not greater than the width of the opening. The circuit board structure according to claim 14, wherein the thickness ratio of the bump to the nickel layer is 10-20. The circuit board structure according to claim 14, wherein the material of the bump is substantially composed of tin and copper.

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