JP7301919B2 - Circuit board with constrained solder interconnect pads - Google Patents

Description

The present invention relates generally to semiconductor processing, and more particularly to a circuit board with solder interconnect pads and method of manufacture thereof.

Various conventional organic semiconductor chip package substrates are electrically connected to flip-chip mounted semiconductor chips via a plurality of solder bumps. In some conventional designs, solder bumps or portions thereof are placed in holes formed in the solder mask, the outermost layer of the circuit board. This hole is intended to be vertically aligned with the underlying bump pad. In conventional designs, the bump pads are manufactured with lateral dimensions larger than the solder mask holes. This creates an interface between the solder mask and the top surface of the bump pad.

Conventional solder interconnect pads are typically formed on underlying vias. At these locations, the solder mask can experience bending moments. This bending moment can cause delamination of the solder mask on the top surface of the bump pad. This delamination can create paths that can cause solder to migrate laterally from overlying bumps and short to adjacent conductor structures such as traces or other bump pads.

There is a continuing trend of packing more and more wiring paths into circuit boards, particularly semiconductor chip package substrates. Among other things, the need for greater wiring path complexity is driven by the increasing number of inputs and outputs in more complex semiconductor die designs. Inserting more traces and vias into a circuit board layout is not an easy task. Indeed, the goal of increasing wiring paths must compete with design rules to ensure that the manufacturing processes used to form circuit boards can do so.

However, conventional techniques to address the potential for solder mask delamination often use enlarged bump pads or design rules that require wider conductor spacing, both of which reduce package density. work against increasing .

SUMMARY OF THE INVENTION The present invention is directed to overcoming or reducing the effects of one or more of the disadvantages set forth above.

According to one aspect of an embodiment of the present invention, a manufacturing method is provided that includes forming a solder mask in a circuit board including a first opening having sidewalls. A solder interconnect pad is formed in the first opening. The sidewalls define the lateral extent of the solder interconnect pads.

According to another aspect of an embodiment of the present invention, a method of manufacturing is provided that includes forming a solder mask on a semiconductor chip package substrate. The mask includes a first opening having sidewalls. A solder interconnect pad is formed in the first opening. The sidewalls define the lateral extent of the solder interconnect pads.

According to another aspect of an embodiment of the invention, a circuit board is provided that includes a solder mask. The solder mask includes a first opening having sidewalls. A solder interconnect pad is formed in the first opening. The sidewalls define the lateral extent of the solder interconnect pads.

These and other advantages of the present invention will become apparent upon reference to the following detailed description and drawings.

1 illustrates an example of a conventional semiconductor chip device including a semiconductor chip mounted on a circuit board; FIG. Figure 2 is a cross-sectional view taken at section 2-2 of Figure 1; 3 is an enlarged view of a portion of FIG. 2; FIG. FIG. 4 is a cross-sectional view similar to FIG. 3 of a conventional circuit board structure; 4 is a cross-sectional view similar to FIG. 3, assuming imperfect alignment of the solder mask openings; FIG. FIG. 5 is a cross-sectional view similar to FIG. 4, assuming imperfect alignment of solder mask openings in a conventional circuit board structure; FIG. 10 is a cross-sectional view showing an example of formation of buildup layers and via openings; 8 is a cross-sectional view similar to FIG. 7 showing an example of masking and trace formation; FIG. 9 is a cross-sectional view similar to FIG. 8 showing an example of forming a solder mask; FIG. 10 is a cross-sectional view similar to FIG. 9 showing an example formation of vias and solder interconnect pads; FIG. 11 is a cross-sectional view similar to FIG. 10 showing placement of additional metal over the solder interconnect pads; FIG. 8 is a cross-sectional view similar to FIG. 7, showing another example of formation of buildup layers and via openings; FIG. 13 is a cross-sectional view similar to FIG. 12 showing an example formation of solder interconnect pads and traces; FIG. 14 is a cross-sectional view similar to FIG. 13, showing another example of formation of a solder mask; FIG. 15 is a cross-sectional view similar to FIG. 14 showing placement of additional metal over the solder interconnect pads; FIG.

Various embodiments of printed circuit boards, such as semiconductor chip package substrates, are described herein. One example includes solder masks and solder interconnect pads, such as bump pads. A solder interconnect pad is positioned in the opening such that the sidewalls of the opening define the lateral extent of the solder interconnect pad. Further details are provided below.

In the drawings described below, reference numerals are generally repeated where the same element appears in more than one drawing. Referring now to the drawings, and in particular FIG. 1, a diagram of an exemplary embodiment of a circuit device 10 comprising a semiconductor chip 15 mounted on a circuit board 20 is shown. An underfill material layer 25 is disposed between the semiconductor chip 15 and the circuit board 20 to reduce the effects of CTE differences. Circuit board 20 is provided with numerous conductor traces and vias and other structures to carry power, ground and signals between semiconductor chip 15 and other circuit devices not shown. It's like Inputs and outputs in the form of pin grid arrays, ball grid arrays, land grid arrays or other types of interconnection schemes may be provided on circuit board 20 to facilitate these communications. In this exemplary embodiment, a ball grid array of solder balls 30 is provided on circuit board 20 .

The semiconductor chip 15 includes, for example, a myriad of different types of circuit devices used in electronic equipment such as microprocessors, graphics processors, microprocessor/graphics processor combinations, systems on chips, application specific integrated circuits, memory devices, and the like. It can be either. Also, semiconductor chip 15 may be single-core or multi-core, and other dies may be stacked on this chip. Semiconductor chip 15 may be composed of bulk semiconductors such as silicon or germanium, semiconductor-on-insulator materials such as silicon-on-insulator materials, graphite, or other materials. The semiconductor chip 15 may be flip-chip mounted to the circuit board 20 or electrically connected to the board by solder bonding or other structure. Interconnect schemes other than flip-chip solder bonding may be used.

Circuit board 20 may be a semiconductor chip package substrate, a circuit card, or substantially any other type of printed circuit board. A monolithic structure can be used for the circuit board 20, but in a more typical configuration a build-up design is used. In that case, the circuit board 20 may consist of a central core. One or more buildup layers are formed on this central core, and one or more other buildup layers are formed below the central core. The core itself may consist of a stack of one or more layers. An example of such a configuration may be a 2-2-2 configuration with a single layer core laminated between two sets of two build-up layers. When implemented as a semiconductor chip package substrate, the number of layers of the circuit board 20 can vary from 4 to 16 or more, but may be less than 4. So-called "coreless" designs can be used as well. Each layer of circuit board 20 may be composed of insulating materials such as various well-known epoxies or other polymers interspersed with metal interconnects. Multi-layer configurations other than build-up can also be used. Optionally, circuit board 20 may be constructed of well-known ceramics or other materials suitable for package substrates or other printed circuit boards.

Attention is now directed to FIG. This figure is a cross-sectional view of FIG. 1 taken at section 2-2. Note that cross-section 2-2 only includes a fairly small portion of semiconductor chip 15 and package substrate 20. FIG. Semiconductor chip 15 may be flip-chip mounted to circuit board 20 or electrically connected to the board by solder bumps, solder joints, conductive pillars, or other structures. In this exemplary embodiment, two solder interconnects or solder joints 35 , 40 are shown, at least partially surrounded by underfill 25 . Although only two solder joints 35 and 40 are shown, there may be tens, hundreds or even thousands of such joints depending on the scale of complexity of the semiconductor chip 15 and circuit board 20 . The solder joints 35,40 comprise solder bumps 45,50 connected to the semiconductor chip 15, presolders 55,60 metallurgically bonded to respective solder interconnect pads 65,70 of the circuit board 20, may consist of Solder bumps 45, 50 are metallurgically bonded to pre-solders 55, 60 by a reflow process and a bump collapse process.

Solder bumps 45, 50 and solder balls 30 may be constructed from various lead-based or lead-free solders. An exemplary lead-based solder may have a composition at or around the eutectic ratio, such as about 63% Sn and about 37% Pb. Examples of lead-free bases include tin-silver (about 98.2% Sn, about 1.8% Ag), tin-copper (about 99% Sn, about 1% Cu), tin-silver-copper (about 96.5% Sn, about 3% Ag, about 0.5% Cu) and the like. The pre-solders 55, 60 may consist of the same type of material. Optionally, the pre-solder 55, 60 may be eliminated and a single solder structure or solder plus conductive pillars may be chosen. The underfill material layer 25 may be, for example, an epoxy mixed with silica filler and phenolic resin, and this material layer is deposited before or after the reflow process to form the solder joints 35,40. good too. Pre-solder 55 , 60 and solder interconnect pads 65 , 70 are laterally surrounded by solder mask 75 . This solder mask is lithographically patterned, such as by laser ablation, to form a plurality of openings to match the various pre-solders (eg, pre-solders 55, 60). Another solder mask 77 is located on the opposite side of circuit board 20 to facilitate attachment of solder balls 30 . Solder masks 75 and 77 may be made from a variety of materials suitable for solder mask manufacture, such as, for example, PSR-4000 AUS703 from Taiyo Ink Mfg. Co., Ltd., or SR7000 from Hitachi Chemical Co., Ltd. good.

In this exemplary embodiment, circuit board 20 is implemented as a semiconductor chip package having a 2-2-2 build-up design. In so doing, interconnect layers or buildup layers 80 , 85 are formed on one side of core 87 and interconnect layers or buildup layers 90 , 95 are formed on the other side of core 87 . Core 87 may be monolithic, laminate, or two or more layers, as desired. The core 87 and build-up layers 80, 85, 90, 95 may be composed of well-known polymeric materials such as GX13 supplied by Ajinomoto Co., Inc. Build-up layers 80 , 85 , 90 , 95 , core 87 and solder masks 75 , 77 constitute the interconnection system of circuit board 20 . The following discussion of the various conductor configurations of FIG. 2 are illustrative of other conductor configurations for circuit board 20. FIG. The buildup layer 80 may include a respective conductor structure or pad 110, 115, and each conductor structure or pad 110, 115 is connected to the buildup layer 85 via a respective via 130, 135 formed in the buildup layer 80. may be interconnected with other sets of conductor structures or pads 120, 125, or may be in ohmic contact. Similarly, conductor pads 120 and 125 of buildup layer 85 may be electrically connected to upper solder interconnect pads 65 and 70 in solder mask 75 via respective vias 140 and 145 . Similarly, the electrical paths through buildup layers 90, 95 and solder mask 77 include contact pads 150, 155 and vias 160, 165 on buildup layer 90 and contact pads 170, 175 and corresponding vias 180 on buildup layer 95. , 185 and via ball pads 190, 195 of solder mask 77 connected to vias 180, 185. FIG. Solder balls 30 are metallurgically bonded to ball pads 190,195. An electrical path through core 87 may be provided through through vias 200 , 205 . These vias may be plated through holes or other types of conductors.

Still referring to FIG. 2, there may be a number of conductor traces interspersed around the solder interconnect pads 65 and 70 and covered by a solder mask 75 . Two of these traces are shown at 210 and 215, respectively. Build-up layers 80, 85, 90, 95 and solder mask 77 may include a plurality of such traces, but such traces are not shown for simplicity of illustration. In fact, there may be hundreds or more of such traces 210, 215 in circuit board 20 to provide flexible routing of power, ground and/or signals. The solder joints 35, 40 are manufactured with a bump pitch of _X1 , whose dimensions depend on various factors. Such factors include the size of semiconductor chip 15, the number of input/output paths required on semiconductor chip 15, and other considerations.

An enlarged view of the portion of FIG. 2 surrounded by the dashed oval 217 is shown in FIG. Attention is now directed to FIG. For context, FIG. 3 shows underfill 25 , solder bumps 45 , pre-solder 55 , conductor pads 65 , solder mask 75 and conductor traces 210 . Also shown are build-up layers 80, 85, vias 130, 140 and pads 120. FIG. Pre-solder 55 is placed in openings 220 in solder mask 75 . A technical objective of this exemplary embodiment is to form the contact pads 65 and the openings 220 in the solder mask 75 with the same or nearly the same lateral dimension _X2 . As will be explained in more detail below, this is accomplished by using the solder mask opening 220 as the limit for the possible lateral dimension _X2 of the pad 65. FIG. One purpose is to eliminate or substantially limit the interface between the top surface 225 of the contact pad 65 and the solder mask 75 . Another purpose is to provide a gap 227 between pad 65 and trace 210 having a width _X3 greater than conventional manufacturing processes and structures described below.

To understand the benefits of eliminating the solder mask interface with the top surface 225 of pad 65, it is helpful to briefly discuss the conventional solder mask and pad arrangement shown in FIG. Note that FIG. 4 is similar to FIG. 3 except for the placement of the conventional contact pads and solder mask. Here, pre-solder 232 has been fabricated on contact pads 234 . A solder mask 236 is fabricated over the contact pads 234 and patterned with openings 238 to accommodate the pre-solder 232 . Note that opening 238 has a lateral dimension of _X2 , while contact pad 234 is manufactured with a lateral dimension of _X4 . This dimension is typically about 20% larger than the lateral dimension _X2 of pad 65 in the exemplary embodiment described above. In FIG. 4, there are some technical implications that result from choosing such a design. First, the gap 241 between the conductor pad 234 and the conductor trace 243 has a width _X5 , which is much larger than the corresponding gap 227 between the conductor pad 65 and the trace 210. It is very narrow. Note that there is a substantial interface 249 between the top surface 251 of the contact pad 234 and the solder mask 236 . If a portion of solder mask 236 is present at interface 249, it can delaminate and move solder from pre-solder 232 toward trace 243, potentially causing a short circuit. This problem can be exacerbated if the solder mask openings 238 are not well aligned vertically with the contact pads 234 and/or the pads 234 are not well aligned vertically with the vias 253 . be. For example, as shown in FIG. 5, poor alignment of opening 238 and pre-solder 232 may result in lateral offset in the x-direction relative to pad 234 and/or misalignment of pad 234 with respect to via 253. and offset in the same direction, gap 241 has a slight width X ₆ such that X ₆ <X ₅ , so that solder penetrates from pre-solder 232 to interface 249 and shorts with trace 243 . more likely to do so. Returning to FIG. 3, note again that there is no or substantially no interface between solder mask 75 and top surface 225 of pad 65 similar to interface 249 described in connection with FIG. . Therefore, even if pads 65, openings 220 in solder mask 75, and pre-solder 55 are poorly aligned in the x-direction with respect to vias 140, as shown in FIG. are less likely to occur. This result is due in part to the larger dimensions of gap 227 compared to conventional gap 241 shown in FIG. 5, even when offset in the x-axis.

An exemplary method of manufacturing contact pads 65 and solder mask 75 can be understood by first referring to FIG. 7 of FIGS. 7-10. FIG. 7 is a cross-sectional view similar to FIG. The upper semiconductor chip 15 shown in FIG. 2 is not shown because it is not attached at this point. The following discussion will focus primarily on contact pads 65 and less on contact pads 70 . However, the discussion is applicable to other contact pads that interact with solder mask 75 as well. At this point, buildup layers 80 and 85 have been formed. A build-up layer 80 is provided by depositing one or more of the types of insulating material described elsewhere herein by spin coating or other techniques and curing by heating or otherwise. good too. Openings 256 may be formed in build-up layers 80 to match vias 130 by laser cutting. Laser 257 may apply laser radiation 259 as a pulsed or continuous beam. The wavelength and spot size of laser radiation 259 are selected to effectively remove material of buildup layer 80 while producing opening 256 with the desired size and footprint. For example, radiation 259 in the ultraviolet range and having a spot size in the range of 2.0-5.0 microns can be used. It is necessary that the opening 256 be drilled all the way down to the underlying pad 110 (see FIG. 2), but care is taken to ensure that the cutting process does not remove excess material from the pad 110. should.

Still referring to FIG. 7, vias 130 may be formed in openings 256 from a variety of conductive materials such as, for example, copper, aluminum, silver, gold, titanium, refractory metals, refractory metal compounds, alloys thereof, and the like. . Instead of a single structure, via 130 may consist of a stack of multiple metal layers, such as a titanium layer followed by a nickel-vanadium layer followed by a copper layer. In other embodiments, the titanium layer may be covered with a copper layer and then overcoated with nickel. However, those skilled in the art will appreciate that many types of conductive materials can be used for vias 130 . Various well-known techniques for applying metallic materials may be used, such as, for example, physical vapor deposition, chemical vapor deposition, plating, and the like. In an exemplary embodiment, vias may be formed by copper plating in two stages. The first step involves applying a relatively thin layer of copper to the openings 256 . In a second step, a bulk plating process is performed to fill vias 130 . To provide build-up layers 80, 85 and associated conductors on core 87 shown in FIG. It should also be understood that

Still referring to FIG. 7, a conductive layer is applied, masked, and etched to form conductive pads 120 and buildup layer 85 is formed using the techniques described above for buildup layer 80 . Conductive pads 120 may be formed using the materials and techniques described above with respect to vias 130 . Openings 263 may then be formed in build-up layer 85 to match unformed vias 140 (see FIG. 2). Laser drilling of the type described above using laser 257 and laser radiation 259 may be used.

Next, as shown in FIG. 8, selected portions of buildup layer 85 are masked using a suitable mask 266 . This mask may be dry film or photoresist. Via openings 263 and 264 are covered, but opening 269 in mask 266 is patterned. Well-known lithographic techniques may be used to apply and pattern mask 266 . A plating process may then be used to form traces 210 in openings 269 . Traces 210 may be formed of the same materials described above with respect to contact pads 120 . Mask 266 may be removed by ashing, solvent stripping, or both.

Referring now to FIG. 9, solder mask 75 may be deposited on buildup layer 85 using well-known solder mask deposition techniques such as, for example, spin coating or other desired deposition techniques. Openings 220, 273 may be formed in solder mask 75 over via openings 263, 264 by well-known lithographic patterning techniques. For example, solder mask 75 may be infused with one or more photoactive chemicals and provided with openings 220, 273 using an exposure and development process. Apertures 220 and 273 may be patterned with lateral dimension _X2 . This dimension is the preferred dimension of the contact pads 65 formed in subsequent processes. Thus, in this exemplary embodiment, solder mask 75 and openings 220 and 273 are used to define the lateral dimensions of solder interconnect pads 65 and 70 that will be subsequently formed. This is in contrast to conventional processes in which contact pads 65 are patterned by conventional masking and etching away.

10, vias 140 and 145 are provided in openings 263 and 264, and solder mask openings 220 and 273 are filled with the materials and techniques described above with respect to contact pads 120 and vias 130 shown in FIG. Interconnect pads 65, 70 may be provided. Note that solder mask openings 220,273 define the lateral dimensions of pads 65,70.

At this point, referring again to FIG. 3, pre-solder 55 (as well as pre-solder 60, although not shown) may be placed and formed in opening 220 as shown. For example, solder paste can be applied by a stencil or the like. Reflow may be performed at this point to bond the pre-solder 55 to the underlying contact pads 65 . After applying the pre-solder 55 , the semiconductor chip 15 shown in FIGS. 1 and 2 may be placed on the circuit board 20 and placed on the pre-solder 55 . A reflow process may be performed to produce the solder joints 35, 40 shown in FIG. The reflow temperature and duration depend on the type of solder and the shapes of the circuit board 20 and semiconductor chip 15 .

As shown in FIG. 11, another material may be applied to the solder interconnect pads 65, 70 at this stage. This may be desirable in situations where there is concern that constituents of the solder will diffuse into the solder interconnect pads 65, 70 and degrade their electrical performance. In this exemplary embodiment, the solder mask 75 may again be used to apply a conductor layer 279 to the solder interconnect pads 65, 70 to mask other features. The composition of conductor layer 279 may vary widely depending on device requirements. For example, in an exemplary embodiment, conductor layer 279 comprises a laminate starting at the bottom of an electrolessly plated nickel layer, followed by a plated palladium layer, and finally a plated gold layer. good too. Additionally, the material selected for the conductor layer 279 will depend on the type of solder used for pre-soldering, if any, and the type of solder used for the solder bumps 45 shown in FIG. Depends on technical requirements. Here, the conductor layer 279 provides a barrier to prevent solder diffusion even in the presence of the underlying solder interconnect pads 65, 70 and vias.

In the exemplary embodiment described above, the formation of the solder mask precedes the fabrication of the contact pads 65 shown in FIGS. 2 and 3, for example. However, a solder mask may be formed after the contact pads 65 in other exemplary embodiments. In this exemplary embodiment, processes may be performed generally as described above to provide build-up layers 80, 85, vias 130 and contact pads 120, as shown in FIG. At this point, openings 263 and 264 are provided in buildup layer 85 as described above. Next, as shown in FIG. 13, solder interconnect pads 65, 70 and conductor traces 210 are formed by applying a suitable conductor layer to buildup layer 85, followed by suitable masking and etching away. may A solder mask 75' may then be applied over the buildup layers 85 and over the conductor traces 210, as shown in FIG. Solder mask 75' may be patterned with openings 220' and 273'. While solder interconnect pads 65 and 70 are conveniently manufactured with lateral dimension _X2 as described above, apertures 220' and 273' are lateral apertures X slightly larger than lateral dimension _X2 of pad 65. ₇ to leave small gaps 281 surrounding the solder interconnect pads 65,70. Clearly, when viewed from above, gap 281 appears as a moat around solder interconnect pads 65,70. In subsequent material deposition processes, particularly plating processes, conductive material is sucked into the gaps 281 to fill the gaps 281 .

A plating process may then be used to partially fill openings 220' and 273' with additional metal of the type described above, as shown in FIG. As mentioned above, the gaps 281 draw in some of the deposited material 289, and in this sense the placement of that material is part of the process of forming the solder interconnect pads 65,70. Part of the motivation behind performing this supplemental deposition or plating process to provide material 289 is the vertical misalignment between openings 220' and 273' and underlying solder interconnect pads 65 and 70. The purpose is to provide some additional conductive material if the alignment is imperfect. The deposition of material 289 may be preceded by a pre-solder and/or solder bump process, generally as described above.

The processes described herein can be performed on individual circuit boards or collectively on a strip or other collection of multiple circuit boards. should be understood. If performed in bulk, the individual circuit boards may be singulated at some stage by sawing or other techniques.

Any of the exemplary embodiments disclosed herein may be embodied in instructions or computer data signals located on a computer-readable medium, such as a semiconductor, magnetic disk, optical disk, or other storage medium. may be embodied as The instructions or software may be capable of synthesizing and/or simulating the circuit structures disclosed herein. In an exemplary embodiment, electronic design automation programs such as Cadence APD, Encore, etc. may be used to synthesize the disclosed circuit structures. The code obtained may be used to fabricate the disclosed circuit structure.

While the invention is susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, it should be understood that the invention is not intended to be limited to the particular forms disclosed. Rather, the invention includes all modifications, equivalents and alternatives falling within the spirit and scope of the invention as defined by the following appended claims.

Claims (18)

forming a plurality of conductor traces (210, 215) on a circuit board (20);
providing solder interconnection pads (65) to said circuit board (20);
forming a solder mask (75) in the circuit board (20) including a first opening (220) having sidewalls and covering the plurality of conductor traces, the first opening overlying the solder interconnect; a step disposed about the connection pad (65);
said first opening having a lateral dimension greater than said solder interconnect pad, said first opening forming a gap between sidewalls of said solder mask and said solder interconnect pad; metal is added to the solder interconnect pads to fill gaps between the sidewalls and the solder interconnect pads ;
Production method. forming a second opening (263) in an interconnect layer (85) of the circuit board to expose an underlying contact pad (120), such that the first opening is aligned with the second opening. and forming said solder mask. 3. The method of claim 2, comprising forming a conductive via (140) in said second opening and forming said solder interconnect pad over said conductive via. After forming the solder interconnect pads, the solder mask and the first openings are formed without contacting the solder interconnect pads, and the metal is applied using a plating process to fill the gaps. The manufacturing method of claim 1, additionally . The method of claim 1, including the step of bonding solder bumps (55) to said solder interconnect pads. 2. The method of claim 1, including bonding a semiconductor chip (15) to the circuit board. 2. The method of claim 1, comprising forming said solder mask and said solder interconnect pads using instructions stored on a computer readable medium. forming a plurality of conductor traces (210, 215) on a semiconductor chip package substrate (20);
providing solder interconnect pads (65) to the semiconductor chip package substrate (20);
forming a solder mask (75) in the semiconductor chip package substrate (20) including a first opening (220) having sidewalls and covering the plurality of conductor traces, the first opening comprising the a step positioned around the solder interconnect pad (65);
said first opening having a lateral dimension greater than said solder interconnect pad, said first opening forming a gap between sidewalls of said solder mask and said solder interconnect pad; metal is added to the solder interconnect pads to fill gaps between the sidewalls and the solder interconnect pads ;
Production method. forming a second opening (263) in an interconnect layer (85) of said semiconductor chip package substrate exposing an underlying conductor pad (120), said first opening being aligned with said second opening. 9. The method of claim 8, comprising forming said solder mask to. 10. The method of claim 9, comprising forming a conductive via (140) in said second opening and forming said solder interconnect pad over said conductive via. After forming the solder interconnect pads, the solder mask and the first openings are formed without contacting the solder interconnect pads, and the metal is applied using a plating process to fill the gaps. 9. The method of manufacturing of claim 8, additionally . 9. The method of claim 8, comprising bonding a semiconductor chip (15) to the semiconductor chip package substrate. 9. The method of claim 8, comprising bonding a plurality of solder balls (30) to said semiconductor chip package substrate. A circuit board (20),
a plurality of conductor traces (210, 215);
a solder mask (75) of the circuit board including a first opening (220) having sidewalls and covering the plurality of conductor traces;
a solder interconnect pad (65) residing within said first opening, said first opening having a lateral dimension greater than said solder interconnect pad, said first opening comprising: forming a gap between the sidewalls of the solder mask and the solder interconnect pad, wherein metal is added to the solder interconnect pad to fill the gap between the sidewall and the solder interconnect pad; a solder interconnect pad;
A circuit board (20) comprising: 15. The circuit board of claim 14, including bonding solder bumps (55) to said solder interconnect pads. 15. The circuit board of claim 14, comprising a semiconductor chip (15) coupled to the circuit board. 15. The circuit board of claim 14, wherein said solder interconnect pads include a top surface (225), and wherein said solder mask does not contact said top surface so as to cover said top surface. 15. The circuit board of claim 14, wherein said circuit board comprises a semiconductor chip package substrate.

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