US20060219567A1 - Fabrication method of conductive bump structures of circuit board - Google Patents
Fabrication method of conductive bump structures of circuit board Download PDFInfo
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- US20060219567A1 US20060219567A1 US11/397,417 US39741706A US2006219567A1 US 20060219567 A1 US20060219567 A1 US 20060219567A1 US 39741706 A US39741706 A US 39741706A US 2006219567 A1 US2006219567 A1 US 2006219567A1
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- openings
- electrically connecting
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- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/02—Electroplating of selected surface areas
- C25D5/022—Electroplating of selected surface areas using masking means
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
- H05K3/3473—Plating of solder
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/421—Blind plated via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0364—Conductor shape
- H05K2201/0367—Metallic bump or raised conductor not used as solder bump
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09372—Pads and lands
- H05K2201/09436—Pads or lands on permanent coating which covers the other conductors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09563—Metal filled via
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/04—Soldering or other types of metallurgic bonding
- H05K2203/043—Reflowing of solder coated conductors, not during connection of components, e.g. reflowing solder paste
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/05—Patterning and lithography; Masks; Details of resist
- H05K2203/0502—Patterning and lithography
- H05K2203/054—Continuous temporary metal layer over resist, e.g. for selective electroplating
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/05—Patterning and lithography; Masks; Details of resist
- H05K2203/0562—Details of resist
- H05K2203/0568—Resist used for applying paste, ink or powder
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
- H05K3/061—Etching masks
- H05K3/062—Etching masks consisting of metals or alloys or metallic inorganic compounds
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
- H05K3/061—Etching masks
- H05K3/064—Photoresists
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
- H05K3/3485—Applying solder paste, slurry or powder
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/423—Plated through-holes or plated via connections characterised by electroplating method
Definitions
- the present invention relates to fabrication methods for conductive bump structures of circuit boards, and more particularly, to a method for fabricating conductive bump structures on electrically connecting pads of a circuit board.
- a plurality of electrode pads are disposed on surface of an IC chip and a plurality of electrically connecting pads corresponding to the electrode pads are formed on a circuit board. Then, the chip is disposed with its active face down on the circuit board and the electrode pads of the chip are electrically connected with the electrically connecting pads of the circuit board through a plurality of solder bumps or other conductive adhesive materials formed between the chip and the circuit board.
- solder bumps or conductive adhesive materials are disposed on electrode pads or electrically connecting pads by printing. With both reduced pitch and size of electrically connecting pads, it becomes difficult to attach the solder bumps to the electrically connecting pads, thereby resulting in the lack of enough bonding force between the solder material and the electrically connecting pads. In addition, in that the solder material support strength is not enough, it is easy for the solder material to overflow during the reflow process.
- an electroplating process is used to form solder material on a circuit board. Compared with the printing method, the electroplating process with higher accuracy can meet the requirements of fine routing so as to implement high-density wiring with reduced circuit board area.
- a conductive layer is first formed on the circuit. Then, solder material can be formed on the conductive layer. Detailed processing steps for the solder bumps are shown in FIGS. 1A to 1 F.
- a solder mask layer 11 is formed on a circuit board 10 with a plurality of electrically connecting pads 100 .
- a plurality of openings 110 are formed in the solder mask layer 11 to expose the electrically connecting pads 100 of the circuit board 10 .
- a conductive layer 12 is formed on the exposed surface of the solder mask layer 11 and the exposed surface of the electrically connecting pads 100 in the openings 110 .
- a resist layer is formed on the conductive layer 12 , the resist layer having openings 130 formed corresponding to the electrically connecting pads 100 to expose the conductive layer 12 .
- conductive bumps 14 are formed on the exposed surface of the conductive layer 12 by electroplating using the conductive layer 12 as a current conducting path.
- the resist layer 13 and the conductive layer 12 underneath the resist layer 13 are removed and a metal protection layer 15 is formed on the exposed surface of the conductive bumps 14 to protect the conductive bumps 14 .
- the conductive bumps 14 are formed in the region formed by openings 110 and the laminated openings 130 .
- the conductive layer 12 has a small electroplating area, it is difficult to keep the current density stable.
- the unstable current density often results in uneven conductive bumps 14 , thereby affecting subsequent processing steps.
- a primary objective of the present invention is to provide a fabrication method of conductive bump structures which can avoid unevenness between solder bumps to ensure stable electrical connections with external electronic devices.
- Another objective of the present invention is to provide a fabrication method of conductive bump structures that can avoid the small electroplating area and deep holes of the prior art, thereby facilitating the electroplating process.
- a further objective of the present invention is to decrease the use of solder material for environmental concern.
- Still another objective of the present invention is to provide a fabrication method of conductive bump structures that can form conductive structures on electrically connecting pads of fine pitch circuit boards for external electrical connections.
- the present invention discloses a fabrication method of conductive bump structures of a circuit board, comprising: providing a circuit board with a plurality of electrically connecting pads formed on at least one surface thereof and covering the circuit board with an insulating protection layer that has a plurality of openings to expose the electrically connecting pads; forming a conductive layer on the insulating protection layer and surface of the openings; forming a metal layer on the conductive layer by electroplating, the openings of the insulating protection layer being deposited by the metal layer; covering the metal layer with a resist layer which is further patterned such that the resist layer to form a plurality of openings corresponding to the electrically connecting pads to partially expose the metal layer; forming an adhesive layer in the openings of the resist layer; and removing the resist layer, and then removing the metal layer and the conductive layer that are not covered by the adhesive layer to form conductive bump structures on the electrically connecting pads.
- the adhesive layer is made of solder material, it is further reflowed to
- the fabrication method of conductive bump structures of a circuit board comprises: providing a circuit board with a plurality of electrically connecting pads formed on at least one surface thereof and covering the circuit board with an insulating protection layer that has a plurality of openings to expose the electrically connecting pads; forming a conductive layer on the insulating protection layer and surface of the openings and forming a metal layer on the conductive layer by electroplating, the openings of the insulating protection layer being deposited by the metal layer; covering the metal layer with a resist layer which is further patterned such that the resist layer only covers the metal layer corresponding in position to the electrically connecting pads; removing the metal layer and the conductive layer that are not covered by the resist layer; and removing the resist layer and forming an adhesive layer on exposed surface of the metal layer.
- a metal layer is directly formed on the whole conductive layer that is not covered by a resist layer and accordingly has a larger electroplating area compared with the prior art, thereby eliminating the prior art drawbacks such as a relatively small electroplating area, electroplating difficulty due to unstable current density, and the presence of deep holes.
- an even and flat surface for the metal layer of the present invention ensures that the subsequently formed conductive bump structures have uniform height, thereby improving the quality of electrical connections between the conductive bump structures and external electronic devices.
- the metal layer can be formed of a low cost copper layer, thereby reducing the fabrication cost and speeding up the fabrication process.
- the present invention also reduces the use of soldering material, which not only reduces the fabrication cost and protect environment, but also avoids bridge and short circuit problems caused by too much soldering material melted in the reflowing process.
- the present invention can provide conductive structures on electrically connecting pads of fine pitch circuit boards for external electrical connections.
- FIGS. 1A to 1 F are cross-sectional diagrams showing a conventional fabrication method of conductive bump structures on electrically connecting pads of a circuit board;
- FIGS. 2A to 2 L are cross-sectional diagrams showing a fabrication method of conductive bump structures of a circuit board according to a first embodiment of the present invention.
- FIGS. 3A to 3 G are cross-sectional diagrams showing a fabrication method of conductive bump structures of a circuit board according to a second embodiment of the present invention.
- FIGS. 2A to 2 L and 3 A to 3 G Preferred embodiments of a fabrication method of conductive bump structures of a circuit board proposed in the present invention are described as follows with reference to FIGS. 2A to 2 L and 3 A to 3 G.
- FIGS. 2A to 2 L show a fabrication method of conductive bump structures of a circuit board according to a first embodiment of the present invention. It should be noted that the figures are diagrams which only show basic constructions related to the present invention.
- a circuit board with a plurality of electrically connecting pads formed on surface thereof is first provided.
- a conductive layer 42 is formed on an insulating surface layer 41 of a circuit board to function as a current conductive path in a subsequent electroplating process.
- the conductive layer 42 can be a metal layer or several laminated metal layers formed of copper (Cu), tin (Sn), nickel (Ni), chromium (Cr), titanium (Ti), Cu—Cr alloy or tin-lead (Sn—Pb) alloy.
- the conductive layer 42 can be formed of conductive polymer material such as polyacetylene, polyanion or organic sulphur polymer.
- a resist layer 43 is formed on the conductive layer 42 by printing, spin-coating or attaching, wherein the resist layer 43 can be a photoresist layer such as a dry film layer or a liquid photoresist layer or a non-photoresist layer. Then, the resist layer 43 is patterned by development, exposure or laser to form a plurality of openings 430 to partially expose the conductive layer 42 . As shown in FIG. 2C , electrically connecting pads 440 are formed in the openings 430 on the exposed surface of the conductive layer 42 by electroplating using the conductive layer 42 as a current conducting path. Meanwhile, the conductive circuit (not shown) can be formed by the electroplating process. As shown in FIG. 2D , the resist layer 43 and the conductive layer 42 underneath the resist layer 43 are then removed.
- the resist layer 43 and the conductive layer 42 underneath the resist layer 43 are then removed.
- an insulating protection layer 45 is formed on surface of the circuit board.
- the insulating protection layer 45 is coated on the surface of the circuit board by printing, spin-coating or attaching and then patterned by exposure, development or laser to form a plurality of openings 450 to expose the electrically connecting pads 440 .
- the insulating protection layer 45 is formed of solder mask material.
- a conductive layer 46 is formed on the insulating protection layer 45 and surface of the openings 450 to function as current conductive path in a subsequent electroplating process.
- the conductive layer 46 can be made of a metal, an alloy or several laminated metal layers or conductive polymer material.
- a metal layer 47 is formed on the conductive layer 46 by electroplating using the conductive layer 46 as a current conductive path, and, meanwhile, the openings 450 are deposited by the metal layer 47 to keep the surface of the metal layer 47 even and flat.
- the metal layer 47 can be made of Pb, Sn, silver (Ag), Cu or an alloy thereof.
- the metal layer 47 is made of copper.
- a resist layer 48 is formed on the metal layer 47 and then patterned to form a plurality of openings 480 corresponding to the electrically connecting pads 440 to partially expose the metal layer 47 .
- the resist layer 48 is formed on the metal layer 47 by printing, spin-coating or attaching.
- an adhesive layer 49 is formed in the openings 480 , which can be formed of Cu, Sn, Pb, Ag, Ni, gold (Au), platinum (Pt) or an alloy thereof by electroplating or printing process.
- the resist layer 48 is removed by chemical etching or physical stripping.
- the metal layer 47 and the conductive layer 46 that are not covered by the adhesive layer 49 are removed, such that portions of the metal layer and conductive layer underneath the adhesive layer corresponding to the electrically connecting pads are retained to form the conductive bump structures on the electrically connecting pads. to form conductive bump structures on the electrically connecting pads 440 .
- the adhesive layer 49 is made of solder material, the adhesive layer 49 is reflowed to completely cover the exposed surface of the metal layer 47 .
- FIGS. 3A to 3 G show a fabrication process for conductive bump structures according to a second embodiment of the present invention.
- a circuit board 50 with a plurality of electrically connecting pads 510 formed on at least one surface thereof is provided.
- the circuit board 50 is covered by an insulating protection layer 55 .
- the insulating protection layer 55 is formed on the circuit board 50 by printing, spin-coating or attaching, which is then patterned to form a plurality of openings 550 to expose the electrically connecting pads 510 .
- a conductive layer 56 is formed on the insulating protection layer 55 and the surface of the openings 550 to function as a current conductive path in a subsequent electroplating process.
- a metal layer 57 is formed on the conductive layer 56 by electroplating using the conductive layer 56 as a current conductive path, the openings 550 of the insulating protection layer 55 being deposited by the metal layer 57 to keep the surface of the metal layer 57 even and flat.
- a resist layer 58 such as a dry film photoresist layer or a liquid photoresist layer is formed on the metal layer 57 by printing, spin-coating or attaching and then patterned such that the resist layer 58 only covers the metal layer 57 corresponding in position to the electrically connecting pads 510 .
- the metal layer 57 and the conductive layer 56 that are not covered by the resist layer 58 are removed, such that portions of the metal layer and conductive layer underneath the adhesive layer corresponding to the electrically connecting pads are retained to form the conductive bump structures on the electrically connecting pads.
- the resist layer 58 is removed by chemical etching or physical stripping such that an adhesive layer 59 can be formed on the exposed surface of the metal layer 47 by electroless plating.
- a metal layer is directly formed on the whole conductive layer that is not covered by a resist layer and accordingly has a larger electroplating area compared with the prior art, thereby eliminating the prior art drawbacks such as a relatively small electroplating area, electroplating difficulty due to unstable current density, and the presence of deep holes.
- the even and flat surface of the metal layer of the present invention ensures that the subsequently formed conductive bump structures have uniform height, thereby improving the quality of electrical connections between the circuit board and external electronic devices.
Abstract
A fabrication method of conductive bump structures of a circuit board includes providing the circuit board with a plurality of electrically connecting pads formed on at least one surface thereof and covering the circuit board with an insulating protection layer formed a plurality of openings to expose the electrically connecting pads; forming a conductive layer on surfaces of the insulating protection layer and openings, and forming a metal layer on the conductive layer by electroplating, with the openings of the insulating protection layer being deposited by the metal layer; forming a resist layer on the metal layer wherein the resist layer is further patterned to form a plurality of openings corresponding to the electrically connecting pads to partially expose the metal layer; forming an adhesive layer in the openings of the resist layer; and removing the resist layer, and then removing the metal layer and conductive layer not covered by the adhesive layer, to form conductive bump structures on the electrically connecting pads.
Description
- This application claims benefit under 35 USC 119 of Taiwan Application No. 094110691, filed Apr. 4, 2005.
- The present invention relates to fabrication methods for conductive bump structures of circuit boards, and more particularly, to a method for fabricating conductive bump structures on electrically connecting pads of a circuit board.
- To make electronic products much lighter, thinner, shorter, and smaller, packages that are characterized with a small integrated circuit area, high component density, and multiple pins, such as BGA, flip chip, MCM and so on, are becoming mainstream in the market. For example, in the flip chip technique, a plurality of electrode pads are disposed on surface of an IC chip and a plurality of electrically connecting pads corresponding to the electrode pads are formed on a circuit board. Then, the chip is disposed with its active face down on the circuit board and the electrode pads of the chip are electrically connected with the electrically connecting pads of the circuit board through a plurality of solder bumps or other conductive adhesive materials formed between the chip and the circuit board.
- Conventionally, solder bumps or conductive adhesive materials are disposed on electrode pads or electrically connecting pads by printing. With both reduced pitch and size of electrically connecting pads, it becomes difficult to attach the solder bumps to the electrically connecting pads, thereby resulting in the lack of enough bonding force between the solder material and the electrically connecting pads. In addition, in that the solder material support strength is not enough, it is easy for the solder material to overflow during the reflow process.
- To overcome the above drawbacks, an electroplating process is used to form solder material on a circuit board. Compared with the printing method, the electroplating process with higher accuracy can meet the requirements of fine routing so as to implement high-density wiring with reduced circuit board area. To form the solder bumps, a conductive layer is first formed on the circuit. Then, solder material can be formed on the conductive layer. Detailed processing steps for the solder bumps are shown in
FIGS. 1A to 1F. - As shown in
FIG. 1A , asolder mask layer 11 is formed on acircuit board 10 with a plurality of electrically connectingpads 100. - As shown in
FIG. 1B , a plurality ofopenings 110 are formed in thesolder mask layer 11 to expose the electrically connectingpads 100 of thecircuit board 10. - As shown in
FIG. 1C , aconductive layer 12 is formed on the exposed surface of thesolder mask layer 11 and the exposed surface of the electrically connectingpads 100 in theopenings 110. - As shown in
FIG. 1D , a resist layer is formed on theconductive layer 12, the resistlayer having openings 130 formed corresponding to the electrically connectingpads 100 to expose theconductive layer 12. - As shown in
FIG. 1E ,conductive bumps 14 are formed on the exposed surface of theconductive layer 12 by electroplating using theconductive layer 12 as a current conducting path. - As shown in
FIG. 1F , theresist layer 13 and theconductive layer 12 underneath theresist layer 13 are removed and ametal protection layer 15 is formed on the exposed surface of theconductive bumps 14 to protect theconductive bumps 14. - In this conventional fabrication method, the
conductive bumps 14 are formed in the region formed byopenings 110 and the laminatedopenings 130. However, the deeper the openings are, the more difficult it is to form theconductive bumps 14 by electroplating. - Moreover, because the
conductive layer 12 has a small electroplating area, it is difficult to keep the current density stable. The unstable current density often results in unevenconductive bumps 14, thereby affecting subsequent processing steps. - According to the above drawbacks, a primary objective of the present invention is to provide a fabrication method of conductive bump structures which can avoid unevenness between solder bumps to ensure stable electrical connections with external electronic devices.
- Another objective of the present invention is to provide a fabrication method of conductive bump structures that can avoid the small electroplating area and deep holes of the prior art, thereby facilitating the electroplating process.
- A further objective of the present invention is to decrease the use of solder material for environmental concern.
- Still another objective of the present invention is to provide a fabrication method of conductive bump structures that can form conductive structures on electrically connecting pads of fine pitch circuit boards for external electrical connections.
- To achieve the above and other objectives, the present invention discloses a fabrication method of conductive bump structures of a circuit board, comprising: providing a circuit board with a plurality of electrically connecting pads formed on at least one surface thereof and covering the circuit board with an insulating protection layer that has a plurality of openings to expose the electrically connecting pads; forming a conductive layer on the insulating protection layer and surface of the openings; forming a metal layer on the conductive layer by electroplating, the openings of the insulating protection layer being deposited by the metal layer; covering the metal layer with a resist layer which is further patterned such that the resist layer to form a plurality of openings corresponding to the electrically connecting pads to partially expose the metal layer; forming an adhesive layer in the openings of the resist layer; and removing the resist layer, and then removing the metal layer and the conductive layer that are not covered by the adhesive layer to form conductive bump structures on the electrically connecting pads. Therein, if the adhesive layer is made of solder material, it is further reflowed to cover exposed surface of the metal layer.
- According to another embodiment of the present invention, the fabrication method of conductive bump structures of a circuit board comprises: providing a circuit board with a plurality of electrically connecting pads formed on at least one surface thereof and covering the circuit board with an insulating protection layer that has a plurality of openings to expose the electrically connecting pads; forming a conductive layer on the insulating protection layer and surface of the openings and forming a metal layer on the conductive layer by electroplating, the openings of the insulating protection layer being deposited by the metal layer; covering the metal layer with a resist layer which is further patterned such that the resist layer only covers the metal layer corresponding in position to the electrically connecting pads; removing the metal layer and the conductive layer that are not covered by the resist layer; and removing the resist layer and forming an adhesive layer on exposed surface of the metal layer.
- In the present invention, a metal layer is directly formed on the whole conductive layer that is not covered by a resist layer and accordingly has a larger electroplating area compared with the prior art, thereby eliminating the prior art drawbacks such as a relatively small electroplating area, electroplating difficulty due to unstable current density, and the presence of deep holes. In addition, an even and flat surface for the metal layer of the present invention ensures that the subsequently formed conductive bump structures have uniform height, thereby improving the quality of electrical connections between the conductive bump structures and external electronic devices.
- Furthermore, the metal layer can be formed of a low cost copper layer, thereby reducing the fabrication cost and speeding up the fabrication process. The present invention also reduces the use of soldering material, which not only reduces the fabrication cost and protect environment, but also avoids bridge and short circuit problems caused by too much soldering material melted in the reflowing process. Thus, the present invention can provide conductive structures on electrically connecting pads of fine pitch circuit boards for external electrical connections.
-
FIGS. 1A to 1F (PRIOR ART) are cross-sectional diagrams showing a conventional fabrication method of conductive bump structures on electrically connecting pads of a circuit board; -
FIGS. 2A to 2L are cross-sectional diagrams showing a fabrication method of conductive bump structures of a circuit board according to a first embodiment of the present invention; and -
FIGS. 3A to 3G are cross-sectional diagrams showing a fabrication method of conductive bump structures of a circuit board according to a second embodiment of the present invention. - Preferred embodiments of a fabrication method of conductive bump structures of a circuit board proposed in the present invention are described as follows with reference to
FIGS. 2A to 2L and 3A to 3G. -
FIGS. 2A to 2L show a fabrication method of conductive bump structures of a circuit board according to a first embodiment of the present invention. It should be noted that the figures are diagrams which only show basic constructions related to the present invention. - As shown in
FIGS. 2A to 2D, a circuit board with a plurality of electrically connecting pads formed on surface thereof is first provided. As shown inFIG. 2A , aconductive layer 42 is formed on aninsulating surface layer 41 of a circuit board to function as a current conductive path in a subsequent electroplating process. Theconductive layer 42 can be a metal layer or several laminated metal layers formed of copper (Cu), tin (Sn), nickel (Ni), chromium (Cr), titanium (Ti), Cu—Cr alloy or tin-lead (Sn—Pb) alloy. Alternatively, theconductive layer 42 can be formed of conductive polymer material such as polyacetylene, polyanion or organic sulphur polymer. As shown inFIG. 2B , a resistlayer 43 is formed on theconductive layer 42 by printing, spin-coating or attaching, wherein the resistlayer 43 can be a photoresist layer such as a dry film layer or a liquid photoresist layer or a non-photoresist layer. Then, the resistlayer 43 is patterned by development, exposure or laser to form a plurality ofopenings 430 to partially expose theconductive layer 42. As shown inFIG. 2C , electrically connectingpads 440 are formed in theopenings 430 on the exposed surface of theconductive layer 42 by electroplating using theconductive layer 42 as a current conducting path. Meanwhile, the conductive circuit (not shown) can be formed by the electroplating process. As shown inFIG. 2D , the resistlayer 43 and theconductive layer 42 underneath the resistlayer 43 are then removed. - Referring to
FIG. 2E , an insulatingprotection layer 45 is formed on surface of the circuit board. In the present embodiment, the insulatingprotection layer 45 is coated on the surface of the circuit board by printing, spin-coating or attaching and then patterned by exposure, development or laser to form a plurality ofopenings 450 to expose the electrically connectingpads 440. Wherein, the insulatingprotection layer 45 is formed of solder mask material. - Referring to
FIG. 2F , aconductive layer 46 is formed on the insulatingprotection layer 45 and surface of theopenings 450 to function as current conductive path in a subsequent electroplating process. Theconductive layer 46 can be made of a metal, an alloy or several laminated metal layers or conductive polymer material. - Referring to
FIG. 2G , ametal layer 47 is formed on theconductive layer 46 by electroplating using theconductive layer 46 as a current conductive path, and, meanwhile, theopenings 450 are deposited by themetal layer 47 to keep the surface of themetal layer 47 even and flat. Wherein, themetal layer 47 can be made of Pb, Sn, silver (Ag), Cu or an alloy thereof. Preferably, themetal layer 47 is made of copper. - Referring to
FIG. 2H , a resistlayer 48 is formed on themetal layer 47 and then patterned to form a plurality ofopenings 480 corresponding to the electrically connectingpads 440 to partially expose themetal layer 47. In the present embodiment, the resistlayer 48 is formed on themetal layer 47 by printing, spin-coating or attaching. - Referring to
FIG. 2I , anadhesive layer 49 is formed in theopenings 480, which can be formed of Cu, Sn, Pb, Ag, Ni, gold (Au), platinum (Pt) or an alloy thereof by electroplating or printing process. - Referring to
FIG. 2J , the resistlayer 48 is removed by chemical etching or physical stripping. - Referring to
FIG. 2K , themetal layer 47 and theconductive layer 46 that are not covered by theadhesive layer 49 are removed, such that portions of the metal layer and conductive layer underneath the adhesive layer corresponding to the electrically connecting pads are retained to form the conductive bump structures on the electrically connecting pads. to form conductive bump structures on the electrically connectingpads 440. - Referring to
FIG. 2L , if theadhesive layer 49 is made of solder material, theadhesive layer 49 is reflowed to completely cover the exposed surface of themetal layer 47. -
FIGS. 3A to 3G show a fabrication process for conductive bump structures according to a second embodiment of the present invention. - Referring to
FIG. 3A , acircuit board 50 with a plurality of electrically connectingpads 510 formed on at least one surface thereof is provided. - Referring to
FIG. 3B , thecircuit board 50 is covered by an insulatingprotection layer 55. In the present embodiment, the insulatingprotection layer 55 is formed on thecircuit board 50 by printing, spin-coating or attaching, which is then patterned to form a plurality ofopenings 550 to expose the electrically connectingpads 510. - Referring to
FIG. 3C , aconductive layer 56 is formed on the insulatingprotection layer 55 and the surface of theopenings 550 to function as a current conductive path in a subsequent electroplating process. - Referring to
FIG. 3D , ametal layer 57 is formed on theconductive layer 56 by electroplating using theconductive layer 56 as a current conductive path, theopenings 550 of the insulatingprotection layer 55 being deposited by themetal layer 57 to keep the surface of themetal layer 57 even and flat. - Referring to
FIG. 3E , a resistlayer 58 such as a dry film photoresist layer or a liquid photoresist layer is formed on themetal layer 57 by printing, spin-coating or attaching and then patterned such that the resistlayer 58 only covers themetal layer 57 corresponding in position to the electrically connectingpads 510. - Referring to
FIG. 3F , themetal layer 57 and theconductive layer 56 that are not covered by the resistlayer 58 are removed, such that portions of the metal layer and conductive layer underneath the adhesive layer corresponding to the electrically connecting pads are retained to form the conductive bump structures on the electrically connecting pads. - Referring to
FIG. 3G , the resistlayer 58 is removed by chemical etching or physical stripping such that anadhesive layer 59 can be formed on the exposed surface of themetal layer 47 by electroless plating. - In the present invention, a metal layer is directly formed on the whole conductive layer that is not covered by a resist layer and accordingly has a larger electroplating area compared with the prior art, thereby eliminating the prior art drawbacks such as a relatively small electroplating area, electroplating difficulty due to unstable current density, and the presence of deep holes. In addition, the even and flat surface of the metal layer of the present invention ensures that the subsequently formed conductive bump structures have uniform height, thereby improving the quality of electrical connections between the circuit board and external electronic devices.
- The invention has been described using exemplary preferred embodiments. However, it is to be understood that the scope of the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements. The scope of the claims, therefore, should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
Claims (16)
1. A fabrication method of conductive bump structures of a circuit board, comprising the steps of:
providing the circuit board with a plurality of electrically connecting pads formed on at least one surface thereof, and applying an insulating protection layer on the circuit board, the insulating protection layer having a plurality of openings to expose the electrically connecting pads;
forming a conductive layer on surfaces of the insulating protection layer and openings thereof, and forming a metal layer on the conductive layer by electroplating, with the openings of the insulating protection layer being deposited by the metal layer;
forming a resist layer on the metal layer, wherein the resist layer is further patterned to form a plurality of openings corresponding to the electrically connecting pads to partially expose the metal layer;
forming an adhesive layer in the openings of the resist layer; and
removing the resist layer, and then removing the metal layer and conductive layer that are not covered by the adhesive layer, such that portions of the metal layer and conductive layer underneath the adhesive layer corresponding to the electrically connecting pads are retained to form the conductive bump structures on the electrically connecting pads.
2. The fabrication method of claim 1 , wherein the electrically connecting pads are fabricated by steps comprising:
forming a conductive layer on an insulating surface layer of the circuit board;
forming a resist layer on the conductive layer on the insulating surface layer and forming a plurality of openings on the resist layer to partially expose the conductive layer on the insulating surface layer; and
forming the electrically connecting pads in the openings of the resist layer by electroplating.
3. The fabrication method of claim 2 , further comprising removing the resist layer and the conductive layer underneath the resist layer.
4. The fabrication method of claim 1 , wherein the adhesive layer is formed on the metal layer by one of an electroplating process and a printing process.
5. The fabrication method of claim 1 , wherein the adhesive layer is made of a material selected from the group consisting of tin (Sn), silver (Ag), gold (Au), copper (Cu), nickel (Ni), lead (Pb), platinum (Pt) and an alloy thereof.
6. The fabrication method of claim 5 , wherein the adhesive layer is reflowed to completely cover an exposed surface of the metal layer partially exposed via the openings of the resist layer.
7. The fabrication method of claim 1 , wherein the metal layer is made of a material selected from the group consisting of Pb, Sn, Ag, Cu and an alloy thereof.
8. The fabrication method of claim 1 , wherein the conductive layer is made of a metal material.
9. The fabrication method of claim 1 , wherein the conductive layer is made of an organic polymer material.
10. A fabrication method of conductive bump structures of a circuit board, comprising the steps of:
providing the circuit board with a plurality of electrically connecting pads formed on at least one surface thereof, and applying an insulating protection layer on the circuit board, the insulating protection layer having a plurality of openings to expose the electrically connecting pads;
forming a conductive layer on surfaces of the insulating protection layer and openings thereof, and forming a metal layer on the conductive layer by electroplating, with the openings of the insulating protection layer being deposited by the metal layer;
applying a resist layer on the metal layer and patterning the resist layer such that the resist layer only covers the metal layer corresponding to the electrically connecting pads;
removing the metal layer and the conductive layer that are not covered by the resist layer; and
removing the resist layer and forming an adhesive layer on an exposed surface of the metal layer by electroless plating.
11. The fabrication method of claim 10 , wherein the electrically connecting pads are fabricated by steps comprising:
forming a conductive layer on an insulating surface layer of the circuit board;
forming a resist layer on the conductive layer on the insulating surface layer and forming a plurality of openings on the resist layer to partially expose the conductive layer on the insulating surface layer; and
forming the electrically connecting pads in the openings of the resist layer by electroplating.
12. The fabrication method of claim 11 , further comprising removing the resist layer and the conductive layer underneath the resist layer.
13. The fabrication method of claim 10 , wherein the adhesive layer is made of a material selected from the group consisting of Sn, Ag, Au, Cu, Ni, Pb, Pt and an alloy thereof.
14. The fabrication method of claim 10 , wherein the metal layer is made of a material selected from the group consisting of Pb, Sn, Ag, Cu and an alloy thereof.
15. The fabrication method of claim 10 , wherein the conductive layer is made of a metal material.
16. The fabrication method of claim 10 , wherein the conductive layer is made of an organic polymer material.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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TW094110691A TWI270329B (en) | 2005-04-04 | 2005-04-04 | Method for fabricating conducting bump structures of circuit board |
TW094110691 | 2005-04-04 |
Publications (1)
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US20060219567A1 true US20060219567A1 (en) | 2006-10-05 |
Family
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US11/397,417 Abandoned US20060219567A1 (en) | 2005-04-04 | 2006-04-03 | Fabrication method of conductive bump structures of circuit board |
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US (1) | US20060219567A1 (en) |
TW (1) | TWI270329B (en) |
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US20080179190A1 (en) * | 2005-03-09 | 2008-07-31 | Phoenix Precision Technology Corporation | Method for fabrication of a conductive bump structure of a circuit board |
US20090050359A1 (en) * | 2007-08-23 | 2009-02-26 | Phoenix Precision Technology Corporation | Circuit board having electrically connecting structure and fabrication method thereof |
EP2180770A1 (en) * | 2008-10-21 | 2010-04-28 | Atotech Deutschland Gmbh | Method to form solder deposits on substrates |
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US20110291273A1 (en) * | 2010-05-26 | 2011-12-01 | Chipmos Technologies Inc. | Chip bump structure and method for forming the same |
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TW200637448A (en) | 2006-10-16 |
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