1270329 九、發明說明： 【發明所屬之技術領域】 =明係有關於-種電路板導電凸塊結構之製法，尤 構種在電路板之電性連接塾上形成導電凸塊結 【先前技術】 為使封裝件更輕薄短小，生產且 墊尺寸之细缚挪彳F. 產/、有鈿小線路覓度與焊 之目根，而： e 業已成為業界持續努力 s. τ β 如 BGA、Fllp Chlp、晶片尺寸封褒（CSP, Chip ^ pac age)與多晶片模組（MCM，咖“ c叫则加 路的面積且具有高密度與多接腳化特性之封裝 ，，二斤成為封裝市場上的主流。以覆晶技術為例1270329 IX. Description of the invention: [Technical field of the invention] = Ming system has a method for manufacturing a conductive bump structure of a circuit board, and particularly a conductive bump is formed on an electrical connection of a circuit board. [Prior Art] In order to make the package lighter and thinner, the production and the size of the pad are moved to the F. production/, with a small line twist and the root of the welding, and: e has become a continuous effort in the industry. τ β such as BGA, Fllp Chlp, Chip Size Socket (CSP) and Multi-Chip Module (MCM), which is a package with an area of high-density and multi-pinning characteristics, and two kilograms become the packaging market. The mainstream of the above. Take the flip chip technology as an example.
Hi 導體積體電路（IC)晶片的表面上配置有電 ^ (Electrode pads)，並且於電路板上形成有相對應之命 早猎由在。亥曰曰片與電路板之間設置焊錫凸塊 s:bump)或其他導電黏著材料，以提供該晶片以 接觸面朝下的方式設置於該電路板上。 在現行覆晶技術中，半導體積體電 :有電極墊細-一而電路板亦具有 性連接墊，在該晶片的電 心、甩 置焊錫凸Mm + 的電性連接塾可設 :干錫嶋其他導電黏著材料，而該晶片係以 面朝下的方式接置於該電路板上，其中，今觸 電黏著材料提供該晶片以及電 X .鬼或導 (i/〇)的連接。 及$路板間的讀輸入/輸出 ]8]83 1270329 塊或㈣板的電性連接塾形成焊錫凸 性連接塾之間隙：二的方式形成，但隨著電 縮小，造成後續性連接墊之尺寸更加 旻·、’、員$成:^干錫凸塊不易附基 上，導致焊錫材料與電性連接塾之間的二性連接墊 由於烊踢材料支撐強度不足，致；:：：佳’同時 錫材料亦會有溢流之現象。 、斗蚪叉熱熔融之焊 為解決上述弊端，或有以電鍍方 + 錫材料之技術，藉以達到細線路之目的二板上形成焊 焊錫的方式相較於印刷塗佈 於電鍍形成預 到細線路，以達高密声你碎、，:精达、度，因而得以達 鑛方式在電路板的；:連接板面積。而以電 該電性連接墊上形成導電層，以在焊錫前，則先在 錫。而在電路板之電性連接塾上形=電=上形成電鍍焊 第1Α圖至第1F圖所示。 y兒鍍焊錫之技術，如 請參閱第1A圖，待於 θ , 之電路板1〇上η , 具有複數個電性連接請 。月芩閱第1Β圖，於該防焊 以顯露出該電路板10之電性連接塾^成有開孔110，俾 凊芩閱第1C圖’接著在該防 内的電性連接墊100表面形：“及其開孔110 請參閱第m圖，復於干电層i2(seedlayer)。 形成有開孔一以外辑於:^ ]8]83 6 1270329 電層12。 “閱第1E圖’然後進行電鍍製程，|i由哕導#声 12作為電鍍的通路，以在h 赭由Μ电層 . 在4笔路板10之電性連接墊100 上形成導電凸塊14。 請參閱第1F圖，之徭梦^ # 電層12,並於該導電凸塊二该阻層13及其所覆蓋之導 以保護該導電凸塊14。 面形成金屬保護層15,藉 層係形成在防焊層11之開孔110及阻 深較n I巾’而该開孔110及130疊置所構成的孔 7《於孔形較深的孔巾形成導電 鍍製程的困難度。 只P曰加免 再者，欲於開孔i丨〇、丨3〇中形 所欲電錄的區域面積小，故所;電’因該 =定，使得該些導電凸塊14形成後的高度;= 千正性i而影響後續製程之進行。 、 因此，鑒於上述之問題，如 凸塊在孔形較心… ㈣免白知技術中之導電 札H乂冰及所欲電鍍的區域 整性不佳影響^中心成，導致平 題。 “衣私之進仃，貫已成目前亟欲解決的課 【發明内容】 鑒方、别述習知技術之缺點，本 -種電路板導電凸塊…” 要目的係提供 導電凸塊之平敕：以避免產生電路板表面 電性連接製程可靠度問題。 /、Μ…件作 】8183 7 1270329 本發明之再—目的係提供一種電 製法，得以避免習知由於電 、电凸塊結構之 兒級适域面積小或备 較深，導致電鍍製程難度增加等問題。' —兔鍍區域孔形 本發明之另—目的係提供—種電 製法，可減少焊锡材料使用量及__ /凸塊結構之 本發明之又再一目的係提供 及其製法，俾得有 種电路板導電凸塊結構 向外作電性導接之導電結^距之笔路板電性連接塾上形成 為達上述及其他目的，本發 一 塊結構之製法，係包括以下步驟：提：：至：路板導電凸 =電性連接墊之電路板，且於該電路板面形成 保纟又層，並令該絕緣保護 谈现一絕緣 連接墊；於該絕緣保護層路出该琶性 該導兩衣向办成一導電層，B 士人 。亥W層上電鍍形成—金屬 ：，且於 緣保護層開口中；於該金〜屬層填充於該絕 對應該電性連接墊位置形成一阻層，且令該阻層 y成(有開口，以夕卜霞山 -，於相層開口中形成_ 。刀。亥金屬 該層所覆蓋之金屬層及導 ：/及私除該阻層及為 性連接墊上形成導電凸塊 路板表面之電 材料，後續復包括進行回尸制中㈣黏著層為焊錫 ‘者層包覆於該金屬層之外露表面上。 干錫材料之 本發明之電路板導電凸塊 例係包括以下實施步驟：提；另-較佳實施 墊之電路板，且於該電路:二！面形成有複數電性連接 板上復盍一絕緣保護層，並令該 8 ]8]83 1270329 絕緣保護層形成複數開口以 保護層及其開口表面形成—導；; 亥笔性連接塾’ ·於該絕緣 形成一金屬層，並使該金^心二於該導電層上電錢 中；於該金屬層上形成=保護層開口 該阻層僅覆蓋住對應於該電性 订13木化製程，以使 層；移除外露於該阻層之金屬 分金屬 之蛉电層，以及移除該阻層，並於 α復皿 一黏著層。 / 萄層外路表面形成 因此，本發明之電路板導電凸塊聋 在電路板上形成具禎激η η ^ 苒之衣法主要係 說车 /、 幵之絕緣保護層以外露出兮命？々 板表面之電性連接墊 。出.亥电路The surface of the Hi-conductor circuit (IC) wafer is provided with an electric (Electrode pads), and a corresponding life is formed on the circuit board. A solder bump s:bump or other conductive adhesive material is disposed between the chip and the circuit board to provide the wafer on the circuit board with the contact surface facing downward. In the current flip chip technology, the semiconductor integrated body has a thin electrode pad and the circuit board also has a connection pad. The electrical connection between the core of the wafer and the solder bump Mm + can be set: dry tin The other electrically conductive adhesive material is attached to the circuit board in a face down manner, wherein the current electric contact adhesive material provides the wafer and the electrical or magnetic connection. And the reading/output between the road boards] 8] 83 1270329 The electrical connection of the block or (four) board forms the gap of the solder bump connection: the second way is formed, but as the electricity shrinks, the subsequent connection pads are formed. The size is even more 旻·, ', member $ into: ^ dry tin bumps are not easy to attach to the base, resulting in the connection between the solder material and the electrical connection between the two-sided connection pad due to insufficient strength of the kicking material support;::: good 'At the same time, the tin material will also overflow. The hot melt welding of the bucket fork is to solve the above drawbacks, or the technology of electroplating + tin material, in order to achieve the purpose of the fine line, the way of forming the solder on the second board is compared with the printing coating on the plating to form the pre-fine line Road, to the high-density sound you break,: fine, degree, and thus can reach the mining method on the circuit board;: connecting board area. The conductive layer is formed on the electrical connection pad to be in the tin before soldering. On the electrical connection of the circuit board, the shape of the upper plate = electric = the plating is formed on the first to the first. y solder plating technology, as shown in Figure 1A, to θ, the circuit board 1 〇 η, with a number of electrical connections please. Referring to FIG. 1 , the soldering is performed to expose the electrical connection of the circuit board 10 to the opening 110, and the surface of the electrical connection pad 100 is then referred to in FIG. Shape: "and its opening 110, please refer to the mth picture, which is repeated on the dry layer i2 (seedlayer). The opening is formed separately from the following: ^]8]83 6 1270329 Electrical layer 12. "Reading Figure 1E" Then, an electroplating process is performed, and |i is used as a path for electroplating to form a conductive bump 14 on the electrical connection pad 100 of the four-way board 10. Referring to FIG. 1F, the electric layer 12, and the conductive layer 2 and the covered layer 13 are covered to protect the conductive bump 14. The metal protective layer 15 is formed on the surface, and the hole is formed in the opening 110 of the solder resist layer 11 and the hole 7 is formed by stacking the openings 110 and 130. The difficulty in forming a conductive plating process. Only P 曰 曰 再 , , , , , , , , , , , 欲 欲 欲 丨〇 丨〇 丨〇 丨〇 丨〇 丨〇 丨〇 丨〇 丨〇 丨〇 丨〇 丨〇 丨〇 丨〇 丨〇 丨〇 丨〇 丨〇 丨〇 丨〇 丨〇 丨〇 丨〇 丨〇 丨〇 丨〇 丨〇 丨〇 丨〇 丨〇 丨〇 Height; = 1000 positive i affects the progress of subsequent processes. Therefore, in view of the above problems, such as the bumps in the shape of the hole is concentric... (4) Conductive in the technology of the white-free technology. The surface of the ice and the area to be electroplated affects the centering, resulting in a problem. "The advancement of clothing and private, has become the current class that wants to solve. [Invention] The shortcomings of the prescription and other known techniques, this kind of circuit board conductive bumps..." The purpose is to provide the level of conductive bumps.敕: To avoid the problem of reliability of the process of electrical connection on the board surface. /, Μ...pieces] 8183 7 1270329 A further object of the present invention is to provide an electro-fabrication method to avoid the difficulty And other issues. '- Rabbit plating area hole shape Another object of the present invention is to provide a method of electroforming, which can reduce the amount of solder material used and __ / bump structure, and another object of the present invention and its preparation method, The conductive bump structure of the circuit board is electrically connected to the conductive junction of the conductive board, and the electrical connection of the pen board is formed to achieve the above and other purposes. The method for manufacturing the structure of the present invention comprises the following steps: : to: the conductive plate of the road board = the circuit board of the electrical connection pad, and the layer of the circuit board is formed with a protective layer, and the insulation protection is said to be an insulating connection pad; the insult is formed in the insulation protection layer The two garments are made into a conductive layer, B. Electroplating is formed on the W layer to form a metal: and is in the opening of the edge protective layer; the gold layer is filled in the absolute electrical connection pad to form a resist layer, and the resist layer is formed into an opening. In the case of Xi Xi Xiashan, the formation of _. Knife. The metal layer and the conductor covered by the layer of the metal: and the private layer and the surface of the conductive pad forming the surface of the conductive bump The material is subsequently included in the corpse (4) the adhesive layer is soldered to the exposed surface of the metal layer. The dry tin material of the circuit board conductive bump of the present invention includes the following implementation steps: In addition, the circuit board of the pad is preferably implemented, and the insulating layer of the insulating layer is formed on the plurality of electrical connecting plates, and the insulating layer of the 8]8] 83 1270329 is formed to form a plurality of openings to protect the circuit board. The layer and its open surface are formed as a guide; a pen-like connection 塾', a metal layer is formed on the insulation, and the gold core is deposited on the conductive layer; a protective layer is formed on the metal layer Opening the resist layer only covers the woody corresponding to the electrical order a layer to remove the metal layer of the metal component exposed to the barrier layer, and to remove the barrier layer, and an adhesive layer on the alpha compound. / The outer surface of the layer is formed. Therefore, the present invention The conductive bumps of the circuit board are formed on the circuit board by the method of stimulating η η ^ 主要. The main method is to expose the electrical connection pads of the surface of the raft on the outer surface of the insulation layer of the vehicle/, 幵.
成道十a 於該絕緣保護層及開口表W 成一導電層，不同於習知之 表面形 口疊置的孔形，藉由該導電二：：成阻層，再形成開 m备表面積，而提供較 。 上電鑛形成-金屬層，再移除部：=方，層 再於其表面形成:;二連接塾部分之金屬層及導電層， 接墊上形成導電凸塊結構反表面之電性連 區域面積過小，所提 i免白知電鑛製程中電鍍 電鍍製程因難度増加，且本發明 =面而， 该絕緣保護層之表面及開 j先王面，成於 ，心的金屬層以形成高度一 ： 俾可避免習知電铲制 〒兒凸塊結構， 置開=接於絕緣保護層與阻層之4 成W凸塊時，因欲於孔形較深的孔中形 9 18183 1270329 ;導電凸塊’而增加電鍍製程的困難度，導致卜 度—致性無法控制，造成電路板與外界電：：_鬼高 完成電性連接。 电子兀件無法有效 同時，本發明之電路板導電凸塊結 電路板表面之絕緣保護層上依次形成導衣〉中，係於 移除部分金屬層及其所覆蓋 '二:屬層，於 藉以在該電路板之電性連接塾上形二：：成㈣層’ 技術中，於絕緣保護層上形成導電層 、避免智知 阻層，然後於絕緣保護層及阻層之開 上形成 塊，高所導致電_二^ 卷月可由材料成本較低且 、 :;物峨鐘出銅質之金屬層，藉以縮 程難^了^由較大的電鑛區域進行電鍍製程以降低電鑛f 層、二’ “後形成材料成本較高之例如為焊錫材料之^著 二心：=程所需時間，以透過減少焊錫材料使用量 而卜低材科成本與環保問題，且可同 成架橋現象及短路問題，俾二:二 塊尺及避免習知模板印刷技術形成導電凸 頸。寸及彳目鄰電性連接㈣距之限制及製程技術上之瓶 【實施方式】 ϋ I W㈣定料體實射'm明本發明之實施方式’ =1:之人士可由本說明書所揭示之内容輕易地瞭解 x ”他優點及功效。本發明亦可藉由其他不同的具 10 麵 1270329 體實施例加以施行或應用，本說明書中的各項細節亦可基 於不同的觀點與應用，在不择離本發明之精神下 修飾與變更。 ° 請參㈣2Α至第21^，將詳細㈣本發明之電路板 塊結構之製法較佳實施例之剖面示意圖。此處須注 思的一點是，該些圖式均為簡化之示意圖，盆僅 式說明本發明之基本架構， 1、 〜方 構成，且所顯示之構成並非以；；1=與f娜 及尺寸比例㈣，其作二= 一之數目、形狀、 為-種選擇性之數目、形狀及尺寸比例 x 〇t且其構成佈局形態可能更H #。 請參閲第2A圖至第2D岡、，士』 此更马妓4。 個電性連接百先提供表面形成有複數 接墊之電路板。如第2A圖所示，係在 表面絕緣層41上形成導命息 , 反 述電鑛金屬材料所需之電；4、首二導電層42主要作為後 數層金屬層所構成：：、v ’其可由金屬或沉積 錫-鉛等單声銅、錫、鎳、鉻、鈦、銅-鉻或 年早層或多層結構，或可使用例 有機硫聚合物等導電高八 跃承本胺或 在該導電層42上;;_刀子材料；如第2B圖所示，接著 膜或液態光阻等光阻：層43 :該阻層43可為-例如乾 用印刷、旋塗或貼人等::叫或非感光阻層’其係利 r H τ 〇寺方式形成於該導電；49矣；$ „ %、光、顯影或雷射等方 s 、，猎 有複數外露出部分導1 49目案化’以使該阻層形成 進行電_leci 之開口 430;如第2〔圖所示， 性，俾在進^==程，藉由該導電層42具導電特 又可了作為電流傳導路徑，以在該等欲電 Π 18183 1270329 鍍開口 430中電銀形成有電 電錢形成有電路板表面之導電線路二當然亦可同時 示，接著即可移除將該阻層圖不），如#扣圖所 •電層42。 ^及该阻層43所覆蓋之導 =閲第_’接著，於 一 保4層45。於本實施例中 ㈣攻 '、‘巴蝝 —方式將該絕緣保護層45塗^用/^、旋塗及貼合之任 案化製程以使該電性連接•‘、二路板表面，再藉由圖 其中’該絕緣保護層45可為例如^讀該絕緣保護層〜 藉由曝光、顯影或雷射等方式力、’’、、防卜層材料所製成，並 45形成有複數個開口 45。邑緣保護層 請參閲第㈣，於性連接塾秦 面形成—導電層46。該導電声 ^ 及其開口物表 屬材料所需之電流傳導路/ 要係作爲後續電鐘金 層金屬層所構成，或可使;例π金屬、合金或沉積數 請參閲第2G圖，接著進行電：子材 46作為電流傳導路徑，且藉 導電層 鍍區域，以於該導帝 W層46表面較大的電 且使該全屬二： 全面電鑛形成-金屬層… 孟屬層47填充於該絕緣 金屬層47表面平整。其中，該合=開口 450中以保持該 錫、銀、銅等金屬或為其合金，惟“二二材:可為錯、 田方、钔為成熟之電鍍材料且 ^ 以由，銅所構成者為較佳，但非以此為限广金屬層47 4閱…，於該金屬層47上形成—阻層48，並 18183 12 1270329 方式將該阻係利用印刷、旋塗及貼合之任一 製程以你邱二亥金屬層47表面，再藉由圖案化 阻層48之°:之该金屬層47顯露於該阻層㈤口 480，且該 位置處。# °彻係對應該電路板表面之電性連接墊440 請參閲第21圖，於哕卩日思+ μ -軸❹49^t；m4㈣形成—黏著層 鉑或1人全，…：“銅、錫、鉛、銀、錄、金、 口盃亚可以電鍍方式直接形成。 請參閲第2J圖，接著，利 式移除該阻層48。 干χΙ或物理移除等方 請參閲第2Κ圖，接著移除未為該黏 =屬層47及導電“，僅留下該黏著；4二斤= ^性連接墊440位置處之部分金屬層^及^下對^ 以於:玄電性連接墊44〇上形成導電凸塊結構。-曰， 晴參閲第2L圖，若兮教益庶 即可進行回焊製程以使得該焊錫:料完時，接著 電性連接塾440上之金屬層47外 正。4該形成於該 、曾請參閱第3A至第3〇圖，將詳細說 V電凸塊結構之製法第二實施例之剖面示—月之笔路板 請參閲第3A，首先提供一至少— 二θ。 連接墊510之電路板50。 、形成有複數電性 +請參閱第3Β圖，接著於該形成有電性連 電路板50上覆蓋一絕緣保護層55。於/ 51〇之 、、舞、施例中，係利 18183 13 1270329 ^刷'mu合之任—方式將該絕 -，藉以使該電性 開口 55〇中。 10择員路方^玄絕緣保護層55之 請參閱DC目，於該絕緣保 面形成一導電層56。爷導^ + 及八開口 550表 屬材料所需要的電流料路^。56主要係作爲後續電鑛金 爲電:透:::錢製程，該導電層56作 於該導電層56上電鐘形成—全；声大的電鑛區域 填充於該絕緣保護層之開 S 便咸金屬層57 平整。 層之開口 550中以保持該金屬層57表面 阻/5月所3£圖’於該金屬層57上形成—阻層58,該 用=膜或液態光阻。於她 -表面，再^荦之==758覆於一 於該電路板5”… 層58僅覆蓋住對應 二=面之電性連接墊51〇位置處之金屬層57。 屬声 圖’移除未為該阻層58所覆蓋之部分全 屬層57及導雷爲以，仅如斗 |刀孟 表面之電性遠驗 層58下對應於該電路板50 56。 510位置處之部分金屬層57及導電層 口月參閲弟3G圖，接菩音，丨田儿过、士 方式移除卿58，清 干 稭以於該金屬層47外露表面上> 電電鍍方式形成—黏著層59。 卜〜表面上以热 18J83 ]4 1270329 口此本發明之電路板導電凸塊纟士播制 在電路板上形成具複數開口之絶緣保1之表法，主要係 板表面之電性連接墊，接…隻曰以外路出该電路 成一導+思 …玄、吧緣保護層及開口表面y 攻v毛層，因該導電層表面夫罗& 面形 有較大的暴露表面積 ^置阻層，而提供導電層 上電鍍形成-全屬>，_ 的電鍵區域而於該導電層 再於其=Γ:連接墊部分之金屬層及導電層 /、衣曲形成一黏著層 接墊上形成導電凸塊έ k笔路板表面之電性連 區域面積過…夕 避免習知電鍍製程中電穿 屬層係=1:Γ』程因難度增加，且本發明該： 該金屬層表面平整，Α接梦^ 表面及開口中，以使 致之導電凸塊結構，俾可二：：；金屬層以形成高度-上形成阻層，而導_田白讀製程，係於導電層 口中電㈣豐置的孔形，然後於該疊置的開 τ兒鍍形成導電凸塊，因φ J間 製程難度增加及所欲電：：σ”孔形較深，使得電鍍 密戶；^έ 又品或面積小，造成製程的電浐 件電性連而影響後續製程— 而非性說明本發明之原理及其功效， 違背本發明之糾及/㈣白此項技藝之人士均可在不 此本發明之=:w，對上述實施例進術 【圖式C乾圍，應如後述之申請專利範圍所列。 18183 15 1270329 第1A圖至第11?圖係顯示習知恭 形成電導電凸塊之剖面示意圖；、电路板之電性連接墊上 笔凸塊結構之製 笔凸塊結構之製 弟Α至第2l圖為本發明之 法弟一實施例之剖面示意圖’·以及 …弟3A至第3G圖為本發明之電路板導 法第二實施例之剖面示意圖。 、The conductive layer 10a is formed into a conductive layer on the insulating protective layer and the opening table W, which is different from the conventional hole shape in which the surface shape is overlapped, and the conductive surface is formed by the conductive layer: . The electric ore is formed into a metal layer, and the removed portion is: = square, and the layer is further formed on the surface thereof; the metal layer and the conductive layer of the second connecting portion, and the electrically connected region area of the opposite surface of the conductive bump structure formed on the pad Too small, the electroplating process in the process of i-free Baizhi electric ore is difficult due to the difficulty, and the invention has the surface, and the surface of the insulating protective layer is opened, and the metal layer of the core is formed to form a height of one:俾 俾 俾 俾 俾 俾 俾 俾 俾 俾 俾 俾 俾 俾 俾 俾 俾 俾 俾 俾 俾 俾 俾 俾 俾 俾 俾 俾 俾 俾 俾 俾 俾 俾 俾 俾 俾 俾 俾 俾 俾 俾 俾 俾 俾 俾 俾 俾 俾 俾 俾 俾 俾 凸The block 'increased the difficulty of the electroplating process, resulting in the inability to control the degree of the degree, causing the board to communicate with the outside world:: _ ghost high to complete the electrical connection. The electronic component cannot be effective at the same time. On the insulating protective layer on the surface of the conductive bump junction circuit board of the circuit board of the present invention, the guide layer is sequentially formed, which is to remove part of the metal layer and cover the 'two: genus layer, In the electrical connection of the circuit board, a second:: into the (four) layer' technology, a conductive layer is formed on the insulating protective layer, the intellectual resistance layer is avoided, and then a block is formed on the insulating protective layer and the resist layer. High electricity leads to electricity _ 2 ^ The moon can be made of lower material cost, and:; material 峨 bell out of the copper metal layer, so that the shrinking process is difficult ^ ^ from the larger electric mining area to carry out the electroplating process to reduce the electric mine f The cost of forming the material after the layer and the second is higher than the cost of the solder material. For example, the time required for the process is to reduce the cost of the solder material and the environmental protection problem, and the bridge can be bridged. Phenomenon and short-circuit problem, 俾 2: two-piece ruler and avoiding the stencil printing technology to form a conductive convex neck. Inch and eye-catching electrical connection (four) distance limitation and process technology bottle [embodiment] ϋ I W (four) Body real shot 'm Ming embodiment of the invention ’ =1: The person can easily understand x ” his advantages and effects by the content disclosed in this manual. The present invention may be embodied or applied by other different embodiments of the present invention. The details of the present invention can be modified and changed without departing from the spirit and scope of the invention. ° Refer to (4) 2Α to 21^, which will be a detailed cross-sectional view of a preferred embodiment of the method for fabricating a circuit board structure of the present invention. It should be noted here that these drawings are simplified schematic diagrams, and the basins merely illustrate the basic structure of the present invention, which is composed of 1, and the composition is not shown; 1 = and f The size ratio (4), which is the number of two, the shape, the number of choices, the shape and size ratio x 〇t and its constituent layout form may be more H #. Please refer to Figure 2A to 2D Gang, Shishi. This is more horse 4. A plurality of electrical connections provide a circuit board having a plurality of pads formed on the surface. As shown in FIG. 2A, a conductive life is formed on the surface insulating layer 41, and the electric power required for the electric ore metal material is reversed. 4. The first two conductive layers 42 are mainly composed of the latter metal layers::, v 'It can be made of metal or deposited tin-lead, such as mono-copper, tin, nickel, chromium, titanium, copper-chromium or early-layer or multi-layer structure, or can be used as a conductive high-octane amine or On the conductive layer 42; _ knife material; as shown in FIG. 2B, followed by photoresist such as film or liquid photoresist: layer 43: the resist layer 43 can be - for example, dry printing, spin coating or affixing, etc. :: Called or non-photosensitive resistive layer's method of forming a r h τ 〇 temple formed on the conductive; 49 矣; $ „ %, light, development or laser, etc., hunting a plurality of exposed portions of the guide 1 49 Meshing 'to make the resist layer form an opening 430 for conducting electricity_leci; as shown in Fig. 2, the polarity is in the range of ^==, and the conductive layer 42 is electrically conductive and can be used as a current. The conductive path is formed in the electroplated silver in the plating opening 430 of the 18183 1270329 plating hole 430, and the conductive circuit formed on the surface of the circuit board is also shown. Then, the resist layer can be removed, such as #扣图图•Electrical layer 42. ^ and the layer covered by the resist layer 43 = read the first _ 'Next, Yu Yibao 4 layer 45. In this In the embodiment, (4) attacking, 'Bang—the method of coating the insulating protective layer 45 with /^, spin coating and lamination to make the electrical connection, 'the surface of the two-way board, and then borrow In the figure, the insulating protective layer 45 can be, for example, read the insulating protective layer ~ by means of exposure, development or laser, etc., and is made of a material, and 45 is formed with a plurality of openings. 45. The edge protection layer is referred to in (4), and the conductive layer 46 is formed on the 塾 塾 面 。 。 。 。 。 。 。 。 。 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电 导电The metal layer is formed or may be; for example, the π metal, the alloy or the deposition number is referred to the 2G diagram, and then the electricity is performed: the sub-material 46 is used as a current conduction path, and the conductive layer is plated to the layer. 46 The surface is larger and makes the whole two: Fully electric ore formation - metal layer... The Meng layer 47 is filled on the surface of the insulating metal layer 47 Wherein, the combination = opening 450 to maintain the tin, silver, copper and other metals or alloys thereof, but "two two materials: can be wrong, the field, the enamel is a mature plating material and ^, by the copper Preferably, the constituents are not limited to the wide metal layer 47 4 , and the resist layer 48 is formed on the metal layer 47 , and the resist is printed, spin coated and bonded by 18183 12 1270329. Either process is based on the surface of your Qiu Erhai metal layer 47, and by patterning the resist layer 48: the metal layer 47 is exposed at the resist layer (5) port 480, and at this position. # °彻 corresponds to the electrical connection pad on the surface of the board 440 Please refer to Figure 21, in the 哕卩日思 + μ - axis ❹ 49 ^ t; m4 (four) formed - adhesive layer platinum or 1 person full, ...: "Copper , tin, lead, silver, gold, gold, and cup can be formed directly by plating. Please refer to Figure 2J, and then remove the barrier layer 48. For dry or physical removal, please refer to 2 Κ , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , A conductive bump structure is formed on the connection pads 44. - 曰, 晴 Refer to Figure 2L, if you can teach the reflow process so that the solder: when finished, then the metal layer 47 on the electrical connection 440 is positive. 4, which is formed in the above, please refer to the 3A to 3rd drawings, and the second embodiment of the method for manufacturing the V-electrode bump structure will be described in detail. Please refer to the 3A, first provide at least one — Two θ. The circuit board 50 of the pad 510 is connected. A plurality of electrical properties are formed. Please refer to FIG. 3, and then an insulating protective layer 55 is overlaid on the electrically formed circuit board 50. In / 51 〇 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , 10Select the way to the side of the insulating layer 55. Please refer to the DC target to form a conductive layer 56 on the insulating surface. The main guide ^ + and eight openings 550 are the current materials required for the material ^. 56 is mainly used as a follow-up electric gold for electricity: through::: money process, the conductive layer 56 is formed on the conductive layer 56 on the electric clock - full; the sound of the electric mine area is filled in the opening of the insulating protective layer The salty metal layer 57 is flat. The opening 550 of the layer is formed on the metal layer 57 to maintain the surface resist of the metal layer 57. The resist layer 58 is formed by a film or a liquid photoresist. On her-surface, then ^=758 is overlaid on the circuit board 5"... The layer 58 covers only the metal layer 57 at the position of the electrical connection pad 51 of the corresponding two-face. Except for the portion of the entire layer 57 and the lightning guide that is not covered by the resist layer 58, only the electrical remote layer 58 of the surface of the bucket is corresponding to the circuit board 50 56. Part of the metal at the position of 510 Layer 57 and the conductive layer mouth month refer to the brother 3G map, pick up the Puyin, Putian children pass, the way to remove the Qing 58, clear the straw on the exposed surface of the metal layer 47 > Electroplating form - adhesive layer 59. Bu ~ surface on the heat 18J83 ] 4 1270329 mouth of the present invention, the circuit board conductive bumps gentleman broadcast on the circuit board to form a plurality of openings of the insulation 1 method, the main board surface electrical connection Pad, connect... only out of the circuit to form a guide + think... Xuan, the edge of the protective layer and the open surface y attack v layer, because the surface of the conductive layer has a large exposed surface area a resist layer, and providing a conductive layer on the conductive layer to form a full-key >, _ key area and the conductive layer and then = Γ: connection pad The metal layer and the conductive layer/, the clothing layer form an adhesive layer to form a conductive bump έ k the electrical connection area of the surface of the circuit board has passed the eve of the electroplating process to avoid the electro-penetration layer system=1:难度 程 因 因 因 因 程 程 程 程 程 程 程 程 程 程 程 程 程 程 程 程 程 程 程 程 程 程 程 程 程 程 程 程 程 程 程 程 程 程 程 程 程 程 程 该 该 该 该 该 该 该The resist layer, and the lead-white read process, is in the shape of the hole in the conductive layer (4), and then is plated on the stacked open-tau to form conductive bumps, because the difficulty of the process between φ J increases and the desired power The ::σ" hole shape is deeper, which makes the plating of the household; the product or the area is small, which causes the electrical connection of the process to be electrically connected and affects the subsequent process - instead of the principle and function of the invention, it is against this Anyone who has the skill of the invention/(4) who is in the art of this invention can use the above-mentioned embodiment instead of the invention of the invention: [Fig. C] should be listed in the patent application scope described later. 18183 15 1270329 Fig. 1A to Fig. 11 are schematic cross-sectional views showing the formation of electrically conductive bumps by the singer; and the structure of the pen bump structure of the pen bump structure on the electrical connection pad of the circuit board to the second picture is BRIEF DESCRIPTION OF THE DRAWINGS FIG. 3 is a cross-sectional view showing a second embodiment of a circuit board guiding method of the present invention. ,
【主要元件符號說明】 10 電路板 100 電性連接墊 110 、 130 開孔 11 防焊層 12 、 46 、 56 導電層 13 阻層 14 導電凸塊 15 金屬保護層 41 絕緣層 42 導電層 43 、 48 、 58 随層 430、450、480、550 開〇 45 > 55 绝緣保護層 440 、 510 電性連接墊 47、57 金屬層 49、59 令占著層 50 電路板 18183 16[Main component symbol description] 10 Circuit board 100 Electrical connection pads 110, 130 Openings 11 Solder mask 12, 46, 56 Conductive layer 13 Resistive layer 14 Conductive bump 15 Metal protective layer 41 Insulating layer 42 Conductive layer 43, 48 , 58 with layer 430, 450, 480, 550 opening 45 > 55 insulating protective layer 440, 510 electrical connection pads 47, 57 metal layer 49, 59 to occupy the layer 50 circuit board 18183 16