TW201021136A - Method for fabricating conductive bump and circuit board structure with the same - Google Patents
Method for fabricating conductive bump and circuit board structure with the same Download PDFInfo
- Publication number
- TW201021136A TW201021136A TW97144555A TW97144555A TW201021136A TW 201021136 A TW201021136 A TW 201021136A TW 97144555 A TW97144555 A TW 97144555A TW 97144555 A TW97144555 A TW 97144555A TW 201021136 A TW201021136 A TW 201021136A
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- TW
- Taiwan
- Prior art keywords
- solder
- layer
- circuit board
- thick metal
- solder resist
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 53
- 239000010410 layer Substances 0.000 claims abstract description 242
- 229910000679 solder Inorganic materials 0.000 claims abstract description 223
- 229910052751 metal Inorganic materials 0.000 claims abstract description 106
- 239000002184 metal Substances 0.000 claims abstract description 106
- 239000011241 protective layer Substances 0.000 claims abstract description 47
- 238000007772 electroless plating Methods 0.000 claims abstract description 11
- 238000007639 printing Methods 0.000 claims abstract description 6
- 238000004519 manufacturing process Methods 0.000 claims description 33
- 239000000463 material Substances 0.000 claims description 29
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 13
- 229910052802 copper Inorganic materials 0.000 claims description 13
- 239000010949 copper Substances 0.000 claims description 13
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 12
- 239000010931 gold Substances 0.000 claims description 12
- 229910052737 gold Inorganic materials 0.000 claims description 11
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 10
- 239000011135 tin Substances 0.000 claims description 10
- 229910052718 tin Inorganic materials 0.000 claims description 10
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 9
- 239000004332 silver Substances 0.000 claims description 9
- 229910052709 silver Inorganic materials 0.000 claims description 8
- 239000003245 coal Substances 0.000 claims 1
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- 229910052732 germanium Inorganic materials 0.000 claims 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims 1
- 238000007747 plating Methods 0.000 abstract description 3
- 239000011295 pitch Substances 0.000 description 12
- 238000010586 diagram Methods 0.000 description 8
- 235000012431 wafers Nutrition 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000003638 chemical reducing agent Substances 0.000 description 3
- 238000007650 screen-printing Methods 0.000 description 3
- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical compound [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 description 2
- 229910021645 metal ion Inorganic materials 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 229910001174 tin-lead alloy Inorganic materials 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 229910001316 Ag alloy Inorganic materials 0.000 description 1
- 229910001020 Au alloy Inorganic materials 0.000 description 1
- 244000241257 Cucumis melo Species 0.000 description 1
- 235000015510 Cucumis melo subsp melo Nutrition 0.000 description 1
- 241000196324 Embryophyta Species 0.000 description 1
- 235000014676 Phragmites communis Nutrition 0.000 description 1
- 244000007853 Sarothamnus scoparius Species 0.000 description 1
- 229910000971 Silver steel Inorganic materials 0.000 description 1
- 229910001128 Sn alloy Inorganic materials 0.000 description 1
- FJJCIZWZNKZHII-UHFFFAOYSA-N [4,6-bis(cyanoamino)-1,3,5-triazin-2-yl]cyanamide Chemical compound N#CNC1=NC(NC#N)=NC(NC#N)=N1 FJJCIZWZNKZHII-UHFFFAOYSA-N 0.000 description 1
- QCEUXSAXTBNJGO-UHFFFAOYSA-N [Ag].[Sn] Chemical compound [Ag].[Sn] QCEUXSAXTBNJGO-UHFFFAOYSA-N 0.000 description 1
- PQIJHIWFHSVPMH-UHFFFAOYSA-N [Cu].[Ag].[Sn] Chemical compound [Cu].[Ag].[Sn] PQIJHIWFHSVPMH-UHFFFAOYSA-N 0.000 description 1
- 230000001680 brushing effect Effects 0.000 description 1
- 238000005234 chemical deposition Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 210000003298 dental enamel Anatomy 0.000 description 1
- 230000001627 detrimental effect Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 244000144977 poultry Species 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 210000002784 stomach Anatomy 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 229910000969 tin-silver-copper Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
Description
201021136 ^9495twf.doc/n 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種電路板結構（circuit board structure )，且特別是有關於一種具有導電凸塊（conductive bump)的電路板結構以及此導電凸塊的製造方法。 【先前技術】 覆晶式（flip chip)封裝是晶片與電路板封裝的一種 方式。電路板上具有多個接墊， ’且雷路妬·5Γ菇i抑要ΜTECHNOLOGICAL FIELD The present invention relates to a circuit board structure, and more particularly to a circuit having a conductive bump. The board structure and the method of manufacturing the conductive bump. [Prior Art] A flip chip package is one way of wafer and circuit board packaging. There are multiple pads on the board, and 'Lei Lu妒·5Γ菇i抑
近年來’隨著電子技術的日新月異，以及高科技電子 產業的相繼問世’使得更人性化、功能更佳的電子產品不 斷地推陳出新，並朝向輕、薄、短、小的趨勢邁進。在此 趨勢之下，由於電路板具有佈線細密、組裝緊湊及性能良 =等優點，因此電路板便成為承載多個電子元件（例如： 晶片）以及使這㈣子元倾此·連接駐魏介之一。 z9495twf.doc/n 201021136 14配置於電路板10的表面12上。防焊層16覆蓋電路板 10的表面12’並具有多個焊罩定義型（s〇lderMaskDefmed， SMD)開口 17 (圖1中僅示意地繪是二個），其中這些開 口 17分別暴露出這些接墊14。這些焊料凸塊18 (圖i中 僅示意地繪是二個）分別覆蓋於這些接墊14上且分別突出 於這些開口 17外。 在後績的製程中’是以迴焊的方式使電路板結構1〇A 與晶片（未繪示）藉由配置於兩者之間的這些焊料凸塊18 電性與結構性連接。。此外，防焊層16的開口 17在微間 距的這些接塾14上方的孔徑縮小，較開〇 17的縱橫比 增加，更不利於印刷或植入大尺寸的焊料凸塊18。同時， 當在這些接墊14上配置大尺寸的焊料凸塊18並與晶片以 迴焊的方式接合時，這些焊料凸塊18會因迴焊受熱而呈現 熔融狀態，由於這些接t 14是以微間距排列於電路板1〇 的表面上，因此容易導致迴桿過程中呈熔融狀態的焊料凸 塊18發生橋接（如圖！之？處）現象及短路問題，而無 Φ 法提供微間距之電性連接結構。 ·、 . _ · 【發明内容】 本發明提供一種導電凸塊的製造方法，其利用無電雷 上形成厚金屬層，來相對降低防焊層之開口 θ、，，,.秩比（開口沬度/開口孔徑的比值），可以避免於迴焊 谭料時發生焊料橋接短路的現象，進而可提高生產良率。 本發明提供-種具有導電凸塊的電路板結構，其藉由 ^9495twf.doc/n 201021136 接墊上之厚金屬層的高度， 横比，可喊少焊料的對降低防焊層之開口的縱 發—種導電凸塊的製造方法。首先，提供-甩路板。電路板具有—表 兀扠仏 列的接塾。接著，形成 ^配置有多個間距排 表面且具有多個開σ，知日二電路板上。防焊層覆蓋 塾。接著，進行—盈雷:口》別暴露出這些接 ψ . …、、电鍍衣程，以於這些接墊的表面分In recent years, with the rapid development of electronic technology and the advent of the high-tech electronics industry, electronic products with more humanization and better functions have been continuously introduced, and they are moving toward a trend of light, thin, short and small. Under this trend, because the circuit board has the advantages of fine wiring, compact assembly and good performance, the circuit board will be used to carry a plurality of electronic components (for example, a wafer) and to make the (four) sub-element . The z9495twf.doc/n 201021136 14 is disposed on the surface 12 of the circuit board 10. The solder mask layer 16 covers the surface 12' of the circuit board 10 and has a plurality of solder mask definition type (SMD) openings 17 (only two are schematically shown in Fig. 1), wherein the openings 17 respectively expose these Pad 14. These solder bumps 18 (only two of which are schematically shown in Fig. i) cover the pads 14 and protrude outside the openings 17, respectively. In the process of the subsequent performance, the circuit board structure 1A and the wafer (not shown) are electrically and structurally connected by the solder bumps 18 disposed therebetween. . In addition, the opening 17 of the solder resist layer 16 has a smaller aperture above the micro-pitch contacts 14, which is greater than the aspect ratio of the opening 17, which is more detrimental to printing or implanting the large-sized solder bumps 18. Meanwhile, when the large-sized solder bumps 18 are disposed on the pads 14 and are soldered to the wafers, the solder bumps 18 are heated by the reflow soldering, since these connections are The micro-pitch is arranged on the surface of the circuit board 1 ,, so that it is easy to cause the solder bump 18 in the molten state during the returning process to be bridged (as shown in the figure) and the short-circuit problem, and the Φ-free method provides the micro-pitch. Electrical connection structure. The invention provides a method for manufacturing a conductive bump, which uses a non-electrical lightning to form a thick metal layer to relatively reduce the opening θ,,, and the ratio of the opening of the solder resist layer (opening degree) / The ratio of the aperture diameter) can avoid the phenomenon of solder bridging short circuit when reflowing the tan material, thereby improving the production yield. The invention provides a circuit board structure with conductive bumps, which can reduce the verticality of the opening of the solder resist layer by the height of the thick metal layer on the pad of the ^9495twf.doc/n 201021136. A method of manufacturing a conductive bump. First, provide - the circuit board. The board has an interface that is in the form of a fork. Next, a plurality of pitch rows are formed and have a plurality of open σ, which are known on the circuit board. The solder mask covers the crucible. Then, carry out - Ying Lei: mouth, do not expose these joints. ..., electroplating process, to the surface of these pads
，其中厚金屬層的厚度大於4微米或防 於厚金ί層上。朴層的純，驗形成—保護層 在本發明之-實施例中，上述之製造方法再以植球或 ρ刷方式形成多個焊料凸塊於每一保護層上，其中每一焊 料凸塊覆蓋每一厚金屬層且突出於每一開口外，再迴焊這 些焊料凸塊，致使焊料熔融而凝聚。 在本發明之一實施例中，上述之厚金屬層的材質包括 化銅。 在本發明之一實施例中，上述之以植球或印刷方式形 成這些焊料凸塊時’更包括進行一焊球迴焊及壓合製程， 以將這些焊料凸塊壓合成硬幣狀（coin)並覆蓋於厚金屬 層上。 在本發明之一實施例中，上述之保護層的材質包括化 錫、化金或化銀。 在本發明之一實施例中，上述之防焊層的這些開口為 焊罩定義型（Solder Mask Defined, SMD)開口，且這些開 z9495twf_doc/n 201021136 口所暴露出的這些接墊為洋罩定義型接墊。 本發明提出一種導電凸塊的製造方法。首先，提供一 载電路板具有—表面’且表面上配置有多個間距排 ==著;進行一無電電鑛製程，以於這些接塾的 f面刀，成:厚金屬層。形成至少—防焊層於電路板 。防桿層覆i電路板的表面且厚金制突丨於防焊層之 外，其中厚金屬層為厚度大於防焊層且小於 ^ 倍的柱狀凸塊。雜，形成—保護層於厚金屬;ΪΙ 化銅在本發私—實施财，上叙厚金屬相材質包括 括無實施财，上叙戦倾層的方法包 燁上例中，上述之防谭層包括-第-防 /隨形成防焊層的步驟，首先，形成 面::路板上，其中第一防焊層覆蓋電路板的表 成第二防焊層於第一防焊層上，其中第二防 焊層覆蓋第一防焊層。 層 縣^之—實_巾，上叙形成第—防焊層於電 一射’包括進行一平坦化製程’對第一防焊層照射 :射先束’以移除局部與厚金屬層相連接處的第一防焊 锡 =:::實施例中’上述之保護層的材質包括化 本明提出-種具有導電凸塊的電路板結構，其包括 201021136 w z9495twf.doc/n —電路板、一f；t焊詹、一厚金屬層以及一保護層。電路板 具有一表面與多個間距排列的接墊。這些接墊配置於表面 上。防焊層配置於電路板上且覆蓋表面。防焊層具有多個 開口，且這些開口分別暴露出這些接墊。厚金屬層分別配 置於這些接墊上。厚金屬層的厚度大於4微米或防焊層高 度的1/5且小於防焊層的高度，又保護層分別覆蓋這些厚 金屬層。Where the thickness of the thick metal layer is greater than 4 microns or on the thick gold layer. In the embodiment of the present invention, the above manufacturing method further forms a plurality of solder bumps on each of the protective layers by ball bonding or ρ brushing, wherein each solder bump Each thick metal layer is covered and protrudes beyond each opening, and these solder bumps are reflowed, causing the solder to melt and coalesce. In an embodiment of the invention, the material of the thick metal layer comprises copper. In an embodiment of the invention, when the solder bumps are formed by ball or printing, the method further includes performing a solder ball reflow and pressing process to press the solder bumps into a coin. And covered on a thick metal layer. In an embodiment of the invention, the material of the protective layer comprises tin, gold or silver. In an embodiment of the invention, the openings of the solder resist layer are formed by a Solder Mask Defined (SMD) opening, and the pads exposed by the openings of the z9495twf_doc/n 201021136 are defined as a mask. Type pads. The invention provides a method of manufacturing a conductive bump. First, a carrier board is provided with a surface and a plurality of pitch rows are arranged on the surface. An electroless ore processing is performed to form a thick metal layer. Form at least - a solder mask on the board. The anti-bar layer covers the surface of the i-type circuit board and the thick gold is protruded outside the solder resist layer, wherein the thick metal layer is a columnar bump having a thickness greater than the solder resist layer and less than ^ times. Miscellaneous, forming - protective layer in thick metal; copper in the private hair - implementation of wealth, the above-mentioned thick metal phase material includes no implementation of wealth, the method of the above-mentioned sloping layer, in the above example, the above-mentioned anti-tan The layer includes a first-prevention/step-forming step of forming a solder resist layer, firstly, forming a surface:: a road board, wherein the first solder resist layer covers the surface of the circuit board and forms a second solder resist layer on the first solder resist layer, The second solder mask covers the first solder mask. The layer of the county - the real _ towel, the upper formation of the first - the solder mask is electrically generated 'including a flattening process 'the first solder mask layer: the first beam 'to remove the local and thick metal layer The first solder resist at the joint =::: In the embodiment, the material of the protective layer mentioned above includes a circuit board structure with conductive bumps, which includes 201021136 w z9495twf.doc/n - a circuit board, A f; t solder, a thick metal layer and a protective layer. The board has a pad with a surface and a plurality of pitches. These pads are placed on the surface. The solder resist layer is disposed on the circuit board and covers the surface. The solder resist layer has a plurality of openings, and the openings expose the pads, respectively. Thick metal layers are placed on these pads, respectively. The thickness of the thick metal layer is greater than 4 microns or 1/5 of the height of the solder mask and less than the height of the solder mask, and the protective layer covers the thick metal layers, respectively.
在本發明之一實施例中，多個焊料凸塊分別覆蓋每一 保護層且突出於每一開口外。 在本發明之一實施例中，上述之厚金屬層的材質包括 化銅。 在本發明之一實施例中，上述之保護層的材質包括化 锡、化金或化銀。 在本發明之一實施例中，上述之防焊層的這些開口為 焊罩定義賴π ’且這些開π所暴露出的這些接塾為焊罩 定義型接墊。 —本發明提出-種具有導電&塊的電路板結構，其包括 :電路板、—防焊層、—厚金屬層、—保護層。電路板具 表面與多個間距制的接墊。這些接塾配置於表面 。防焊層配置於板上且覆蓋表面。防焊層具有多個 ^:i ^些開口分別暴露出這些接墊。厚金屬層分別配 芦為上。厚金屬層突出於防焊層之外，且厚金屬 切畴層且掃卩辑層高^倍陳狀凸塊。 保遽層復盍於厚金屬層所突出的表面上。 201021136 29495twf.doc/n 在本發明之一實施例中，上述之厚金屬層的材質包括 化銅。 在本發明之一實施例中，上述之保護層的材質包括化 錫、化金或化銀。 在本發明之一實施例中’上述之防焊層的這些開口為 非焊罩定義型（Non-Solder Mask Defined, NSMD )開口， 且這些開口所暴露出的這些接墊為非焊罩定義型接墊。 综上所述，由於本發明之導電凸塊的製造方法因可採 用無電電鍍製程、氣相沉積法、濺鍍法，以於接墊的表面 上形成厚金屬層’故可相對降低防焊層之開口的縱橫比（開 口深度/開口孔徑的比值），因縱橫比較低，所以可減少焊 料的使用量，因而可避免於迴焊焊料時焊料發生橋接短路 的現象，進而提高導電凸塊的製程良率及電路板結構的可 靠度。 為讓本發明之上述和其他目的、特徵和優點能更明顯 易懂’下文特舉實施例’並配合所附圖式作詳細說明如下。 【實施方式】 圖2為本發明之一實施例之一種具有導電凸塊的電路 板結構的示意圖。請參考圖2 ’在本實施例中，具有導電 凸塊的電路板結構100A包括一電路板1〇〇、一防焊層 120A、一厚金屬層130A以及、一保護層132以及多個焊 料凸塊140。 詳細而言，電路板1〇〇具有一表面1〇2與多個間距排 201021136 29495twf.doc/n 列的接墊110 (圖2中僅示意地緣示二個），其中這些接 墊110配置於電路板100的表面102上，且任兩相鄰之這 些接墊110的間距介於50微米（#m)至150微米（vm) 之間。在本實施例中，這些接墊110的材質包括銅，電路 板 1 〇〇 例如是一印刷電路板（printed Circuit Board，PCB ) 或一載板（ICCarrier)。 防焊層120A配置於電路板1〇〇上且覆蓋電路板ι〇〇 ❹ 的表面1〇2 ’其中防焊層120A具有多個開口 122A (圖2 中僅示意地繪示二個），且這些開口 122A分別暴露出這 些接墊lio。在此必須說明的是，依據防焊層12〇A之這些 開口 122A所分別暴露出這些接墊n〇的面積大小，可分 為焊罩定義型開口及非焊罩定義型開口兩種型態。在本實 妩例中，防焊層120A的這些開口 122A為烊罩定義型開 口，且這些開口 122A所分別暴露出的這些接墊n〇為焊 罩定義型接墊。 ’ 厚金屬層130A分別配置於這些接墊11〇上，且厚金 屬層130A的厚度大於4微米（Am)或防焊層12〇A的高 度的1/5且小於防焊層120A的高度，其令厚金屬層13〇a 例如是無電電鍍法所形成的化銅。在本實施例中，厚金屬 層130A的厚度設計與防焊層12〇A的高度具有一比例關 係。以一般防焊層12〇a的高度（約為5微米〜2〇微米） 為例，當防焊層mA的高度為2〇微米Um)時，厚金 屬層130A的厚度為防焊層12〇A的高度的1/5或更高，也 就是說，厚金屬層130A的厚度例如大於4微米（㈣）， 11In one embodiment of the invention, a plurality of solder bumps cover each of the protective layers and protrude beyond each of the openings. In an embodiment of the invention, the material of the thick metal layer comprises copper. In an embodiment of the invention, the material of the protective layer comprises tin, gold or silver. In one embodiment of the invention, the openings of the solder resist layer described above are defined by the solder mask and the contacts exposed by the openings π are solder mask defining pads. - The invention proposes a circuit board structure having a conductive & block comprising: a circuit board, a solder mask, a thick metal layer, a protective layer. The board has a pad with a surface and a plurality of pitches. These ports are placed on the surface. The solder resist layer is disposed on the board and covers the surface. The solder mask has a plurality of ^: i ^ openings that expose the pads, respectively. The thick metal layer is respectively equipped with a reed. The thick metal layer protrudes beyond the solder resist layer, and the thick metal cuts the domain layer and the broom layer is high. The protective layer is entangled on the surface of the thick metal layer. 201021136 29495twf.doc/n In an embodiment of the invention, the material of the thick metal layer comprises copper. In an embodiment of the invention, the material of the protective layer comprises tin, gold or silver. In an embodiment of the invention, the openings of the solder resist layer are non-solder mask defined (NSMD) openings, and the pads exposed by the openings are non-weld mask-defined. Pads. In summary, since the method for manufacturing the conductive bump of the present invention can adopt an electroless plating process, a vapor deposition method, or a sputtering method to form a thick metal layer on the surface of the pad, the solder resist layer can be relatively reduced. The aspect ratio of the opening (the ratio of the opening depth to the opening aperture) is low in the aspect ratio, so that the amount of solder used can be reduced, thereby avoiding the phenomenon of bridging short-circuiting of the solder during solder reflow, thereby improving the process of the conductive bumps. Yield and reliability of the board structure. The above and other objects, features and advantages of the present invention will become more <RTIgt; Embodiments Fig. 2 is a schematic view showing a circuit board structure having conductive bumps according to an embodiment of the present invention. Please refer to FIG. 2 'In this embodiment, the circuit board structure 100A having conductive bumps includes a circuit board 1 , a solder resist layer 120A , a thick metal layer 130A , a protective layer 132 , and a plurality of solder bumps . Block 140. In detail, the circuit board 1 has a surface 1〇2 and a plurality of pads 110 of the 201021136 29495 twf.doc/n row (only two are schematically shown in FIG. 2), wherein the pads 110 are disposed on The surface 102 of the circuit board 100, and the spacing of any two adjacent pads 110 is between 50 micrometers (#m) and 150 micrometers (vm). In this embodiment, the material of the pads 110 includes copper, and the circuit board 1 is, for example, a printed circuit board (PCB) or a carrier (ICCarrier). The solder resist layer 120A is disposed on the circuit board 1 且 and covers the surface 1 〇 2 ′ of the circuit board ι 其中 where the solder resist layer 120A has a plurality of openings 122A (only two are schematically shown in FIG. 2 ), and These openings 122A expose these pads lio, respectively. It should be noted that, according to the opening 122A of the solder resist layer 12A, the area of the pads n〇 can be divided into two types: the solder mask defined opening and the non-welded cover defined opening. . In the present embodiment, the openings 122A of the solder resist layer 120A are shroud-defining openings, and the pads n〇 exposed by the openings 122A are respectively solder mask-defined pads. The thick metal layers 130A are respectively disposed on the pads 11A, and the thickness of the thick metal layer 130A is greater than 1 micrometer (Am) or 1/5 of the height of the solder resist layer 12A and less than the height of the solder resist layer 120A. The thick metal layer 13〇a is, for example, copper formed by electroless plating. In the present embodiment, the thickness design of the thick metal layer 130A has a proportional relationship with the height of the solder resist layer 12A. Taking the height of the general solder resist layer 12〇a (about 5 μm to 2 μm) as an example, when the height of the solder resist layer mA is 2 μm μm, the thickness of the thick metal layer 130A is the solder resist layer 12〇. The height of A is 1/5 or higher, that is, the thickness of the thick metal layer 130A is, for example, greater than 4 μm ((4)), 11
20 願J36-twfM 且厚金屬層13GA的厚度上限小於防焊層丨觀的高度。 些焊料凸塊14G (圖2中僅示意地緣示二個）分別 覆盍每-保護層132 ’且這些焊抖凸塊14〇分別突出於每 開σ mA外。在本霄施例中，這些谭料凸塊⑽的材 貝包括錫鉛合金或錫銀鋼合金（無鉛合金）。保護層132 覆蓋厚金屬層130A的頂部，其中保護層16〇的材質包括 化錫、化金或化銀。 _ 由^這些焊料凸塊14〇是分別位於每一保護層132 上丄而每一厚金屬層13〇A的厚度可相對降低防烊層 之母開口 122A的縱橫比（開口深度/開口孔徑的比值）， 也就疋巩，厚金屬層13〇A可降低這些焊料凸塊14〇填入 這些開口 122A的深度，尤其是，高縱橫比的開口 122A若 無厚金屬層130A降低其縱橫比，習知焊料不易藉由網版 印刷或植球等方式充分地填入於開口底部角落中，且焊料 填入於開口的量明顯不足時，容易在其底部（焊料凸塊18 與接墊14的接合處）產生空孔或缺陷，使得焊料凸塊18 Φ 的可靠度降低。 簡言之’本實施例之具有導電凸塊之電路板結構 100A，其厚金屬層13〇A的厚度增加（較佳為防焊層i2〇a 的高度1/5或更高），可相對降低防焊層12〇A之這些開口 mA的縱橫比。此外，當這些焊料凸塊140覆蓋每一保護 層132 %’厚金屬層i3〇A的厚度可降低這些焊料凸塊“ο 填入這些開口 122A的深度，方便使用者以印刷或植球方 式快速形成具有預定高度的焊料凸塊14〇,即可構成微間 12 201021136·— 足巨之電性連接結構。因此，本實施例可提高這些焊料凸壞 140的可靠度。 、 以上僅介紹本發明之具有導電凸塊之電路板結構 A、’並未介紹本發明之導電凸塊的製作方法。對此，以 下^ 乂圖,2中的具有導電凸塊之電路板結構100A作為舉 例a兄明’亚配合圖3A至圖3£對本發明的導電凸塊的製作 方法進行詳細的說明。 立圖3A至圖3E為圖2之導電凸塊的製造方法的流程示 思圖。睛先參考圖3A’依照本實施例的導電凸塊的製作方 法^首先，提供—電路板100。電路板100具有一表面102, 且私路板100的表面102上配置有多個間距排列的接墊 110 (圖3A中僅示意地緣示二個），其中任兩相鄰之這些 接塾110的間距介於5〇微米Um)至150微米Um) 之間。 5月參考圖3B’接著’形成一防焊層120A於電路板1〇〇 上二詳細而言，防焊層120A覆蓋電路板10〇的表面1〇2 ❹ 與故些接墊110的一部份，且防焊層120A具有多個開口 122A (圖3B中僅示意地繪示二個），其中這些開口 122A 分別暴露出這些接墊110。依據防焊層12〇A之這些開口 122A所分別暴露出這些接墊11G的面積大小，可分為焊罩 定義型開口及非焊罩定義型開口兩種型態。在本實施例 中’ P方焊層12GA的這些開卩122A為焊罩錢型開口，且 這些開口 122A所分別暴露出的這些接墊11〇為焊罩定義 型接墊。 13 201021136 z9495twf.doc/n 201021136 z9495twf.doc/n20 The upper limit of the thickness of the J36-twfM and thick metal layer 13GA is smaller than the height of the solder mask. The solder bumps 14G (only two of which are shown schematically in Fig. 2) cover each of the protective layers 132' and the solder bumps 14'' respectively protrude beyond each σ mA. In the present embodiment, the material of these tan bumps (10) includes tin-lead alloy or tin-silver steel alloy (lead-free alloy). The protective layer 132 covers the top of the thick metal layer 130A, wherein the material of the protective layer 16A includes tin, gold or silver. _ These solder bumps 14 〇 are respectively located on each of the protective layers 132 and the thickness of each thick metal layer 13 〇 A can relatively reduce the aspect ratio (opening depth / opening aperture of the mother opening 122A of the tamper resistant layer) The ratio), that is, the thick metal layer 13A reduces the depth at which the solder bumps 14 are filled into the openings 122A. In particular, the high aspect ratio opening 122A reduces the aspect ratio thereof without the thick metal layer 130A. Conventional solders are not easily filled in the bottom corners of the opening by screen printing or ball implantation, and when the amount of solder filled in the openings is significantly insufficient, it is easy to be at the bottom thereof (solder bumps 18 and pads 14) The joints) create voids or defects that reduce the reliability of the solder bumps 18 Φ. In short, the circuit board structure 100A having conductive bumps of the present embodiment has an increased thickness of the thick metal layer 13A (preferably the height of the solder resist layer i2〇a is 1/5 or higher), which is relatively The aspect ratio of the opening mA of the solder resist layer 12A is lowered. In addition, when these solder bumps 140 cover the thickness of each protective layer 132% thick metal layer i3〇A, these solder bumps can be reduced. “The depth of these openings 122A is filled, which is convenient for the user to print or plant the ball quickly. The solder bumps 14A having a predetermined height are formed to form the electrical connection structure of the micro-interval 12 201021136·—the present embodiment can improve the reliability of the solder bumps 140. The circuit board structure A with the conductive bumps does not describe the manufacturing method of the conductive bump of the present invention. For this, the circuit board structure 100A with conductive bumps in the following is shown as an example. FIG. 3A to FIG. 3E are schematic diagrams of the manufacturing method of the conductive bump of FIG. 2. FIG. 3A to FIG. 3E are schematic diagrams of the manufacturing method of the conductive bump of FIG. 'Method of Fabricating Conductive Bumps According to the Present Embodiment ^ First, a circuit board 100 is provided. The circuit board 100 has a surface 102, and the surface 102 of the private board 100 is provided with a plurality of pads 110 arranged in a pitch (Fig. Only indicated in 3A The edge is shown in two), wherein the spacing between any two adjacent ones of the interfaces 110 is between 5 μm Um and 150 μm Um. May to refer to FIG. 3B 'then' to form a solder resist layer 120A on the circuit board 1) In detail, the solder resist layer 120A covers a surface 1〇2 of the circuit board 10A and a portion of the pads 110, and the solder resist layer 120A has a plurality of openings 122A (only in FIG. 3B) Two of the openings 122A are respectively exposed, and the openings 122A respectively expose the pads 110. The openings 122A of the solder resist layer 12A respectively expose the area of the pads 11G, and can be classified into a solder mask definition type. There are two types of openings and non-welded cover-defined openings. In the present embodiment, the openings 122A of the 'P square solder layer 12GA are solder mask money openings, and the pads 11A are respectively exposed by the openings 122A. Define the type of pad for the solder mask. 13 201021136 z9495twf.doc/n 201021136 z9495twf.doc/n
睛參考圖3c ’接著，進行—無·^鍍製程，以於這 些接塾m的表面分別形成一厚金屬層13〇a，其中厚 層130A的厚度約為防焊層職高度的1/5或更高。詳細 =言’本實施例所進行之無電電鑛製程，是利用所添加的 還原劑使金屬離子縣成金屬，並沉積在這些接墊110的 表面’即構成所謂的厚金屬層130A，其中厚金屬層13〇a 的材質包括化銅。簡言之’本實施例之厚金屬層13〇a是 採用化學沈積的方式形成於這些接墊11〇的表面上。Referring to Fig. 3c', a plating process is performed to form a thick metal layer 13〇a on the surface of the interface m, wherein the thickness of the thick layer 130A is about 1/5 of the height of the solder resist layer. Or higher. In detail, the electroless ore process performed in the present embodiment is to use a reducing agent to form a metal ion into a metal and deposit it on the surface of the pads 110 to form a so-called thick metal layer 130A, wherein the thick The material of the metal layer 13〇a includes copper. Briefly, the thick metal layer 13A of this embodiment is formed on the surface of these pads 11 by chemical deposition.
請參考圖犯’接著’形成一保護層m於厚金屬層 13 0 A上’亚以植球或印刷方式外加迴焊以形成多個烊料凸 塊140於每一保護層132上，其中每一焊料凸塊14〇覆蓋 每一保濩層132且突出於每一開口 122人外。請參考圖3e， 接著，當以植球或印刷方式形成這些焊料凸塊14〇時，更 可進行一焊球壓合製程，以將這些焊料凸塊14〇更緊密地 壓&於保羞層132上，以形成一硬幣狀（c〇in)之焊料凸 塊140’並使這些焊料凸塊14〇分別填滿防焊層12〇八的這 些開口 122A，以做為後續電路板結構1〇〇A與晶片（未繪 示）之間的電性連接結構。θ 由於這些焊料凸塊140是位於厚金屬層13〇A上，且 厚金屬層130A的厚度例如大於4微米，約為防焊層12〇A 高度的1/5或更高，降低這些悍料凸塊14〇填入這些開口 122A的深度，方便使用者以印刷或植球方式快速形成具有 預定高度的焊料凸塊，故本實施例可於微間距排列之這些 接塾110上構成電性連接結構。在本實施例中，這些焊料 14 20102113629495twf_ 凸塊140的材質包括錫鉛合金或錫銀銅合金。至此，已於 電路板結構100A上完成導電凸塊的製作。 簡言之，由於實施例之導電凸塊的製造方法是採用無 電電鍍製程，不需使用高污染且成本高的電鍵製程，以於 接墊no的表面上形成厚金屬層130A，其中厚金屬層13〇A ^厚度增加，故可相對降低防焊層12〇A之開口 122A的縱 檢比（開口深度/開口孔徑的比值）。此外，在線路板結構 鲁 100A 一整體預定高度的情況下’由於焊料凸塊140是覆蓋 於厚金屬層130A上’因此可藉由厚金屬層13〇八的厚度增 加來減少焊料凸塊140的使用量，以及可避免習知於迴焊 焊，18時呈熔融狀態的焊料凸塊n8發生橋接現象及短路 問題（請參考圖1)，進而提高導電凸塊的製程良率及電 路板結構100A的可靠度。 圖4A為本發明之另一實施例之一種具有導電凸塊的 電路板結構的示意圖。請參考圖4A，在本實施例中，具有 導電凸塊的電路板結構100B包括一電路板1〇〇、一防焊層 _ 120B、一厚金屬層13〇B以及一保護層15〇。 曰 羊細而δ，電路板1 〇〇具有一表面102與多個間距排 列的接塾110 (圖4中僅示意地緣示二個），其中這些接 墊110配置於電路板100的表面102上，且任兩相鄰&這 些接塾110的間距介於50微米（从m)至150微米（#瓜） 之間。在本實施例中’這些接墊110的材質包括銅，電路 板100例如是一印刷電路板或載板（IC carrier)。 防焊層120B配置於電路板1〇0上且覆蓋電路板1〇〇 15 29495twf.doc/n 201021136 V/ V ✓ vy \J^ 的表面102，其中防焊層12〇B具有多個開口 122B (圖4 中僅示意地緣示二個），且這些開口 122B分別暴露出這 些接墊110。在此必須說明的是，依據防焊層120B之這些 開口 122B所分別暴露出這些接墊11〇的面積大小，可分 為焊罩定義型開口及非焊罩定義型開口兩種型態。在本實 施例中，防焊層120B的這些開口 122B為非焊罩定義型開 口且這些開口 122B所分別暴露出的這些接墊HQ為 焊罩定義型接墊。 ❹ 厚金屬層130B分別配置於這些接墊11〇上，其中厚 金屬層130B突出於防焊層12〇B之外，且厚金屬層、13〇$ 可以為厚度大於防焊層12〇b且小於防焊層12〇]3高度兩倍 的柱狀凸塊，但不以此為限。在本實施例中，厚金屬層13〇^ 的厚度的設計與防焊層！細的高度具有一比例關係，以 一般防焊層120B的高度（約為5微米〜2〇微米）為例， 田防焊層120B的尚度為1〇微米（am)時，厚金屬層 的厚度小於防焊層12GB的高度的二倍，也就是說，厚金 • 屬層刪的厚度小於等於2〇微米Um)。厚金屬層誦 例如是無電電鍍法所形成的化銅。 保護層150覆蓋於厚金屬層13〇B所突出的表面上。 在本實施例令，保護層15〇的材質例如是無電電鍍法所形 成的化錫。在另一實施例中，保護層15〇亦可由鎳金或有 機保焊鮮保護層取代’同樣緖止厚金屬層1遍的氧 化。由於保護層150是位於厚金屬層13〇B的表面上，而 厚金屬層130B是突出於防焊層12〇B之外，因此本實施例 16 ^9495twf.doc/n 201021136 料與防焊層120B之開口 122B的縱橫比的問題，也就 是說，在本實施例中，無需沉積大量的焊料於厚金屬層 130B上’即可於間距排列之接墊11〇上形成電性連接結 構。 ^圖4B為本發明之另一實施例之一種具有導電凸塊的 電路板結構的示意圖。請同時參考圖4A與圖4B，圖4B 之电路板結構100C與圖4A之電路板結構ιοοΒ相似，惟 一者主要差異之處在於：圖4B -電路板結構1〇〇c的防焊 層120C包括一第一防焊層124與一第二防焊層126，其中 弟防¥層124覆蓋電路板1〇〇的表面1〇2，第二防焊層 126覆蓋第一防焊層124。在本實施例中，第一防焊層 與第二防焊層126的材質實質上相同。 簡吕之，本實施例之具有導電凸塊之電路板結構Referring to the figure, a protective layer m is formed on the thick metal layer 130 A to be sub-ball or printed and reflowed to form a plurality of tantalum bumps 140 on each of the protective layers 132, each of which A solder bump 14 〇 covers each of the protective layers 132 and protrudes from each of the openings 122. Referring to FIG. 3e, next, when the solder bumps 14 are formed by ball or printing, a solder ball bonding process can be further performed to more closely press the solder bumps 14 to the shy layer. 132, to form a coin-shaped solder bump 140' and fill the solder bumps 14A with the openings 122A of the solder resist layer 12, respectively, as a subsequent circuit board structure. The electrical connection structure between the 〇A and the wafer (not shown). θ Since these solder bumps 140 are located on the thick metal layer 13A, and the thickness of the thick metal layer 130A is, for example, greater than 4 micrometers, which is about 1/5 or more of the height of the solder resist layer 12A, the materials are lowered. The bumps 14 are filled in the depths of the openings 122A, so that the user can quickly form solder bumps having a predetermined height by printing or balling. Therefore, the present embodiment can form an electrical connection on the interfaces 110 of the fine pitch arrangement. structure. In the present embodiment, the material of the solder 14 20102113629495twf_ bump 140 includes a tin-lead alloy or a tin-silver-copper alloy. So far, the fabrication of the conductive bumps has been completed on the circuit board structure 100A. In short, since the manufacturing method of the conductive bump of the embodiment adopts an electroless plating process, it is not necessary to use a highly polluting and costly key bonding process to form a thick metal layer 130A on the surface of the pad no, wherein the thick metal layer The thickness of 13 〇A ^ is increased, so that the vertical inspection ratio (the ratio of the opening depth/opening aperture ratio) of the opening 122A of the solder resist layer 12A can be relatively lowered. In addition, in the case where the wiring board structure Lu 100A has an overall predetermined height 'because the solder bumps 140 are over the thick metal layer 130A', the solder bumps 140 can be reduced by the thickness increase of the thick metal layers 13 The amount of use, and the solder bump n8 which is in a molten state at 18 o'clock, can be avoided, and the solder bump n8 is bridged and short-circuited (refer to FIG. 1), thereby improving the process yield of the conductive bump and the circuit board structure 100A. Reliability. 4A is a schematic diagram of a circuit board structure having conductive bumps according to another embodiment of the present invention. Referring to FIG. 4A, in the embodiment, the circuit board structure 100B having conductive bumps includes a circuit board 1A, a solder resist layer _120B, a thick metal layer 13B, and a protective layer 15A. The circuit board 1 has a surface 102 and a plurality of spaced-apart interfaces 110 (only two are schematically shown in FIG. 4), wherein the pads 110 are disposed on the surface 102 of the circuit board 100. And any two adjacent & the spacing of these interfaces 110 is between 50 microns (from m) to 150 microns (# melon). In the present embodiment, the material of these pads 110 includes copper, and the circuit board 100 is, for example, a printed circuit board or an IC carrier. The solder resist layer 120B is disposed on the circuit board 1〇0 and covers the surface 102 of the circuit board 1〇〇15 29495twf.doc/n 201021136 V/V ✓ vy \J^, wherein the solder resist layer 12〇B has a plurality of openings 122B (only two are shown schematically in Figure 4), and these openings 122B expose the pads 110, respectively. It should be noted that the size of the pads 11B exposed by the openings 122B of the solder resist layer 120B can be divided into two types: the solder mask defining type opening and the non-welding mask defining type opening. In the present embodiment, the openings 122B of the solder resist layer 120B are non-weld cap definition openings and the pads HQ exposed by the openings 122B are respectively solder mask defining pads.厚 Thick metal layers 130B are respectively disposed on the pads 11〇, wherein the thick metal layer 130B protrudes beyond the solder resist layer 12〇B, and the thick metal layer, 13〇$ may be thicker than the solder resist layer 12〇b The columnar bump is less than twice the height of the solder resist layer 12〇]3, but is not limited thereto. In this embodiment, the thickness of the thick metal layer 13〇^ is designed and the solder resist layer! The fine height has a proportional relationship, taking the height of the general solder resist layer 120B (about 5 μm to 2 μm) as an example. When the field solder resist layer 120B is 1 μm (am), the thick metal layer is The thickness is less than twice the height of the solder mask 12GB, that is, the thickness of the thick gold layer is less than or equal to 2 μm Um. The thick metal layer 诵 is, for example, copper formed by electroless plating. The protective layer 150 covers the surface on which the thick metal layer 13B protrudes. In the present embodiment, the material of the protective layer 15 is, for example, tin which is formed by electroless plating. In another embodiment, the protective layer 15 can also be replaced by a nickel-gold or an organic solder-protected protective layer. Similarly, the thick metal layer is oxidized for one pass. Since the protective layer 150 is on the surface of the thick metal layer 13B, and the thick metal layer 130B is protruded beyond the solder resist layer 12B, the present embodiment is in the form of a solder resist layer. The problem of the aspect ratio of the opening 122B of 120B, that is, in this embodiment, it is not necessary to deposit a large amount of solder on the thick metal layer 130B to form an electrical connection structure on the pads 11 of the pitch arrangement. Figure 4B is a schematic diagram of a circuit board structure having conductive bumps in accordance with another embodiment of the present invention. Referring to FIG. 4A and FIG. 4B simultaneously, the circuit board structure 100C of FIG. 4B is similar to the circuit board structure ιοοΒ of FIG. 4A, and the only difference is that: FIG. 4B - the solder resist layer 120C of the circuit board structure 1〇〇c includes A first solder mask layer 124 and a second solder resist layer 126, wherein the layer 124 of the control layer covers the surface 1〇2 of the circuit board 1〇〇, and the second solder resist layer 126 covers the first solder resist layer 124. In the present embodiment, the materials of the first solder resist layer and the second solder resist layer 126 are substantially the same. Jane Luzhi, the circuit board structure with conductive bumps of this embodiment
l〇〇B、100C，其厚金屬層130B突出於防焊層120B、120Cl〇〇B, 100C, the thick metal layer 130B protrudes from the solder resist layers 120B, 120C
之外’且厚金屬層1306可以為厚度大於防焊層120B、120C 小於防焊層12〇B、12〇c高度兩倍的柱狀凸塊，其中防 ❹ 焊層，厚度約為5微米〜2G微米之間，較佳以無電電鑛 f形成具有預定高度的柱狀凸塊，不禽使用高污染且成本 南的電鑛製程，即可於間距排列之接塾11〇上形成電性連 接結構。 以上僅介紹本發明之具有導電凸塊之電路板結構 100B，並未介紹本發明之導電凸塊的製作方法。對此，以 下將以圖4B中的具有導電凸塊之電路板結構卿c作為舉 例說明，並配合圖5A至圖5G對本發明的導電凸塊的製作 17 ^.9495twf.d〇c/n 201021136 方法進行詳細的說明。 一立圖至圖5G為圖4B之導電凸塊的製造方法的流程 不思圖Ά參考81 5A’依照本實施例的導電&塊的製作 方法’首先’提供一電路板1〇〇。電路板100具有-表面 路板刚的表面102上配置有多個間距排列的接 圖5A中僅不意地繪示二個），其中任兩相鄰之這 1接塾110的間距介於5〇微米（㈣）至15〇微米（ 之間。The outer thick layer 1306 may be a columnar bump having a thickness greater than twice the height of the solder resist layers 120B, 120C and less than twice the height of the solder resist layers 12〇B, 12〇c, wherein the anti-friction layer has a thickness of about 5 μm. Between 2G micrometers, columnar bumps having a predetermined height are preferably formed without electro-electric ore f, and no high-pollution and costly electric ore process can be used for the poultry to form an electrical connection on the pitch-arranged joint 11〇. structure. Only the circuit board structure 100B with conductive bumps of the present invention will be described above, and the method of fabricating the conductive bumps of the present invention will not be described. In this regard, the circuit board structure with conductive bumps in FIG. 4B will be exemplified below, and the fabrication of the conductive bumps of the present invention will be described with reference to FIGS. 5A to 5G. 17 ^.9495twf.d〇c/n 201021136 The method is described in detail. A vertical view to Fig. 5G is a flow chart of a method of manufacturing the conductive bump of Fig. 4B. </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> <RTIgt; The circuit board 100 has a surface plate having a plurality of pitches arranged on the surface 102 of the surface plate. FIG. 5A is only schematically shown in FIG. 5A, and the spacing between any two adjacent ones of the interfaces 110 is 5〇. Micron ((iv)) to 15 micron (between.
# ▲接著，形成—光阻層170於電路板100的表面102上， /、光阻層170南於這些接墊11〇，且未覆蓋這些接整 I/O其目的在於限制後續所要形成之厚金屬層 130B的形 此>考圖5B，接著，進行—無電電鍍製程，以於這 二a U〇的表面分別形成一厚金屬層130B。詳細而言， 推所ί仃之無電電鍍製程，是利用所添加的還原劑 偏子還原成金屬，並沉積在這些接墊110的表面， 胃的厚金屬層13GB，其中厚金屬層13GB的材質 °簡言之’本實_之厚金屬層13GB是採用化 干沈^的方式形成於這些接墊110的表面上。 ㈣曰月^考圖5C ’接著，移除光阻層170以及形成至少 一防焊層l2〇C於電路柘 就於嫩Γ為侧成防焊層 . 的貝轭例，但不以此為限。在本實 防焊層120C包括一第—防焊層124與一第二防 h 126，且形成防焊層mc的步驟，首先，形成第一防 18 201021136— 焊層124於電路板loo上，其中第一防焊層124覆蓋電路 板1〇〇的表面102。在本實施例中，形成第一防焊層124 於電路板100上的方式包括噴墨法或網版印刷法或捲軸式 (roll to roll)。 請同時參考圖5D與5E，接著，進行一平坦化製程， 對第一防焊層124照射一雷射光束l，以移除局部與厚金 屬層130B相連接處的第一防焊層124。詳細而言，當第一 防焊層124形成於電路板100上時，由於這些接墊u〇呈 間距排列且因表面張力的關係，使得位於任兩相鄰之這些 接墊110上的厚金屬層130B與第一防焊層124的相連接 處與電路板100的表面102不平行，因此照射雷射光束L 以移除局部與厚金屬層130B相連接處的第一防焊層 124 ’除了可以使得第一防焊層124的表面平坦化外，還可 =增加後續製程時保護層150與厚金屬層13〇B之間的接 著面積並且有清潔功能，有助於後續製程。 請參考圖5F，之後，形成第二防焊層126於第一防焊 • 層124上，其中第二防.焊層覆蓋第一防焊層124。詳 細而言，在本實施例中，第一防焊層124覆蓋電路板1〇〇 的表面102，且厚金屬層130B突出於第二防焊層126之 外，其中厚金屬層130B為厚度大於防焊層12〇(：且小於防 焊層120C高度兩倍的柱狀凸塊，防焊層12〇c的厚度約為 5胃微米〜20微米之間。此外，在本實施例中，形成第二防 烊層126與第-防焊層124上的方式包括喷墨法或網版印 刷法或捲轴式（roll to roll)。 19 z9495twf.doc/xi 201021136 值得一提的是「在其他的實施例中，防焊層12〇c亦 可僅為單一層，也就是說’防焊層12〇c可如同圖4A之防 焊層120B。因此，圖5C至圖5F形成防焊層12〇C於電路 板100上只是本發明的一實施例，並非用以限制本發明。 請參考圖5G，接著，最後，形成一保護層15〇於厚 金屬層130B所突出的表面上。在本實施例中，形成保護 層150的方法包括無電電鍍法，利用所添加的還原劑使金 屬離子還原成金屬，並沉積在厚金屬層13〇B所突出的表 ❹ 面上’而保護層150的材質包括化錫、化銀、化金或錫合 金。此外，本實施例之焊料150亦可為其他保護層，其材 貝包括鎳金或有機保焊劑。至此，已於電路板結構 上完成導電凸塊的製作。 簡言之’由於實施例之導電凸塊的製造方法是採用無 電電鑛製程，以於接塾11〇的表面上形成厚金屬層13〇b， 此厚金屬層1遍突$於防料歌之外，且厚金屬層 130Β為厚度大於防焊層12QC且小於防焊層高度兩 倍的柱狀凸塊，故不需使㈣㈣且成本高的.電鑛製程， =於間轉狀触11G上形成電性連接結構。此外， 焊的方柄，可崎免受熱魏_焊料發生橋 問題，進而提高導電凸塊的製程良率及電路 板結構100C的可靠度。 益電祕本發明m塊的製造方法因採用 tip夂⑽接塾的表面上形成厚金屬層，故可相 牛- >層之開口的縱橫比（開口深度/開口孔徑的比 20 201021136 29495twf.d〇c/n 值L，而減少焊料的使用量，進而可避免於迴焊焊料時受 熱呈熔融的焊料發生橋接現象與短路問題，進而提高導電 凸塊的製程良率及電路板結構的可靠度。此外，在^板 二構100A —整體預定尚度的情況下，由於焊料凸塊或焊 料是覆蓋於厚金屬層上，因此可藉由厚金屬層的厚度來減 少焊料凸塊或烊料的使用量。 雖然本發明已以實施例揭露如上，然其並非用以限定 本發明’任何所屬技術領域中具有通常知識者，在不脫離 本發明之精神和範圍内，當可作些許之更動與潤飾，故本 發明之保護範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1為習知一種電路板結構的剖面示意圖。 圖2為本發明之一實施例之一種具有導電凸塊的電路 板結構的示意圖。 圖3A至圖3E為圖2之導電凸塊的製造方法的流程示 鲁 意圖。 圖4A為本發明之另一實施例之一種具有導電凸塊的 電路板結構的示意圖。 圖4B為本發明之另一實施例之一種具有導電凸塊的 電路板結構的示意圖。 圖5Α至圖5g為圖4Β之導電凸塊的製造方法的流程 示意圖。 21 201021136_ '【主要元件符號說明】 10A :電路板結構 10 : 12 :表面 14 : 16 :防焊層 17 : 18 :焊料凸塊 19 : 100A、100B、100C :電路板結構 100 :電路板 102 110 :接墊 參 120A、120B、120C :防焊層 122A、122B :開口 124:第一防焊層 126 130A、130B :厚金屬層 140 :焊料凸塊 132 170 :光阻層 L :雷射光束 P : 電路板 接墊 開口 電鍍種子層 :表面 :第二防焊層 、150 :保護層 橋接處# ▲ Next, the photoresist layer 170 is formed on the surface 102 of the circuit board 100, and the photoresist layer 170 is formed on the pads 11A, and the integrated I/O is not covered. The purpose is to limit the subsequent formation. The shape of the thick metal layer 130B is as follows. Next, an electroless plating process is performed to form a thick metal layer 130B on the surfaces of the two a U 〇. In detail, the electroless plating process of the pusher is reduced to metal by using the added reducing agent, and deposited on the surface of these pads 110. The thick metal layer of the stomach is 13 GB, and the thick metal layer is 13 GB. °In a nutshell, the thick metal layer 13GB of the present invention is formed on the surface of these pads 110 by means of a dry film. (4) 曰月^考图5C' Next, remove the photoresist layer 170 and form at least one solder mask l2〇C in the circuit 柘 on the side of the enamel is a solder resist layer. limit. The first solder resist layer 120C includes a first solder mask layer 124 and a second solder resist layer 126, and a solder resist layer mc is formed. First, a first anti- 18 201021136 - solder layer 124 is formed on the circuit board loo. The first solder mask layer 124 covers the surface 102 of the circuit board 1 . In the present embodiment, the manner in which the first solder resist layer 124 is formed on the circuit board 100 includes an ink jet method or a screen printing method or a roll to roll. Referring to FIGS. 5D and 5E simultaneously, a planarization process is performed to irradiate the first solder resist layer 124 with a laser beam l to remove the first solder resist layer 124 where the portion is bonded to the thick metal layer 130B. In detail, when the first solder resist layer 124 is formed on the circuit board 100, since the pads are arranged at a pitch and due to the surface tension, the thick metal on any of the adjacent pads 110 is made. The junction of the layer 130B with the first solder resist layer 124 is not parallel to the surface 102 of the circuit board 100, thus illuminating the laser beam L to remove the first solder mask layer 124' where the portion is joined to the thick metal layer 130B. The surface of the first solder resist layer 124 may be flattened, and the bonding area between the protective layer 150 and the thick metal layer 13B may be increased in a subsequent process and have a cleaning function to facilitate subsequent processes. Referring to FIG. 5F, a second solder mask layer 126 is formed on the first solder mask layer 124, wherein the second solder resist layer covers the first solder resist layer 124. In detail, in the embodiment, the first solder resist layer 124 covers the surface 102 of the circuit board 1 , and the thick metal layer 130B protrudes beyond the second solder resist layer 126 , wherein the thick metal layer 130B is thicker than The solder resist layer 12〇 (: and less than twice the height of the solder resist layer 120C, the solder resist layer 12〇c has a thickness of about 5 μm to 20 μm. Further, in the present embodiment, the formation The manner of the second anti-mite layer 126 and the first solder resist layer 124 includes an inkjet method or a screen printing method or a roll to roll. 19 z9495twf.doc/xi 201021136 It is worth mentioning that "in other In the embodiment, the solder resist layer 12〇c may be only a single layer, that is, the solder resist layer 12〇c may be like the solder resist layer 120B of FIG. 4A. Therefore, FIG. 5C to FIG. 5F form the solder resist layer 12. 〇C is only an embodiment of the present invention on the circuit board 100, and is not intended to limit the present invention. Referring to FIG. 5G, finally, finally, a protective layer 15 is formed on the surface of the thick metal layer 130B. In an embodiment, the method of forming the protective layer 150 includes electroless plating, and the metal ions are further returned by using the added reducing agent. The metal is deposited on the surface of the surface of the thick metal layer 13B. The material of the protective layer 150 includes tin, silver, gold or tin alloy. In addition, the solder 150 of this embodiment may also be The other protective layer, the material of which includes nickel gold or an organic soldering flux. Thus, the fabrication of the conductive bumps has been completed on the circuit board structure. Briefly, the manufacturing method of the conductive bumps of the embodiment is an electroless ore processing process. a thick metal layer 13〇b is formed on the surface of the interface 11,, the thick metal layer 1 is overlaid on the surface of the material, and the thick metal layer 130 is thicker than the solder resist layer 12QC and smaller than the solder resist layer. Double columnar bumps, so there is no need to make (4) (four) and high cost. The electric ore process, = form an electrical connection structure on the 11G. In addition, the square handle of the welding can be protected from heat. _ solder joint bridge problem, thereby improving the process yield of the conductive bump and the reliability of the circuit board structure 100C. The manufacturing method of the m block of the invention is formed by forming a thick metal layer on the surface of the tip 夂 (10) interface. The aspect ratio of the opening of the phase - > layer (opening depth / opening The aperture ratio is 20 201021136 29495twf.d 〇 c / n value L, and the amount of solder used is reduced, thereby avoiding bridging and short-circuiting of the solder which is heated by the reflow solder, thereby improving the process of the conductive bumps. Yield and reliability of the board structure. In addition, in the case of the overall configuration of the board 100A, since the solder bump or solder is over the thick metal layer, the thickness of the thick metal layer can be To reduce the amount of solder bumps or dips used. Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention to those of ordinary skill in the art without departing from the spirit and scope of the invention. In the meantime, the scope of protection of the present invention is subject to the definition of the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic cross-sectional view showing a conventional circuit board structure. 2 is a schematic diagram of a circuit board structure having conductive bumps according to an embodiment of the present invention. 3A to 3E are schematic diagrams showing the flow of the method of manufacturing the conductive bump of Fig. 2. 4A is a schematic diagram of a circuit board structure having conductive bumps according to another embodiment of the present invention. 4B is a schematic diagram of a circuit board structure having conductive bumps according to another embodiment of the present invention. 5A to 5g are schematic flow charts showing a method of manufacturing the conductive bump of FIG. 21 201021136_ '[Main component symbol description] 10A: Circuit board structure 10 : 12 : Surface 14 : 16 : Solder mask 17 : 18 : Solder bump 19 : 100A, 100B, 100C : Circuit board structure 100 : Circuit board 102 110 : pads 120A, 120B, 120C: solder resist layers 122A, 122B: opening 124: first solder resist layer 126 130A, 130B: thick metal layer 140: solder bump 132 170: photoresist layer L: laser beam P : Board Pad Opening Plating Seed Layer: Surface: Second Solder Mask, 150: Protective Layer Bridge
22twenty two
Claims (1)
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| Application Number | Priority Date | Filing Date | Title |
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| TW097144555A TWI476844B (en) | 2008-11-18 | 2008-11-18 | Method for fabricating conductive bump and circuit board structure with the same |
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| Application Number | Priority Date | Filing Date | Title |
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| TW097144555A TWI476844B (en) | 2008-11-18 | 2008-11-18 | Method for fabricating conductive bump and circuit board structure with the same |
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| Publication Number | Publication Date |
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| TW201021136A true TW201021136A (en) | 2010-06-01 |
| TWI476844B TWI476844B (en) | 2015-03-11 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI484572B (en) * | 2012-06-25 | 2015-05-11 | Unimicron Technology Corp | Method for fabricating conductive bump and wiring substrate |
| TWI682695B (en) * | 2018-07-05 | 2020-01-11 | 同泰電子科技股份有限公司 | Circuit board structure with conection terminal formed by solder mask defined process |
| CN111354845A (en) * | 2018-12-20 | 2020-06-30 | 同泰电子科技股份有限公司 | Light-emitting diode carrier plate with preset conductive bumps |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI330053B (en) * | 2006-08-14 | 2010-09-01 | Unimicron Technology Corp | Conductive connection structure formed on the surface of circuit board and manufacturing method thereof |
| TWI316381B (en) * | 2007-01-24 | 2009-10-21 | Phoenix Prec Technology Corp | Circuit board and fabrication method thereof |
| TWI355868B (en) * | 2007-03-23 | 2012-01-01 | Circuit board structure having buffer layer and me |
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2008
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI484572B (en) * | 2012-06-25 | 2015-05-11 | Unimicron Technology Corp | Method for fabricating conductive bump and wiring substrate |
| TWI682695B (en) * | 2018-07-05 | 2020-01-11 | 同泰電子科技股份有限公司 | Circuit board structure with conection terminal formed by solder mask defined process |
| CN111354845A (en) * | 2018-12-20 | 2020-06-30 | 同泰电子科技股份有限公司 | Light-emitting diode carrier plate with preset conductive bumps |
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