1351,749. 九、發明說明： 【發明所屬之技術領域】 • 本發明係關於一種封裝基板及其製法，尤指一種適用 於覆晶封裝之封裝基板及其製法。 5 【先前技術】 隨著電子產業的蓬勃發展，電子產品亦逐漸進入多功 能、高性能的研發方向。為滿足半導體封裝件高積集度 > (integration)以及微型化（miniaturization)的封裝要求， 10 提供多數主被動元件及線路連接之電路板，亦逐漸由單層 板演變成多層板，以使在有限的空間下，藉由層間連接技 術（interlayer connection)擴大電路板上可利用的佈線面積 而配合高電子密度之積體電路（integrated circuit)需求。 一般半導體裝置之製程，首先係由晶片載板製造業者 15 生產適用於該半導體裝置之晶片載板，如基板或導線架。 之後再將該些晶片載板交由半導體封裝業者進行置晶、打 .線、封膠以及植球等封裝製程。又一般半導體封裝是將半 導體晶片背面黏貼於封裝基板頂面進行打線接合（wire bonding )，或者將半導體晶片之作用面以覆晶接合（ 20 chip)方式與封裝基板接合，再於基板之背面植以焊料球以 供與其他電子裝置進行電性連接。 S知封裝基板之結構請參考圖如圖1所示，首先提 供一於其相對兩表面各具有一線路層115及具有貫穿該兩 表面之導電通孔之核心板11，接著利用業界熟知之線路 1351749 增層技術，於核心板11兩表面形成線路增層結構12，此線 路增層結構12具有一線路層13，並具有複數導電盲孔137電 性連接線路層115與線路層13，如此完成一基板本體1〇 (其 表面可區分為一第一表面l〇a及一相對之第二表面1〇b，而 5 第一表面l〇a之線路即為線路層13)。而後，在第一表面1(^ 及第二表面l〇b分別形成一具有複數開孔164顯露線路層13 做為電性連接墊（凸塊焊墊131、被動元件焊墊132及焊球 墊130)之防焊層16。 然後，同時分別於凸塊焊墊131、被動元件焊墊132及 10 焊球墊130上以電鍍形成金屬凸塊14卜金屬層142及金屬層 140。接著，仍以電鍍方式，於金屬凸塊141、金屬層142及 金屬層140表面形成一表面處理層19，該表面處理層19的材 料可為錫、銀、金等’基於成本考量一般為錫，以保護金 屬凸塊141免於因曝露環境中之空氣而遭受氧化等侵襲。據 15 此’即完成一封裝基板。復可分別在金屬凸塊14卜金屬層 142及金屬層140上之表面處理層19表面形成焊料凸塊、焊 料球（圖未示），以分別提供與一半導體晶片（圖未示） 進行覆晶接合、一被動元件接合（圖未示）及一印刷電路 板（圖未示）接合。 2〇 在現今積體電路功能日益增加下，其電性要求益增 大封裝基板製程在關鍵尺寸（criticai dimension，如：最 • .· · · 小線寬）不斷縮小的趨勢中，面臨的問題也陸續出現。由 於線路厚度與寬度及線路間距具一定相對的比例關係，且 最外面的線路層13包含與之同時形成的電性連接墊（凸塊 1351749 焊塾U1、被動元件焊墊132及焊球墊130)，因此當線路層 ^厚度隨著寬度縮小時，與之對應的電性連接墊尺寸與厚 , 度也隨之縮小，因此金屬凸塊141與焊料凸塊兩者之接觸面 積亦隨著縮小’此會造成接點強度不足以承受晶片與基板 5 間的應力，而發生接點（joint)斷裂的現象，因此影響封 裝結構之可靠性。 再者’隨著半導體晶片表面佈設電極塾之密度提高， 晶片與封裝基板之焊.料凸塊尺寸亦需隨之縮小，而晶片及 • 封裝基板接置後之間隙高度亦隨著接點尺寸縮小而下降， 10導致在填充底部膠材時，膠材不易完全填滿於封裝基板與 晶片之間的空隙而產生孔洞，進而發生晶片爆裂等嚴重問 題。 另外，經由上述方法製成之封裝基板，由於表面處理 層19無法於金屬凸塊141側面製作，以致於長時間放置易使 15金屬凸塊141側面因氧化等因素受損，於封裝時無法與底膠 緊密結合，影響封裝結構之可靠性，甚至造成接點失效。 鲁基於上述問題，封裝基板具有足夠強度之電性連接 塾’不易填充底部膠材之問題，及保護金屬凸塊侧面因氧 化等因素造成之損害，實為現今業界亟需解決之課題。 20 【發明内容】’ 本發明提供一種封裝基板，其包括：一基板本體，其 具有相對之-第一表面與一第二表面，第一表面具有一線 路廣1¾線路並具有複數凸塊焊塾及複數被動元件焊 1351.749 墊，其中該些凸塊焊墊係呈陣列排列；複數電鍍金屬凸塊， 係設於該些凸塊焊墊表面；以及一第一防焊層係設於第 一表面，第一防焊層具有一開口區，以顯露該基板本體第 一表面之凸塊焊墊陣列區域，第一防焊層並具有複數第一 開孔’以顯露該些被動元件焊墊之部份表面。 上述封裝基板中，金屬凸塊之高度可高於第一防焊層。 上述封裝基板中，電鍍金屬凸塊所使用之材料不限， 較佳可使用銅或錫作為電鍍金屬凸塊之材料。1351, 749. IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a package substrate and a method of manufacturing the same, and more particularly to a package substrate suitable for flip chip packaging and a method of fabricating the same. 5 [Prior Art] With the rapid development of the electronics industry, electronic products have gradually entered the direction of multi-functional and high-performance research and development. In order to meet the packaging requirements of semiconductor package high integration & miniaturization, 10 circuit boards that provide most active and passive components and line connections are gradually evolved from single-layer boards to multi-layer boards. In a limited space, the interconnect area available on the board is expanded by the interlayer connection to match the high electron density integrated circuit requirements. In the general semiconductor device process, the wafer carrier manufacturer 15 first produces a wafer carrier, such as a substrate or lead frame, suitable for the semiconductor device. The wafer carriers are then transferred to a semiconductor packager for packaging processes such as crystallization, wire bonding, encapsulation, and ball placement. In a general semiconductor package, the back surface of the semiconductor wafer is adhered to the top surface of the package substrate for wire bonding, or the active surface of the semiconductor wafer is bonded to the package substrate by a chip bonding method, and then implanted on the back surface of the substrate. A solder ball is used for electrical connection with other electronic devices. Please refer to FIG. 1 for the structure of the package substrate. First, a core layer 115 having a circuit layer 115 and conductive vias extending through the two surfaces is provided on the opposite surfaces, and then the well-known circuit is used. 1351749 The layering technology forms a line build-up structure 12 on both surfaces of the core board 11. The line build-up structure 12 has a circuit layer 13 and has a plurality of conductive blind holes 137 electrically connected to the circuit layer 115 and the circuit layer 13, thus completing A substrate body 1 〇 (the surface thereof can be divided into a first surface 10a and an opposite second surface 1 〇 b, and the line of the 5th surface 〇a is the circuit layer 13). Then, a first surface 1 (^ and a second surface 10b are respectively formed with a plurality of openings 164 to expose the circuit layer 13 as electrical connection pads (bump pad 131, passive component pad 132 and solder ball pad) 130) The solder resist layer 16. Then, the metal bumps 14 and the metal layer 142 and the metal layer 140 are formed by electroplating on the bump pads 131, the passive component pads 132 and the solder ball pads 130, respectively. A surface treatment layer 19 is formed on the surface of the metal bump 141, the metal layer 142, and the metal layer 140 by electroplating. The material of the surface treatment layer 19 may be tin, silver, gold, etc. The metal bumps 141 are protected from oxidation and the like by exposure to the air in the environment. According to this, a package substrate is completed. The surface treatment layer 19 on the metal bumps 142 and the metal layer 140 is respectively provided. Solder bumps and solder balls (not shown) are formed on the surface to provide flip chip bonding with a semiconductor wafer (not shown), a passive component bonding (not shown), and a printed circuit board (not shown). Bonding. 2〇In today's integrated circuit Increasingly, the electrical requirements increase the package substrate process in the critical dimension (such as: the most · · · · · small line width) shrinking trend, the problems are also appearing. Due to the thickness of the line It has a proportional relationship with the width and the line spacing, and the outermost circuit layer 13 includes electrical connection pads (bumps 1351749, U1, passive component pads 132 and solder ball pads 130) formed at the same time. When the thickness of the circuit layer is reduced with the width, the size and thickness of the corresponding electrical connection pads are also reduced, so the contact area between the metal bumps 141 and the solder bumps is also reduced. The joint strength is insufficient to withstand the stress between the wafer and the substrate 5, and the joint breakage occurs, thereby affecting the reliability of the package structure. Further, as the density of the electrode on the surface of the semiconductor wafer is increased, the wafer is increased. The solder bump size of the package substrate also needs to be reduced, and the gap height between the wafer and the package substrate is also reduced as the contact size is reduced. When the bottom rubber is filled, the rubber material is not easily filled in the gap between the package substrate and the wafer to cause voids, and serious problems such as wafer bursting occur. Further, the package substrate produced by the above method cannot be surface treated layer 19 It is made on the side of the metal bump 141, so that the long-term placement makes the side of the 15 metal bump 141 damaged by oxidation and the like, and cannot be tightly combined with the primer during packaging, which affects the reliability of the package structure and even causes contact failure. Based on the above problems, Lu has a problem that the package substrate has sufficient strength and electrical connection 塾 'not easy to fill the bottom adhesive material, and protects the side of the metal bump from oxidation and other factors, which is an urgent problem in the industry today. 20 SUMMARY OF THE INVENTION The present invention provides a package substrate comprising: a substrate body having opposite first surfaces and a second surface, the first surface having a line width of 13⁄4 lines and having a plurality of bump solder bumps And a plurality of passive components soldering 13511.947 pads, wherein the bump pads are arranged in an array; a plurality of plated metal bumps are disposed on the bump pads; and a first solder resist layer is disposed on the first surface The first solder resist layer has an open area to expose the bump pad array region of the first surface of the substrate body, and the first solder resist layer has a plurality of first openings 'to expose the portions of the passive component pads Part of the surface. In the above package substrate, the height of the metal bumps may be higher than that of the first solder resist layer. In the above package substrate, the material used for plating the metal bumps is not limited, and copper or tin is preferably used as the material of the plated metal bumps.
10 15 右使用銅作為電鍍金屬凸塊之材料時，該封裝基板更 可包括一表面處理層，係設於第一開孔所顯露之被動元件 焊塾表面及㈣金屬凸塊表面，並延伸至覆蓋凸塊焊墊側 表面。該表面處理層之材料能防止電鍍金屬凸塊及凸塊焊 墊讫党物理性或化學性損害，較佳可選自鎳/金有機保焊 膜化鎳金、鎳/把/金、錫、焊錫、無錯焊錫及銀其中 之一者。 另方面，若使用錫作為電鑛金屬凸塊之材料時，電 φ 鍍金屬凸塊之尺寸可小於或等於凸塊焊墊，此時更可包括 一表面處理層，係設於第一開孔所顯露之被動元件焊墊表 面及電鍍金屬凸塊表面，並延伸至覆蓋凸塊焊墊側表面。 2〇或者，若使用錫作為電鍍金屬凸塊之材料時，電鍍金屬凸 塊之尺寸可大於凸塊焊墊並包覆凸塊焊墊。 上述封裝基板中，基板本體第二表面具有複數焊球 墊，並設有一第二防焊層，係具有複數第二開孔，以顯露 1351749 焊球墊之部份表面。該封裝基板復可再包括一表面處理層 設於第二開孔所顯露之焊球墊表面。 本發明亦提供一種封裝基板之製法，其步驟包括：提 供—基板本體，其具有相對之一第一表面與一第二表面， 5第一表面具有一線路層，該線路層並具有複數凸塊焊墊及 複數被動元件焊墊，其中該些凸塊焊墊係呈陣列排列；於 基板本體第一表面形成一阻層，並於該阻層形成複數開孔 顯露凸塊焊墊之部份表面；於阻層之開孔中及其顯露之凸 • 塊烊墊上形成複數電鍍銅凸塊；移除阻層；以及於基板本 10體表面形成一第一防焊層，並於第一防焊層形成一開口 區，以顯露基板本體表面之凸塊焊塾陣列區域，且於第一 防焊層形成複數第一開孔，以顯露被動元件焊墊之部份表 面。 上述之製法更可包括於第一開孔所顯露之被動元件焊 15墊表面，及於電鍍銅凸塊表面形成一表面處理層，表面處 理層並延伸至覆蓋凸塊焊墊側表面。該表面處理層所使用 • 之材料不限，只要能防止電鍍銅凸塊及凸塊焊墊遭受物理 性或化學性損害即可，較佳可選自於由錦/金有機保焊 膜化鎳&金、鎳/把/金、錫、焊錫、無錯焊錫及銀其中 2〇 之一者。 本發明另提供-種封裝基板之製法’其步称包括：提 供-基板本體，其具有相對之一第一表面與一第二表面， 第一表面具有一線路層，該線路層並具有複數凸塊焊墊及 複數被動元件焊墊，其令凸塊焊塾係呈陣列排列；於該基 1351749 板，體表面形成一第一防焊層，並於第一防焊層形成一開 區以顯路該基板本體表面之凸塊焊墊陣列區域，且於 ^第防焊層形成複數第一開孔，以顯露該些被動元件焊墊 之部份表面；於該基板本體第一表面形成一阻層，並於該 5阻層形成複數開孔以顯露該些凸塊焊墊；於該阻層之開孔 中及其顯露之凸塊焊墊上形成複數電鍍錫凸塊；以及移除 該阻層。 上述之製法中，阻層之開口之尺寸不大小不受限制’ 要此·顯露凸塊焊塾即可’若阻層之開口尺寸大於凸塊焊 ίο 塾時’能使電鐘錫凸塊包覆凸塊焊塾，則可防止凸塊焊墊 受到物理性或化學性損傷。另一方面，若阻層之開口之尺 寸係小於或等於凸塊焊墊時，更可包括一步驟：於第一開 孔所顯露之被動元件焊墊表面，及於電鍍錫凸塊表面形成 一化錫層，該化錫層並延伸至覆蓋凸塊焊墊側表面。同樣， 15 該化錫層可防止凸塊焊墊受到物理性或化學性損傷》 綜上所述，本發明所提供之封裝基板及其製法，因其 .凸塊蟬塾表面配置有電鑛金屬凸塊，其材料例如為銅則可 減少焊錫總量以降低成本。另一方面，由於電鍍金屬凸塊 直接與電性連接墊甚至其周圍之介電層接合，其結合力優 2〇 於與防焊層之結合力，因此可降低因接點強度不足所造成 之接點斷裂，以增加封裝基板之可靠性。此外，防焊層具 有一開口區，以顯露基板本體第一表面之凸塊焊墊陣列區 域，得以克服在填充底部膠材時，膠材不易完全填滿於封 裝基板與晶片之間的空隙之問題。再者，因具有延伸至覆 1351749 蓋凸塊焊墊側表面之表面處理層，故能防止電鍍金屬凸塊 及凸塊焊墊遭受物理性或化學性損害；若該電鍍金屬凸塊 材料為錫則可令其尺寸大於凸塊焊墊，俾以完整包覆凸塊 i 焊墊，或另以化錫層覆蓋凸塊焊墊側表面，故能防止凸塊 5 焊墊遭受物理性或化學性損害。 【實施方式】 .以下係藉由特定的具體實施例說明本發明之實施方 式，熟習此技藝之人士可由本說明書所揭示之内容輕易地 10 了解本發明之其他優點與功效。本發明亦可藉由其他不同 的具體實施例加以施行或應用，本說明書中的各項細節亦 可基於不同觀點與應用，在不悖離本發明之精神下進行各 種修飾與變更。 實施例1 15 首先，請參考圖2A至2E，此為本發明之封裝基板製作 流程剖視圖。 如圖2A所示，提供一基板本體20，其具有相對之一第 一表面20a與一第二表面20b。第一表面20a具有一線路層 23，該線路層23並具有複數凸塊焊墊231及複數被動元件焊 2〇 墊232，且凸塊焊墊231呈陣列排列。而第二表面20b具有複 數焊球墊2 3 0。該基板本體2 0係於一核心板21及其兩側利用 線路增層技術形成一線路增層結構22，而該線路增層結構 22的形成過程，係先於該核心板21及其兩側形成一介電層 220，再於該些介電層220表面分別形成一導電晶種層229， 11 1351749 藉由該導電晶種層229導電，以電鑛形成該線路層23。該導 電晶種層229的材料可為銅、錫、鎮、絡、鈦、銅-鉻合金 以及錫-鉛合金中所組群組其中之一者，在本實施例中係為 銅0 •5 接著，於基板本體20第一表面20a形成一阻層24,並於 阻層24形成複數開孔244以顯露該些凸塊焊墊231之部份表 面。該阻層24使用的材料係可為乾膜或液態光阻等。 而後，參考圖2B所示，於該些開孔244中，以及其顯露 ^ 之凸塊焊墊231表面形成複數電鍍金屬凸塊25。該電鍍金屬 10 凸塊25可選用自錫、銀、銅、金、叙、'録、鋅、錄、錯、 鎂、銦、鎵以及上述金屬所成群組之合金之其中一者，本 實施例則使用銅。 如圖2C所示，移除阻層24及其覆蓋之導電晶種層229。 接著參考圖2D，於基板本體20之第一表面20a形成一第一防 15 焊層26，其高度係低於電鍍金屬凸塊25之高度，以及於第 二表面20b形成一第二防焊層28。並於第一防焊層26形成一 開口區263，以顯露基板本體20表面之凸塊焊墊231陣列區 1 域，且於第一防焊層26形成複數第一開孔264,以顯露該些 被動元件焊墊232之部份表面。同樣，也於第二防焊層28形 20 成複數第二開孔284，以顯露該些焊球墊230之部份表面。 而後，如圖2E所示，透過物理沉積如濺鍍及蒸鍍，或 化學沉積如無電電鍍，於第一開孔264所顯露之被動元件焊 墊232表面、第二開孔284所顯露之焊球墊230表面、電鍍金 屬凸塊25表面、及凸塊焊墊231顯露之側表面，皆形成一表 12 1351749 面處理層29，即完成本發明之封裝基板。該表面處理層29 所使用的材料可為錫、銀、鎳、金、鉻/鈦、鎳/金、鎳/鈀、 鎳/鈀/金、有機保焊膜、化鎳浸金、焊錫及無鉛焊錫其中之 一者。 •5 本發明復提供一種封裝基板，如圖2D所示，其包括： 一基板本體20，其具有相對之一第一表面20a與一第二表面 20b，第一表面20a具有一線路層23，線路層23並具有複數 凸塊焊墊231及複數被動元件焊墊232,其中該些凸塊焊墊 f 231係呈陣列排列；複數電鍍金屬凸塊25，係設於該些凸塊 10 焊墊231表面；以及一第一防焊層26，係設於第一表面20a， 第一防焊層26具有一開口區263，以顯露基板本體20第一表 面20a之凸塊焊墊23.1陣列區域，第一防焊層26並具有複數 第一開孔264，以顯露該些被動元件焊墊232之部份表面。 上述之封裝基板，其中，該些電鍍金屬凸塊25係高於 15 第一防焊層26。 上述之封裝基板復可包括一表面處理層29,如圖2E所 示，係設於該些第一開孔264所顯露之被動元件焊墊232表 > 面，及設於該些電鍍金屬凸塊25表面，同時延伸至覆蓋凸 塊焊墊231顯露之侧表面。 20 上述之封裝基板中，該基板本體20之第二表面20b具有 複數焊球墊230,並設有一第二防焊層28,係具有複數第二 開孔284，以顯露該些焊球墊230之部份表面，而該封裝基 板亦可再包括一表面處理層29,係設於該些第二開孔284所 顯露之焊球墊230表面。 13 25 1351749 實施例2 本實施例提供另一種製作本發明之封裝基板的製法。 請參考圖3A至3F，此為本發明之封裝基板製作流程剖視圖。 '如圖3A所示，提供一基板本體20,其具有相對之一第 5 一表面20a與一第二表面2 Ob。第一表面20a具有一線路層 23，該線路層23並具有複數凸塊焊墊231及複數被動元件焊 墊232，且該些凸塊焊墊231呈陣列排列。而第二表面20b具 有複數焊球墊230。該基板本體20的製造方法可參考實施例 i 1，茲不贅述。 10 接著，同樣參考圖3A，於基板本體20第一表面20a形成 一第一防焊層26,及於第二表面20b形成一第二防焊層28。 而後，參考圖3B所示，於第一防焊層26開設一開口區 263及複數第一開孔264，以分別顯露上述基板本體20之第 一表面20a上之凸塊焊墊231陣列區域及被動元件焊墊 15 232。同時，於第二防焊層28開設複數第二開孔284，用以 顯露基板本體20之第二表面20b上焊球墊230。 如圖3C所示，形成一導電晶種層229覆蓋基板本體20 1 之第一表面20a及第二表面20b，亦即是同時覆蓋第一防焊 層26之表面、第一防焊層26之開口區263所顯露之凸塊焊墊 20 231陣列區域、第一防焊層26之第一開孔264所顯露之被動 元件焊墊232、第二防焊層28之表面、及第二防焊層？8之第 二開孔284所顯露之焊球墊230。 接著，參考圖3D所示，於第一防焊層26及第二防焊層 28之表面，分別形成一阻層24覆蓋兩者。並於該阻層24形 1351749 成複數開孔244顯露凸塊焊墊231表面之導電晶種層229。並 且，該開孔244之尺寸小於凸塊焊墊231之尺寸。 如圖3E所示，藉由該些開孔244所顯露之導電晶種層 ' 229導通電流，於該些開孔244中形成複數電鍍金屬凸塊 •5 25。本實施例使用錫作為材料。本實施例中該金屬金屬凸 塊25之高度係高於第一防焊層26之高度。 再者，如圖3F所示，移除阻層24及其下所覆蓋之導電 晶種層229。同樣利用類似實施例1所述之方式，於第一開 > 孔264所顯露之被動元件焊墊232表面、第二開孔284所顯露 10 之焊球墊230表面、電鍍金屬凸塊25表面、以及凸塊焊墊231 顯露之側表面，皆形成一表面處理層29，即完成本發明之 封裝基板。該表面處理層29所使用的材料可選自如實施例1 所述，本實例則為化錫，俾以完整保護該些電鍍金屬凸塊 25及凸塊焊墊231 15 實施例3 本實施例再提供一種製作本發明之封裝基板的製法。 丨 其製法類似於實施例2所述，但主要不同點則如下詳述。 首先，重複實施例2圖3A至圖3C之步驟。接著，參考 20 圖3D’所示，於第一防焊層26及第二防焊層28之表面，分別 形成一阻層24，因並於該些阻層24分別形成複數開孔244以 顯露該些凸塊焊墊231、複數開孔246以顯露第一防焊層26 之第一開孔264及其所顯露之被動元件焊墊232、複數開孔 245以顯露第二防焊層28之第二開孔284及其所顯露之焊球 25 墊230等三者表面之導電晶種層229。並且，開孔24^之尺寸 15 1351749 大於該些凸塊焊墊231之尺寸，且開孔246之尺寸大於第一 防焊層26之第一開孔264之尺寸，而開孔245之尺寸大於第 二防焊層28之第二開孔284之尺寸。 再者，如圖3E’所示，利用上一步驟顯露出之導電晶種 5層229導通電流，於開孔244,245,246中進行電鍍形成複數電 鍍金屬凸塊25。本實施例使用錫作為材料，但其他材料如 實施例所舉之金屬亦可選擇使用。該金屬凸塊25之高度， 可以略咼於第一防焊層26之高度。本實施例於凸塊焊墊23 j • 表面之電鍍金屬凸塊25，係包覆凸塊焊墊231之上表面及側 10 表面’俾以完整保護凸塊焊墊231。 再者，如圖3F’所示，移除阻層24及其下所覆蓋之導電 晶種層229，即完成本發明之封裝基板。 上述實施例僅係為了方便說明而舉例而已，本發明所 主張之權利範圍自應以申請專利範園所述為準，而非僅限 15 於上述實施例。 | 【圖式簡單說明】 圖1係習知封裝基板之剖面結構示意圖。 圖2 A至2 E係本發明實施例1中封裝基板製法之流程剖面結 20 構示意圖。 圖3A至3F係本發明實施例2中封裝基板製法之流程剖面結 構示意圖。 圖3D’至3F’係本發明實施例3中封裝基板製法之部分流程 剖面結構示意圖。 1351,749 【主要元件符號說明】 10,20 基板本體 10a,20a 第一表面 10b，20b 第二表面 11,21 核心板 115,13,23 線路層 116 導電通孔 12,22 . 線路增層結構 130,230 焊球墊 131,231 凸塊焊墊 132,232 被動元件焊墊 137 導電盲孔 140,142 金屬層 141 金屬凸塊 16 防焊層 164,244,245,246 開孔 19, 29 表面處理層 220 介電層 229 導電晶種層 24 阻層 25 電鍍金屬凸塊 26 第一防焊層 263 開口區 264 第一開孔 28 第二防焊層 284 第二開孔 1710 15 When copper is used as the material of the plated metal bump, the package substrate may further comprise a surface treatment layer, which is disposed on the surface of the passive component soldering surface exposed by the first opening and (4) the surface of the metal bump, and extends to Cover the side surface of the bump pad. The material of the surface treatment layer can prevent physical or chemical damage of the plated metal bumps and the bump pads, and is preferably selected from the group consisting of nickel/gold organic solder masked nickel gold, nickel/bar/gold, tin, One of solder, error-free solder and silver. On the other hand, if tin is used as the material of the electric ore bump, the size of the electric φ metallized bump may be less than or equal to the bump pad, and may further include a surface treatment layer disposed on the first opening. The surface of the passive component pad and the surface of the plated metal bump are exposed and extend to cover the side surface of the bump pad. 2〇 Or, if tin is used as the material of the plated metal bump, the size of the plated metal bump may be larger than the bump pad and the bump pad is covered. In the above package substrate, the second surface of the substrate body has a plurality of solder ball pads, and a second solder resist layer is provided, and has a plurality of second openings to expose a part of the surface of the 1351749 solder ball pad. The package substrate further includes a surface treatment layer disposed on the surface of the solder ball pad exposed by the second opening. The invention also provides a method for manufacturing a package substrate, the method comprising: providing a substrate body having a first surface and a second surface, wherein the first surface has a circuit layer, and the circuit layer has a plurality of bumps a solder pad and a plurality of passive component pads, wherein the bump pads are arranged in an array; a resist layer is formed on the first surface of the substrate body, and a part of the surface of the plurality of open-hole exposed bump pads is formed on the resist layer Forming a plurality of electroplated copper bumps on the exposed holes of the resist layer and the exposed bumps; removing the resist layer; and forming a first solder resist layer on the surface of the substrate 10, and performing the first solder resist The layer forms an open area to expose the bump array area of the substrate body surface, and a plurality of first openings are formed in the first solder mask to expose a portion of the surface of the passive component pad. The above method can further include the surface of the passive component soldering 15 exposed by the first opening, and forming a surface treatment layer on the surface of the electroplated copper bump, and the surface treatment layer extends to cover the side surface of the bump pad. The material used for the surface treatment layer is not limited, as long as the electroplated copper bump and the bump pad are prevented from being physically or chemically damaged, preferably selected from the group consisting of gilt/gold organic solder masked nickel. & Gold, nickel / handle / gold, tin, solder, error-free solder and silver, one of two. The invention further provides a method for manufacturing a package substrate, the step of which includes: providing a substrate body having a first surface and a second surface, the first surface having a circuit layer having a plurality of convexities a solder pad and a plurality of passive component pads, wherein the bump soldering system is arranged in an array; on the base 1351749, a first solder mask is formed on the surface of the body, and an open area is formed in the first solder resist layer to display Forming a bump pad array region on the surface of the substrate body, and forming a plurality of first openings in the solder resist layer to expose a portion of the surfaces of the passive component pads; forming a resistor on the first surface of the substrate body And forming a plurality of openings in the 5 resist layer to expose the bump pads; forming a plurality of plated tin bumps on the exposed bumps of the resist layer and the exposed bump pads; and removing the resist layer . In the above method, the size of the opening of the resist layer is not limited. 'This is to expose the bump solder joints. 'If the opening size of the resist layer is larger than the bump soldering ί 塾 ' ' can make the electric bell tin bump package Overlay bumps prevent physical or chemical damage to the bump pads. On the other hand, if the size of the opening of the resist layer is less than or equal to the bump pad, it may further include a step of: forming a surface of the passive component pad exposed on the first opening and forming a surface on the surface of the electroplated tin bump A tin layer that extends to cover the side surface of the bump pad. Similarly, the tin layer can prevent the bump pads from being physically or chemically damaged. In summary, the package substrate provided by the present invention and the method for manufacturing the same are provided because the surface of the bump is provided with an electric metal. Bumps, such as copper, reduce the total amount of solder to reduce cost. On the other hand, since the plated metal bump is directly bonded to the electrical connection pad or even the dielectric layer around it, the bonding force is superior to the bonding force with the solder resist layer, thereby reducing the insufficiency of the contact strength. The contacts are broken to increase the reliability of the package substrate. In addition, the solder resist layer has an open area to expose the bump pad array area of the first surface of the substrate body, thereby preventing the glue material from being completely filled in the gap between the package substrate and the wafer when filling the bottom adhesive material. problem. Furthermore, since the surface treatment layer is extended to cover the side surface of the bump pad of the 1351749, the plated metal bump and the bump pad can be prevented from being physically or chemically damaged; if the plated metal bump material is tin The size of the bump 5 can be prevented from being physically or chemically affected by the bump pad, the bump pad i, or the tin pad covering the side surface of the bump pad. damage. [Embodiment] The following embodiments are described by way of specific embodiments, and those skilled in the art can readily understand the other advantages and advantages of the invention. The present invention may be embodied or applied in various other specific embodiments, and various modifications and changes may be made without departing from the spirit and scope of the invention. Embodiment 1 15 First, please refer to Figs. 2A to 2E, which are cross-sectional views showing the manufacturing process of the package substrate of the present invention. As shown in Fig. 2A, a substrate body 20 is provided having a first surface 20a and a second surface 20b. The first surface 20a has a wiring layer 23 having a plurality of bump pads 231 and a plurality of passive component pads 2, and the bump pads 231 are arranged in an array. The second surface 20b has a plurality of solder ball pads 230. The substrate body 20 is formed on a core board 21 and its two sides by a line build-up technology to form a line build-up structure 22, and the line build-up structure 22 is formed prior to the core board 21 and its two sides. A dielectric layer 220 is formed, and a conductive seed layer 229 is formed on the surface of the dielectric layer 220. The conductive layer 229 is electrically conductive to form the wiring layer 23 by electric ore. The material of the conductive seed layer 229 may be one of a group of copper, tin, stellite, complex, titanium, copper-chromium alloy and tin-lead alloy, which in this embodiment is copper 0 • 5 Then, a resist layer 24 is formed on the first surface 20a of the substrate body 20, and a plurality of openings 244 are formed in the resist layer 24 to expose portions of the bump pads 231. The material used for the resist layer 24 may be a dry film or a liquid photoresist or the like. Then, referring to FIG. 2B, a plurality of plated metal bumps 25 are formed on the surfaces of the bumps 244 and the bump pads 231 on which they are exposed. The electroplated metal 10 bumps 25 may be selected from one of alloys of tin, silver, copper, gold, ruthenium, 'recorded, zinc, recorded, wrong, magnesium, indium, gallium, and the above metals. For example, copper is used. As shown in FIG. 2C, the resist layer 24 and its covered conductive seed layer 229 are removed. Referring to FIG. 2D, a first anti-15 solder layer 26 is formed on the first surface 20a of the substrate body 20, the height of which is lower than the height of the plated metal bumps 25, and a second solder resist layer is formed on the second surface 20b. 28. An opening region 263 is formed on the first solder resist layer 26 to expose the array region 1 of the bump pad 231 on the surface of the substrate body 20, and a plurality of first openings 264 are formed in the first solder resist layer 26 to reveal the Part of the surface of the passive component pads 232. Similarly, a plurality of second openings 284 are formed in the second solder mask 28 to expose portions of the solder ball pads 230. Then, as shown in FIG. 2E, the surface of the passive component pad 232 exposed by the first opening 264 and the second opening 284 are exposed by physical deposition such as sputtering and evaporation, or chemical deposition such as electroless plating. The surface of the ball pad 230, the surface of the plated metal bump 25, and the side surface exposed by the bump pad 231 are all formed into a surface treatment layer 29 of the table 12,351, which is the package substrate of the present invention. The surface treatment layer 29 may be made of tin, silver, nickel, gold, chromium/titanium, nickel/gold, nickel/palladium, nickel/palladium/gold, organic solder mask, nickel immersion gold, solder, and lead-free. One of the solders. The present invention provides a package substrate, as shown in FIG. 2D, comprising: a substrate body 20 having a first surface 20a and a second surface 20b, the first surface 20a having a circuit layer 23, The circuit layer 23 has a plurality of bump pads 231 and a plurality of passive component pads 232, wherein the bump pads f 231 are arranged in an array; a plurality of plated metal bumps 25 are disposed on the bumps 10 pads. 231 surface; and a first solder resist layer 26 is disposed on the first surface 20a, the first solder resist layer 26 has an opening region 263 to expose the array area of the bump pads 23.1 of the first surface 20a of the substrate body 20, The first solder mask 26 has a plurality of first openings 264 to expose portions of the surface of the passive component pads 232. The package substrate described above, wherein the plated metal bumps 25 are higher than the first solder resist layer 26. The package substrate may include a surface treatment layer 29, as shown in FIG. 2E, disposed on the surface of the passive component pad 232 exposed by the first openings 264, and disposed on the plated metal bumps. The surface of the block 25 extends while covering the exposed side surface of the bump pad 231. In the above package substrate, the second surface 20b of the substrate body 20 has a plurality of solder ball pads 230, and is provided with a second solder mask 28 having a plurality of second openings 284 to expose the solder ball pads 230. A portion of the surface of the solder ball pad 230 exposed by the second openings 284 may be further included in the package substrate. 13 25 1351749 Embodiment 2 This embodiment provides another method of fabricating the package substrate of the present invention. Please refer to FIG. 3A to FIG. 3F , which are cross-sectional views showing the manufacturing process of the package substrate of the present invention. As shown in Fig. 3A, a substrate body 20 is provided which has a pair of a fifth surface 20a and a second surface 2 Ob. The first surface 20a has a wiring layer 23 having a plurality of bump pads 231 and a plurality of passive component pads 232, and the bump pads 231 are arranged in an array. The second surface 20b has a plurality of solder ball pads 230. The manufacturing method of the substrate body 20 can be referred to the embodiment i 1, and will not be described again. 10 Next, referring to FIG. 3A, a first solder resist layer 26 is formed on the first surface 20a of the substrate body 20, and a second solder resist layer 28 is formed on the second surface 20b. Then, as shown in FIG. 3B, an opening region 263 and a plurality of first openings 264 are formed in the first solder resist layer 26 to respectively expose the array regions of the bump pads 231 on the first surface 20a of the substrate body 20 and Passive component pad 15 232. At the same time, a plurality of second openings 284 are formed in the second solder resist layer 28 for exposing the solder ball pads 230 on the second surface 20b of the substrate body 20. As shown in FIG. 3C, a conductive seed layer 229 is formed to cover the first surface 20a and the second surface 20b of the substrate body 20 1 , that is, to cover the surface of the first solder resist 26 and the first solder resist 26 . The array of bump pads 20 231 exposed by the opening region 263, the passive component pad 232 exposed by the first opening 264 of the first solder resist layer 26, the surface of the second solder resist layer 28, and the second solder resist Floor? The solder ball pad 230 exposed by the second opening 284 of 8. Next, referring to FIG. 3D, a resist layer 24 is formed on both surfaces of the first solder resist layer 26 and the second solder resist layer 28 to cover both of them. The conductive layer 229 on the surface of the bump pad 231 is exposed in the plurality of openings 244 in the resist layer 24 shape 1351749. Moreover, the size of the opening 244 is smaller than the size of the bump pad 231. As shown in FIG. 3E, the conductive seed layer '229, which is exposed by the openings 244, conducts current, and a plurality of plated metal bumps are formed in the openings 244. This embodiment uses tin as a material. In this embodiment, the height of the metal metal bump 25 is higher than the height of the first solder resist layer 26. Further, as shown in Fig. 3F, the resist layer 24 and the conductive seed layer 229 covered thereunder are removed. Similarly, in the manner similar to that described in Embodiment 1, the surface of the passive component pad 232 exposed by the first opening 264, the surface of the solder ball pad 230 exposed by the second opening 284, and the surface of the plated metal bump 25 are also used. And the exposed side surfaces of the bump pads 231 form a surface treatment layer 29, that is, the package substrate of the present invention is completed. The material used for the surface treatment layer 29 may be selected as described in Embodiment 1, and the present embodiment is tin, yttrium to completely protect the electroplated metal bumps 25 and the bump pads 231 15 . A method of making the package substrate of the present invention is provided.制 The preparation method is similar to that described in Embodiment 2, but the main differences are as follows. First, the steps of Fig. 3A to Fig. 3C of Embodiment 2 are repeated. Next, as shown in FIG. 3D', a resist layer 24 is formed on the surfaces of the first solder resist layer 26 and the second solder resist layer 28, and a plurality of openings 244 are formed in the resist layers 24 to reveal The bump pads 231 and the plurality of openings 246 are formed to expose the first opening 264 of the first solder resist layer 26 and the exposed passive component pads 232 and the plurality of openings 245 to expose the second solder resist layer 28 The second opening 284 and the conductive pad layer 229 on the surface of the solder ball 25 pad 230 and the like are exposed. Moreover, the size 15 1351749 of the opening 24 is larger than the size of the bump pads 231, and the size of the opening 246 is larger than the size of the first opening 264 of the first solder resist layer 26, and the size of the opening 245 is larger than The size of the second opening 284 of the second solder resist layer 28. Further, as shown in Fig. 3E', the conductive seed 5 layer 229 which is exposed in the previous step is turned on, and electroplated in the openings 244, 245, 246 to form a plurality of plated metal bumps 25. This embodiment uses tin as a material, but other materials such as those exemplified in the examples may be optionally used. The height of the metal bumps 25 may be slightly higher than the height of the first solder resist layer 26. In this embodiment, the bump pads 23 j are plated with metal bumps 25 covering the upper surface of the bump pads 231 and the side 10 surfaces to completely protect the bump pads 231. Further, as shown in Fig. 3F', the resist layer 24 and the conductive seed layer 229 covered thereunder are removed, i.e., the package substrate of the present invention is completed. The above-described embodiments are merely examples for convenience of description, and the scope of the claims of the present invention is determined by the application of the patent application, and is not limited to the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic cross-sectional view of a conventional package substrate. 2A to 2E are schematic views showing a flow cross-sectional structure of a method for manufacturing a package substrate in the first embodiment of the present invention. 3A to 3F are schematic cross-sectional views showing the flow of a method for manufacturing a package substrate in Embodiment 2 of the present invention. 3D to 3F are schematic cross-sectional structural views showing a part of the flow of the package substrate in the third embodiment of the present invention. 1351,749 [Description of main component symbols] 10,20 substrate body 10a, 20a first surface 10b, 20b second surface 11, 21 core plate 115, 13, 23 circuit layer 116 conductive via 12, 22 . 130,230 solder ball pads 131,231 bump pads 132,232 passive component pads 137 conductive blind holes 140,142 metal layer 141 metal bumps 16 solder mask 164,244,245,246 openings 19, 29 surface treatment layer 220 dielectric layer 229 conductive seed layer 24 resist layer 25 electroplated metal bump 26 first solder resist layer 263 open area 264 first opening 28 second solder resist layer 284 second opening 17