TWI402955B - Chip package structure and package substrate - Google Patents
Chip package structure and package substrate Download PDFInfo
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- TWI402955B TWI402955B TW99111124A TW99111124A TWI402955B TW I402955 B TWI402955 B TW I402955B TW 99111124 A TW99111124 A TW 99111124A TW 99111124 A TW99111124 A TW 99111124A TW I402955 B TWI402955 B TW I402955B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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Description
本發明是有關於一種晶片封裝技術，且特別是有關於一種封裝基板及採用此封裝基板的晶片封裝結構。The present invention relates to a chip packaging technology, and more particularly to a package substrate and a chip package structure using the package substrate.
目前在半導體封裝技術中，封裝基板(package substrate)是經常使用的構裝元件之一。封裝基板包括多層圖案化線路層(patterned conductive layer)以及多層介電層(dielectric layer)交替疊合而成，且兩線路層之間可透過導電孔(conductive via)而彼此電性連接。兩最外層的圖案化導電層具有多個接墊。封裝基板更具有兩分別覆蓋兩最外層圖案化導電層的防銲層(solder mask layer)，而這些防銲層具有多個開口，且這些開口分別暴露出這些接墊的一部分，用以定義出接墊的接合區域。Currently, in semiconductor packaging technology, a package substrate is one of the components that are often used. The package substrate comprises a plurality of patterned conductive layers and a plurality of dielectric layers alternately stacked, and the two circuit layers are electrically connected to each other through a conductive via. The two outermost patterned conductive layers have a plurality of pads. The package substrate further has two solder mask layers respectively covering the two outermost patterned conductive layers, and the solder resist layers have a plurality of openings, and the openings respectively expose a part of the pads for defining The joint area of the pads.
晶片可透過覆晶接合(flip chip bonding)或打線接合(wire bonding)等方式組裝至封裝基板，以形成一晶片封裝結構。此外，封裝基板更可經由多個銲球(solder ball)組裝至外部元件(例如是印刷電路板)，其中銲球是配置於封裝基板的接墊上。然而，當接墊的接合區域是由防銲層的開口所定義，即接墊為銲罩定義(Solder Mask Defined，SMD)型的接墊時，銲球僅與部分的接墊表面相接合。因此，銲球可能無法穩固地附著於接墊上，因而影響晶片封裝結構的可靠度。此外，基於不同封裝基板的結構需求，在製程上亦需要對應的調整。The wafer can be assembled to the package substrate by flip chip bonding or wire bonding to form a chip package structure. In addition, the package substrate can be assembled to an external component (for example, a printed circuit board) via a plurality of solder balls, wherein the solder balls are disposed on pads of the package substrate. However, when the bonding area of the pad is defined by the opening of the solder resist layer, that is, the pad is a pad of the Solder Mask Defined (SMD) type, the solder ball is only engaged with a part of the pad surface. Therefore, the solder balls may not be firmly attached to the pads, thus affecting the reliability of the chip package structure. In addition, based on the structural requirements of different package substrates, corresponding adjustments are also required in the process.
本發明提供一種封裝基板，具有較佳的可靠度。The invention provides a package substrate with better reliability.
本發明提供一種晶片封裝結構，其採用上述之封裝基板，具有較佳的可靠度。The invention provides a chip package structure which adopts the above package substrate and has better reliability.
本發明更提出一種晶片封裝結構，適於放置在一承載器上。晶片封裝結構包括一封裝基板及一晶片。封裝基板包括一疊合層、一圖案化導電層、一防銲層、至少一外部接墊及一墊高圖案。疊合層具有彼此相對的一第一表面與一第二表面。圖案化導電層配置於疊合層的第一表面上，且具有至少一內部接墊。防銲層配置於疊合層的第一表面上，且具有至少一開口，其中開口暴露出內部接墊。外部接墊配置於防銲層上且位於開口內，其中外部接墊與開口所暴露出的內部接墊連接。墊高圖案配置於防銲層上。墊高圖案相對於疊合層之第一表面的高度大於外部接墊相對於疊合層之第一表面的高度。當封裝基板經由墊高圖案放置在承載器上時，外部接墊不接觸承載器。晶片配置於封裝基板上，位於疊合層的第二表面，且電性連接至封裝基板。The invention further provides a chip package structure suitable for placement on a carrier. The chip package structure includes a package substrate and a wafer. The package substrate includes a laminated layer, a patterned conductive layer, a solder resist layer, at least one external pad, and a pad pattern. The laminated layer has a first surface and a second surface opposite to each other. The patterned conductive layer is disposed on the first surface of the laminated layer and has at least one internal pad. The solder resist layer is disposed on the first surface of the laminated layer and has at least one opening, wherein the opening exposes the inner pad. The external pads are disposed on the solder resist layer and are located in the openings, wherein the external pads are connected to the internal pads exposed by the openings. The padding pattern is disposed on the solder resist layer. The height of the pad pattern relative to the first surface of the overlay layer is greater than the height of the outer pad relative to the first surface of the overlay layer. When the package substrate is placed on the carrier via the padding pattern, the external pads do not contact the carrier. The wafer is disposed on the package substrate, is located on the second surface of the laminated layer, and is electrically connected to the package substrate.
本發明還提出一種晶片封裝結構，適於連接一電子元件。晶片封裝結構包括一封裝基板、一晶片及至少一銲球。封裝基板包括一疊合層、一圖案化導電層、一防銲層、至少一外部接墊及一墊高圖案。疊合層具有彼此相對的一第一表面與一第二表面。圖案化導電層配置於疊合層的第一表面上，且具有至少一內部接墊。防銲層配置於疊合層的第一表面上，且具有至少一開口，其中開口暴露出內部接墊。外部接墊配置於防銲層上且位於開口內，其中外部接墊與開口所暴露出的內部接墊連接。墊高圖案配置於防銲層上，其中墊高圖案相對於疊合層之第一表面的高度大於外部接墊相對於疊合層之第一表面的高度。晶片配置於封裝基板上，位於疊合層的第二表面，且電性連接至封裝基板。銲球連接外部接墊，且當封裝基板經由銲球連接電子元件時，墊高圖案不接觸電子元件。The present invention also provides a chip package structure suitable for connecting an electronic component. The chip package structure includes a package substrate, a wafer, and at least one solder ball. The package substrate includes a laminated layer, a patterned conductive layer, a solder resist layer, at least one external pad, and a pad pattern. The laminated layer has a first surface and a second surface opposite to each other. The patterned conductive layer is disposed on the first surface of the laminated layer and has at least one internal pad. The solder resist layer is disposed on the first surface of the laminated layer and has at least one opening, wherein the opening exposes the inner pad. The external pads are disposed on the solder resist layer and are located in the openings, wherein the external pads are connected to the internal pads exposed by the openings. The pad pattern is disposed on the solder resist layer, wherein a height of the pad pattern relative to the first surface of the overlay layer is greater than a height of the external pad relative to the first surface of the overlay layer. The wafer is disposed on the package substrate, is located on the second surface of the laminated layer, and is electrically connected to the package substrate. The solder balls connect the external pads, and when the package substrate is connected to the electronic components via the solder balls, the pad pattern does not contact the electronic components.
本發明提出一種封裝基板，其包括一疊合層、一圖案化導電層、一防銲層、至少一外部接墊及一墊高圖案。疊合層具有一表面。圖案化導電層配置於疊合層的表面上，且具有至少一內部接墊。防銲層配置於疊合層的表面上，且具有至少一開口，其中開口暴露出內部接墊。外部接墊配置於防銲層上且位於開口內，其中外部接墊與開口所暴露出的內部接墊連接。墊高圖案配置於防銲層上，其中墊高圖案相對於疊合層之表面的高度大於外部接墊相對於疊合層之表面的高度。The invention provides a package substrate comprising a laminated layer, a patterned conductive layer, a solder resist layer, at least one external pad and a pad pattern. The laminated layer has a surface. The patterned conductive layer is disposed on the surface of the laminated layer and has at least one internal pad. The solder resist layer is disposed on the surface of the laminated layer and has at least one opening, wherein the opening exposes the inner pad. The external pads are disposed on the solder resist layer and are located in the openings, wherein the external pads are connected to the internal pads exposed by the openings. The pad pattern is disposed on the solder resist layer, wherein the height of the pad pattern relative to the surface of the overlay layer is greater than the height of the outer pad relative to the surface of the overlay layer.
基於上述，本發明之封裝基板具有與內部接墊相連接的外部接墊，因此可增加銲球與接墊的接觸面積，以提升銲球銲接至封裝基板後的可靠度。此外，本發明之封裝基板亦具有墊高圖案，且此墊高圖案相對於疊合層之表面的高度大於外部接墊相對於疊合層之表面的高度。因此，當封裝基板經由墊高圖案放置在承載器上時，可避免外部接墊接觸承載器，以提升晶片組裝至封裝基板後的可靠度。Based on the above, the package substrate of the present invention has an external pad connected to the inner pad, so that the contact area of the solder ball and the pad can be increased to improve the reliability of the solder ball after soldering to the package substrate. In addition, the package substrate of the present invention also has a pad pattern, and the height of the pad pattern relative to the surface of the laminate layer is greater than the height of the outer pad relative to the surface of the laminate layer. Therefore, when the package substrate is placed on the carrier via the padding pattern, the external pads can be prevented from contacting the carrier to improve the reliability after the wafer is assembled to the package substrate.
為讓本發明之上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。The above described features and advantages of the present invention will be more apparent from the following description.
圖1A為本發明之一實施例之一種晶片封裝結構的剖面示意圖。圖1B為圖1A之封裝基板的仰視示意圖。請先參考圖1A，晶片封裝結構20包括一封裝基板100及一晶片200，而晶片200組裝至封裝基板100上。特別是，在本實施例中，封裝基板100或是已組裝晶片200的晶片封裝結構20適於放置在承載器10上，此承載器10例如是作為製程中輸送搬運之用的承載器。1A is a cross-sectional view showing a chip package structure according to an embodiment of the present invention. FIG. 1B is a bottom view of the package substrate of FIG. 1A. Referring first to FIG. 1A, the chip package structure 20 includes a package substrate 100 and a wafer 200, and the wafer 200 is assembled onto the package substrate 100. In particular, in the present embodiment, the package substrate 100 or the wafer package structure 20 of the assembled wafer 200 is adapted to be placed on a carrier 10, such as a carrier for transport handling in a process.
封裝基板100包括一疊合層110、一圖案化導電層120、一防銲層130、至少一外部接墊140(圖1A中示意地繪示多個)及一墊高圖案150(圖1A中示意地繪示二個)。疊合層110具有一第一表面112與相對於第一表面112的一第二表面114。在本實施例中，疊合層110是由多個圖案化導電層113與多個介電層115交替疊合而成，且這些圖案化導電層113之間可透過至少一導電孔117而彼此電性連接。The package substrate 100 includes a stacked layer 110, a patterned conductive layer 120, a solder resist layer 130, at least one external pad 140 (shown schematically in FIG. 1A), and a pad pattern 150 (FIG. 1A) Two are shown schematically. The laminate layer 110 has a first surface 112 and a second surface 114 opposite the first surface 112. In this embodiment, the laminated layer 110 is formed by alternately laminating a plurality of patterned conductive layers 113 and a plurality of dielectric layers 115, and the patterned conductive layers 113 are transparent to each other through at least one conductive hole 117. Electrical connection.
外層的圖案化導電層120配置於疊合層110的第一表面112上，且此外層的圖案化導電層120具有至少一內部接墊122(圖1A中示意地繪示多個)。防銲層130配置於疊合層110的第一表面112上，且防銲層130具有至少一開口132(圖1A中示意地繪示多個)，其中這些開口132分別暴露出對應的這些內部接墊122。這些外部接墊140配置於防銲層130上且位於對應的這些開口132內，其中這些外部接墊140與相對應之這些開口132所暴露出的這些內部接墊122在結構上及電性上連接。The outer patterned conductive layer 120 is disposed on the first surface 112 of the stacked layer 110, and the patterned conductive layer 120 of the outer layer has at least one inner pad 122 (a plurality of which are schematically illustrated in FIG. 1A). The solder resist layer 130 is disposed on the first surface 112 of the laminated layer 110, and the solder resist layer 130 has at least one opening 132 (shown schematically in FIG. 1A), wherein the openings 132 respectively expose the corresponding inner portions Pad 122. The external pads 140 are disposed on the solder resist layer 130 and are located in the corresponding openings 132. The external pads 140 are structurally and electrically connected to the internal pads 122 exposed by the corresponding openings 132. connection.
在本實施例中，每一外部接墊140包括一主體部142與一金屬保護層144，其中這些主體部142分別與這些內部接墊122連接，而這些金屬保護層144分別覆蓋這些主體部142所暴露出的表面，用以作為這些主體部142的抗氧化層。此處所述之這些金屬保護層144例如是鎳/金層、鎳/鈀/金層、鎳/錫層、鈀層、金層或其他適當的金屬，在此並不加以限制。In this embodiment, each of the external pads 140 includes a body portion 142 and a metal protection layer 144, wherein the body portions 142 are respectively connected to the internal pads 122, and the metal protection layers 144 cover the body portions 142, respectively. The exposed surface serves as an antioxidant layer for these body portions 142. The metal protective layer 144 described herein is, for example, a nickel/gold layer, a nickel/palladium/gold layer, a nickel/tin layer, a palladium layer, a gold layer or other suitable metal, which is not limited herein.
這些墊高圖案150配置於疊合層110的第一表面112上。在本實施例中，這些墊高圖案150配置於防銲層130上。特別是，這些墊高圖案150相對於疊合層110之第一表面112的高度H1大於這些外部接墊140相對於疊合層110之第一表面112的高度H2。換言之，相對於疊合層110的第一表面112，這些墊高圖案150的頂面是高於外部接墊140的頂面。因此，當封裝基板100經由這些墊高圖案150放置在承載器10上時，這些外部接墊140不會接觸承載器10，意即外部接墊140與承載器10之間存有一間隔距離D1。取而代之的，是由這些墊高圖案150與承載器10接觸。這些外部接墊140為導電結構，並且基於設計的需求會與外層的圖案化導電層120、疊合層110的多個圖案化導電層113、晶片200電性連接。若承載器10(例如：用於製程輸送的承載器)上存有靜電電流或是其他非預期的電流，透過這些墊高圖案150的配置，則可以有效避免因這些外部接墊140與承載器10接觸，而使靜電電流或是其他非預期的電流透過外部接墊140、外層的圖案化導電層120、疊合層110的多個圖案化導電層113而導通至晶片200，進而造成晶片200損傷的問題。These padding patterns 150 are disposed on the first surface 112 of the laminated layer 110. In the present embodiment, the pad pattern 150 is disposed on the solder resist layer 130. In particular, the height H1 of the pad pattern 150 relative to the first surface 112 of the overlay 110 is greater than the height H2 of the outer pads 140 relative to the first surface 112 of the overlay 110. In other words, the top surface of the pad pattern 150 is higher than the top surface of the outer pad 140 with respect to the first surface 112 of the overlay 110. Therefore, when the package substrate 100 is placed on the carrier 10 via the padding patterns 150, the external pads 140 do not contact the carrier 10, that is, there is a separation distance D1 between the external pads 140 and the carrier 10. Instead, these padding patterns 150 are in contact with the carrier 10. The external pads 140 are electrically conductive structures and are electrically connected to the patterned conductive layer 120 of the outer layer, the plurality of patterned conductive layers 113 of the stacked layer 110, and the wafer 200 based on design requirements. If the carrier 10 (for example, the carrier for process delivery) has an electrostatic current or other unintended current, the configuration of the pad pattern 150 can effectively avoid the external pads 140 and the carrier. 10 contacting, and causing an electrostatic current or other unintended current to pass through the external pad 140 , the patterned conductive layer 120 of the outer layer, and the plurality of patterned conductive layers 113 of the stacked layer 110 to conduct to the wafer 200, thereby causing the wafer 200 The problem of damage.
請參考圖1B，在本實施例中，這些墊高圖案150包括多個墊高點152(圖1B中僅示意地繪示四個)，其中這些墊高點152分別分佈於防銲層130的多個角落134(圖1B中僅示意地繪示四個)。也就是說，本實施例之這些墊高圖案150是呈現點狀分佈或非連續分佈的型態分佈於防銲層130的這些角落134上。此外，在其他未繪示的實施例中，這些墊高圖案150亦可呈現連續分佈的型態分佈於防銲層130的周圍，例如這些墊高圖案150為條狀分佈、或是點狀與條狀的組合來分佈。換言之，本發明在此並不限定的這些墊高圖案150的結構形態，已知的其他能達到同等提升封裝基板100之可靠度的結構設計，仍屬於本發明可採用的技術方案，不脫離本發明所欲保護的範圍。此外，這些墊高圖案150的材質例如是防銲材料。Referring to FIG. 1B , in the embodiment, the pad pattern 150 includes a plurality of pad points 152 (only four are schematically shown in FIG. 1B ), wherein the pad height points 152 are respectively distributed on the solder resist layer 130 . A plurality of corners 134 (only four are shown schematically in FIG. 1B). That is to say, the pad pattern 150 of the present embodiment is distributed on the corners 134 of the solder resist layer 130 in a pattern in which a dot distribution or a discontinuous distribution is present. In addition, in other embodiments not shown, the pad patterns 150 may also be distributed in a continuously distributed pattern around the solder resist layer 130. For example, the pad patterns 150 are strip-shaped or dot-shaped. A combination of strips is distributed. In other words, the structural form of the pad pattern 150, which is not limited herein, and other structural designs that can achieve the same reliability of the package substrate 100 are still applicable to the technical solution of the present invention. The scope of the invention to be protected. Further, the material of these pad pattern 150 is, for example, a solder resist material.
晶片200位於疊合層110的第二表面114，且電性連接至封裝基板100。在本實施例中，封裝基板100更包括一防銲層160，其配置於疊合層110的第二表面114上，且防銲層160具有至少一開口162(圖1A中示意地繪示多個)，其中這些開口162分別暴露出配置於第二表面114的部份圖案化導電層113。The wafer 200 is located on the second surface 114 of the laminated layer 110 and is electrically connected to the package substrate 100. In this embodiment, the package substrate 100 further includes a solder resist layer 160 disposed on the second surface 114 of the laminated layer 110, and the solder resist layer 160 has at least one opening 162 (shown schematically in FIG. 1A And wherein the openings 162 respectively expose a portion of the patterned conductive layer 113 disposed on the second surface 114.
晶片封裝結構20更包括多個凸塊210及一封裝膠體220，其中這些凸塊210配置於晶片200與封裝基板100之間且分別位於這些開口162所暴露出的部份圖案化導電層113上，而晶片200透過這些凸塊210與封裝基板100相電性連接。此外，封裝膠體220填充於晶片200與封裝基板100之間，且封裝膠體220包覆這些凸塊210。The chip package structure 20 further includes a plurality of bumps 210 and an encapsulant 220. The bumps 210 are disposed between the wafer 200 and the package substrate 100 and are respectively located on the partially patterned conductive layer 113 exposed by the openings 162. The wafer 200 is electrically connected to the package substrate 100 through the bumps 210. In addition, the encapsulant 220 is filled between the wafer 200 and the package substrate 100, and the encapsulant 220 covers the bumps 210.
基於上述，在本實施例中，晶片200以覆晶接合(flip chip bonding)的方式電性連接至封裝基板100。在另一未繪示實施例中，晶片200可以打線接合(wire bonding)或其他的方式電性連接至封裝基板100。Based on the above, in the present embodiment, the wafer 200 is electrically connected to the package substrate 100 in a flip chip bonding manner. In another embodiment, the wafer 200 can be electrically connected to the package substrate 100 by wire bonding or other means.
由於本實施例之封裝基板100具有分別與這些內部接墊122連接的這些外部接墊140，因此相對於習知由防銲層之開口所定義的接墊區域而言，本實施例之配置於防銲層130上的這些外部接墊140可具有較大的接墊面積。Since the package substrate 100 of the present embodiment has the external pads 140 respectively connected to the internal pads 122, the configuration of the present embodiment is configured with respect to the pad region defined by the opening of the solder resist layer. These external pads 140 on the solder mask layer 130 can have a larger pad area.
此外，由於本實施例之封裝基板100具有這些墊高圖案150，且這些墊高圖案150相對於疊合層110之第一表面112的高度大於這些外部接墊140相對於疊合層110之第一表面112的高度(即這些墊高圖案150的頂面高於這些外部接墊140的頂面)。因此，當封裝基板100經由這些墊高圖案150放置在承載器10上時，可避免這些外部接墊140接觸承載器10，以降低靜電電流或是其他非預期的電流經由外部接墊140而導入晶片200的可能性，因而提升晶片200組裝至封裝基板100後的可靠度。In addition, since the package substrate 100 of the embodiment has the pad pattern 150, and the height of the pad pattern 150 relative to the first surface 112 of the layer 110 is greater than the number of the external pads 140 relative to the layer 110 The height of a surface 112 (i.e., the top surface of the pad pattern 150 is higher than the top surface of the outer pads 140). Therefore, when the package substrate 100 is placed on the carrier 10 via the padding patterns 150, the external pads 140 can be prevented from contacting the carrier 10 to reduce electrostatic current or other unintended currents introduced through the external pads 140. The possibility of the wafer 200 thus improves the reliability of the wafer 200 after assembly to the package substrate 100.
圖2為本發明之另一實施例之一種晶片封裝結構的剖面示意圖。本實施例沿用前述實施例的元件標號與部分內容，其中採用相同的標號來表示相同或近似的元件，並且省略了相同技術內容的說明。關於省略部分的說明可參照前述實施例，本實施例不再重複贅述。2 is a cross-sectional view showing a chip package structure according to another embodiment of the present invention. The same reference numerals are used to denote the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted portions, reference may be made to the foregoing embodiments, and the detailed description is not repeated herein.
請參考圖2，本實施例的晶片封裝結構30與前述實施例之晶片封裝結構20相似，其主要的差異在於：圖2之晶片封裝結構30更包括至少一銲球300(圖2中示意地繪示多個)，其中這些銲球300分別連接至這些外部接墊140，以透過這些銲球300與外部元件相電性連接。Referring to FIG. 2, the chip package structure 30 of the present embodiment is similar to the chip package structure 20 of the previous embodiment. The main difference is that the chip package structure 30 of FIG. 2 further includes at least one solder ball 300 (shown schematically in FIG. 2). A plurality of solder balls 300 are respectively connected to the external pads 140 to be electrically connected to the external components through the solder balls 300.
詳細來說，這些墊高圖案150相對於疊合層110之第一表面112的高度H1小於這些銲球300相對於疊合層110之第一表面112的高度H3。換言之，相對於疊合層110之第一表面112，這些墊高圖案150的頂面低於這些銲球300的頂面。在依實施例中，這些墊高圖案150相對於防銲層130的高度至少小於這些銲球300相對於防銲層130的高度的1/2。因此，當晶片封裝結構30之銲球300與外部之一電子元件12欲連接時，這些墊高圖案150不會與外部之電子元件12接觸，意即墊高圖案150與外部之電子元件12之間存有一間隔距離D2，故不會影響銲球300與外部之電子元件12的接合。在一實施例中，外部之電子元件12例如是一電路基板、一電子封裝體或是其他的電子元件。In detail, the height H1 of the pad pattern 150 relative to the first surface 112 of the overlay layer 110 is less than the height H3 of the solder balls 300 relative to the first surface 112 of the overlay layer 110. In other words, the top surface of the pad pattern 150 is lower than the top surface of the solder balls 300 with respect to the first surface 112 of the overlay layer 110. In an embodiment, the height of the pad pattern 150 relative to the solder mask 130 is at least less than 1/2 the height of the solder balls 300 relative to the solder mask 130. Therefore, when the solder ball 300 of the chip package structure 30 and one of the external electronic components 12 are to be connected, the pad pattern 150 does not contact the external electronic component 12, that is, the pad pattern 150 and the external electronic component 12 are There is a spacing distance D2 therebetween, so that the bonding of the solder ball 300 to the external electronic component 12 is not affected. In one embodiment, the external electronic component 12 is, for example, a circuit substrate, an electronic package, or other electronic component.
綜上所述，由於本實施例之封裝基板具有分別與這些內部接墊相連接的這些外部接墊，因此相對於習知由防銲層之開口所定義的接墊區域而言，本實施例之每一銲球與對應的外部接墊可具有較大接觸面積，故可提升銲球組裝至封裝基板後的可靠度。此外，本發明之封裝基板具有這些墊高圖案，且這些墊高圖案相對於疊合層之表面的高度大於這些外部接墊相對於疊合層之表面的高度。因此，當封裝基板經由這些墊高圖案放置在承載器上時，可避免這些外部接墊接觸承載器，可提升晶片封裝至封裝基板後的可靠度。另外，本發明之封裝基板具有這些墊高圖案，且這些墊高圖案相對於疊合層之表面的高度小於這些銲球相對於疊合層之表面的高度。因此，當封裝基板經由這些銲球與外部之電子元件連接時，這些墊高圖案的配置不會影響這些銲球與外部之電子元件的接合。In summary, since the package substrate of the embodiment has the external pads respectively connected to the internal pads, the embodiment is different from the pad region defined by the opening of the solder resist layer. Each of the solder balls and the corresponding external pads can have a large contact area, thereby improving the reliability of the solder balls after assembly to the package substrate. Furthermore, the package substrate of the present invention has these pad patternes, and the height of the pad pattern relative to the surface of the laminate layer is greater than the height of the outer pads relative to the surface of the laminate layer. Therefore, when the package substrate is placed on the carrier via the padding patterns, the external pads can be prevented from contacting the carrier, and the reliability after the chip package is packaged to the package substrate can be improved. In addition, the package substrate of the present invention has these pad patternes, and the height of the pad pattern relative to the surface of the laminate layer is less than the height of the solder balls relative to the surface of the laminate layer. Therefore, when the package substrate is connected to the external electronic components via the solder balls, the arrangement of the pad pattern does not affect the bonding of the solder balls to the external electronic components.
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，故本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.
10．．．承載器10. . . Carrier
12．．．電子元件12. . . Electronic component
20、30．．．晶片封裝結構20, 30. . . Chip package structure
100．．．封裝基板100. . . Package substrate
110．．．疊合層110. . . Laminated layer
112．．．第一表面112. . . First surface
113．．．導電層113. . . Conductive layer
114．．．第二表面114. . . Second surface
115．．．介電層115. . . Dielectric layer
117．．．導電孔117. . . Conductive hole
120．．．圖案化導電層120. . . Patterned conductive layer
122．．．內部接墊122. . . Internal pad
130、160．．．防銲層130, 160. . . Solder mask
132、162．．．開口132, 162. . . Opening
134．．．角落134. . . corner
140．．．外部接墊140. . . External pad
142．．．主體部142. . . Main body
144．．．金屬保護層144. . . Metal protective layer
150．．．墊高圖案150. . . Pad pattern
152．．．墊高點152. . . High point
200．．．晶片200. . . Wafer
210．．．凸塊210. . . Bump
220．．．封裝膠體220. . . Encapsulant
300．．．銲球300. . . Solder ball
D1、D2．．．間隔距離D1, D2. . . Spacing distance
H1、H2、H3．．．高度H1, H2, H3. . . height
圖1A為本發明之一實施例之一種晶片封裝結構的剖面示意圖。1A is a cross-sectional view showing a chip package structure according to an embodiment of the present invention.
圖1B為圖1A之封裝基板的仰視示意圖。FIG. 1B is a bottom view of the package substrate of FIG. 1A.
圖2為本發明之另一實施例之一種晶片封裝結構的剖面示意圖。2 is a cross-sectional view showing a chip package structure according to another embodiment of the present invention.
10．．．承載器10. . . Carrier
20．．．晶片封裝結構20. . . Chip package structure
100．．．封裝基板100. . . Package substrate
110．．．疊合層110. . . Laminated layer
112．．．第一表面112. . . First surface
113．．．導電層113. . . Conductive layer
114．．．第二表面114. . . Second surface
115．．．介電層115. . . Dielectric layer
117．．．導電孔117. . . Conductive hole
120．．．圖案化導電層120. . . Patterned conductive layer
122．．．內部接墊122. . . Internal pad
130．．．防銲層130. . . Solder mask
132、162．．．開口132, 162. . . Opening
140．．．外部接墊140. . . External pad
142．．．主體部142. . . Main body
144．．．金屬保護層144. . . Metal protective layer
150．．．墊高圖案150. . . Pad pattern
160．．．防銲層160. . . Solder mask
200．．．晶片200. . . Wafer
210．．．凸塊210. . . Bump
220．．．封裝膠體220. . . Encapsulant
D1．．．間隔距離D1. . . Spacing distance
H1、H2．．．高度H1, H2. . . height
Claims (13)
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| TWI700788B (en) * | 2019-05-02 | 2020-08-01 | 恆勁科技股份有限公司 | Flip-chip package substrate and its fabrication method |
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| TW200737472A (en) * | 2006-03-24 | 2007-10-01 | Chipmos Technologies Inc | Leadless semiconductor package with electroplated layer embedded in encapsualnt and the method for fabricating the same |
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| TW200737472A (en) * | 2006-03-24 | 2007-10-01 | Chipmos Technologies Inc | Leadless semiconductor package with electroplated layer embedded in encapsualnt and the method for fabricating the same |
| TW200834849A (en) * | 2007-02-06 | 2008-08-16 | Powertech Technology Inc | Land GRID array package |
| TW200929479A (en) * | 2007-12-31 | 2009-07-01 | Phoenix Prec Technology Corp | Packaging substrate and method for menufacturing the same |
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