201125096 vl i lu-_5 33658twf.doc/n 六、發明說明： 【發明所屬之技術領域】 -種封裝基彳二=是有關於 【先前技術】 目鈉在半‘肢封裝技術中，封裝基板（package :tte)是时㈣的難元狀—。域基板包括多 g回木化線路層（patterned c〇nductive layer)以及多層介 電層（dielectric layer)交替疊合而成，且兩線路層之間可 透過導電孔—tive via)而彼此電輯接。兩最外層 的圖案化導電層具^彡個接墊。聽基板更具有兩分別覆 蓋=最外層圖案化導電層的防銲層（福^心㈣， 而XI些防銲層具有多朗π ’且這賴口分別暴露出這些 接墊的-部分，用以定義出接墊的接合區域。 .曰曰片可透過覆晶接合（fliP chip bonding)或打線接合 (wire bonding)等方式組裝至封裝基板，以形成一晶片封 裝結構。此外，封裝基板更可經由多個銲球（s〇lderbaU) 組裝至外部元件（例如是印刷電路板），其中銲球是配置 於封裝基板的接墊上。然而，當接墊的接合區域是由防銲 層的開口所定義，即接墊為銲罩定義（Solder Mask Defined’ SMD)型的接墊時，銲球僅與部分的接墊表面相 接合。因此，銲球可能無法穩固地附著於接墊上，因而影 響晶片封裝結構的可靠度。此外，基於不同封裝基板的結 201125096 VIT10-0005 33658twf.doc/n 構需求，在製程上亦需要對應的調整 【發明内容】 本發明提供-種封褒基板，具有較佳的可靠度。 本發明提供-種晶，其·上述之 板’具有較佳的可靠度。 抑本發明更提出-種晶片封裝結構，適於放置在一承韋 =上。晶>；封裝結構包括—封裝基板及―晶#。封裝某相 广疊合層、一圖案化導電層、一防銲層、至少二 =及^高懒。疊合層具有彼此相對的—第-表面虚 且ί ^ 案化導電層配置於#合層的第—表面/，、 上:、2;、;=墊。：銲層配置於疊合層的第-表面 置於防銲層上且位於開叫，其中外部接墊盘^ 斤=出的内部接墊連接。塾高圖案配置於 上 回圖案相對於疊合層之第一表日墊 於疊合芦之篦一矣品认^ ώ 的问度大於外部接塾相對 ml 表的商度。當封裝基板經由墊高圖安於 器上時，外部接塾不接觸承載器。晶片配置;封 展基板上’位於疊合層的第_本 封 板。 ^ θ料—表面，電性連接至封裝基 本^棘出-種晶㈣I纟罐 域結構包括-封裝基板、— 封裝基板包括—疊合層、—圖案 y〜球。 少-外部接墊及—藝高圖案。疊合層具有彼此:對^^ 201125096 νιηυ-υυυ5 33658twf.d〇c/n 表面與一第二表面。圖案化導電層配置於疊合層的第一 表面上，且具有至少一内部接墊。防銲層配置於疊合層的 第-表面上’且具有至少—開口，其中開口暴露出内部接 墊。外部接墊配置於防銲層上且位於開口内，其中外部接 塾與開口所暴露出的内部接墊連接。塾高圖案配置於防鲜 層上，其中墊高圖案相對於疊合層之第—表面的高度大於 外。f5接塾相對於$合層之第—表面的高度。晶片配置於封 裝基板上’位於疊合層的第二表面，且電輯接至封裝基 板。銲球連接外部接墊，且t封裝基板經由銲球連接電子 元件時，墊高圖案不接觸電子元件。 本發明提出-種封裝基板，其包括一疊合層、一圖案 電層、—防銲層、至少—外部接塾及—墊高圖案。疊 合層具有-表面。圖案料電層配置於4合層的表面上, 且具有至少一内部接墊。防銲層配置於疊合層的表面上， /、有至y開口，其中開口暴露出内部接墊。外部接墊 =置於防銲層上且位於開口内，其中外部接墊與開口所暴 =出的内部接墊連接。墊高圖案配置於防銲層上，其中塾 同圖案相對於疊合層之表面的高度大於外部接墊相對於最 合層之表面的高度。 且 基於上述，本發明之封裝基板具有與内部接墊相連接 ^外部接塾，因此可增加銲球與接塾的接觸面積，以提升 録球鋒接至封裝基板後的可靠度。此外，本發明之封裝基 ，亦具有墊高®案’且此墊高圖案減於疊合層之表面二 问度大於外部接墊相對於疊合層之表面的高度。因此，者 201125096 V1T1O-O005 33658^-f.doc/n 封裝基板經由墊高圖案放置在 墊接觸承載器，以提升晶時’可避免外部接 為=本^之上述義和優點能更明顯雜，下文特 舉貝她例，並配合所附圖式作詳細說 【實施方式】 ―，1A為本發明之一實施例之—種晶片封裝結構的刹 面:思圖。圖1B為圖ία之封裝基板的仰視示意圖。請先 ^圖，晶片封裝結構2〇包括一封裝基板1〇〇及一晶 ^00，而晶片200組裝至封裝基板1〇〇上。特別是，在 本貫施例中，封裝基板刚或是已組裝晶片2⑽的晶片封 裝結構2G適於放置在承載器1()上，此承載器1()例如是作 為製程中輸送搬運之用的承載器。 封裝基板100包括一疊合層110、一圖案化導電層 12〇、一防銲層130、至少一外部接墊14〇 (圖1A中示意 地緣示多個）及—墊高圖案150 (圖1A中示意地繪示二 個）。疊合層110具有一第一表面112與相對於第一表面 112的一第二表面114。在本實施例中，疊合層11()是由多 j固圖案化導電層113與多個介電層115交替叠合而成，且 這些圖案化導電層113之間可透過至少一導電孔117而彼 此電性連接。 外層的圖案化導電層12〇配置於疊合層11〇的第一表 面112上，且此外層的圖案化導電層120具有至少一内部 接墊122 (圖1A中示意地繪示多個）。防銲層130配置於 201125096 VilllMKXb 33658twf.doc/n 疊合層110的第一表s 112上，且防銲層13〇具有至少一 開口 132 (圖1A中示意地綠示多個），其中這些開口⑶ 分別暴露出對應的這些内部接塾122。這些外部接塾⑽ 配置於防鮮層13G上且位於對應的這些開口 132内，巧 這些外部接墊M0與相對應之這些開σ 132所暴露出喊 些内部接墊122在結構上及電性上連接。 在本實施例中’每-外部接塾14〇包括一主體部142 與-金屬保護層144 ’其中這些主體部142分別與這些内 部接墊I22連接’而這些金屬保護層m分別覆蓋這些主 體部142所暴露出的表面’肖以作為這些主體部142的抗 乳化層。此處所述之這些金屬保護層m例如是錄/金層、 錄/把/金層、鎳/錫層、鈀層、金層或其他適當的金屬，\ 此並不加以限制。 這些墊高圖案150配置於疊合層11〇的第—表面112 上。在本實施财’這錄高_ 15G配置於防鲜層13〇 上。特別是二這些墊高圖案15〇相對於疊合層n〇之第一 表面112白勺尚度H1大於這些外部触14〇相對於疊合層 110之第—表面112的高度H2。換言之，相對於疊合層ιι〇 的第一表面112，這些墊高圖案15〇的頂面是高於外部接 墊140的頂®。因此’當封裝基板⑽經由這些墊高圖案 150。放置在减器10上時，這些外部接塾⑽不會接觸承 載器10’意即外部接塾14〇與承載器1〇之間存有一間隔 距_ D卜取而代之的，是由這些墊高圖案15()與承載器 10接觸。這些外部接塾H0 4導電結構，並且基於設計的 201125096 V1T10-0005 33658twf.doc/n201125096 vl i lu-_5 33658twf.doc/n VI. Description of the invention: [Technical field of the invention] - a kind of package base 2 = is related to [prior art] M. sodium in the semi-limb encapsulation technology, package substrate ( Package :tte) is the difficult element of time (four). The domain substrate comprises a plurality of patterned c〇nductive layers and a plurality of dielectric layers alternately stacked, and the two circuit layers are electrically connected to each other via a conductive via- tive via Pick up. The two outermost patterned conductive layers have a plurality of pads. The listening substrate further has two solder mask layers covering the outermost patterned conductive layer (Fu ^ Xin (4), and some solder resist layers of XI have multiple π ' and the lands respectively expose the portions of these pads, To define the bonding area of the pad. The cymbal piece can be assembled to the package substrate by flip chip bonding or wire bonding to form a chip package structure. In addition, the package substrate can be further It is assembled to an external component (for example, a printed circuit board) via a plurality of solder balls (single-bar), wherein the solder balls are disposed on the pads of the package substrate. However, when the bonding regions of the pads are formed by the openings of the solder resist layer The definition is that when the pad is a Solder Mask Defined' SMD type pad, the solder ball is only bonded to a part of the pad surface. Therefore, the solder ball may not be firmly attached to the pad, thus affecting the chip. The reliability of the package structure. In addition, based on the different package substrate junctions 201125096 VIT10-0005 33658twf.doc/n configuration requirements, the corresponding adjustments are also required in the process. [Invention] The present invention provides a kind of sealing base. The invention provides a seed crystal, and the above-mentioned board has better reliability. The invention further proposes a chip package structure suitable for being placed on a support. >; package structure includes - package substrate and "crystal #. Package a phase of a wide layer, a patterned conductive layer, a solder mask, at least two = and ^ high lazy. The stack has opposite each other - the first - the surface is imaginary and ί ^ The conductive layer is disposed on the first surface of the # layer, /, upper:, 2;,; = pad.: the solder layer is disposed on the first surface of the laminated layer on the solder resist layer And located in the open call, wherein the external pad is connected to the internal pad connection. The high pattern is arranged in the upper pattern relative to the first surface of the laminated layer. The degree of ώ is greater than the quotient of the external interface relative to the ml table. When the package substrate is placed on the device via the pad, the external interface does not contact the carrier. The wafer configuration; the overlay substrate is located on the overlay layer _This sealing plate. ^ θ material - surface, electrically connected to the package basic ^ spine - seed crystal (four) I 纟 tank domain structure including - package base - The package substrate comprises - a laminated layer, - a pattern y ~ ball. Less - an external pad and - an art pattern. The laminated layers have each other: a pair of ^^ 201125096 νιηυ-υυυ5 33658twf.d〇c/n surface and one a second surface. The patterned conductive layer is disposed on the first surface of the laminated layer and has at least one internal pad. The solder resist layer is disposed on the first surface of the laminated layer and has at least an opening, wherein the opening is exposed The inner pad is disposed on the solder resist layer and is located in the opening, wherein the outer joint is connected with the inner pad exposed by the opening. The high pattern is disposed on the anti-fresh layer, wherein the pad pattern is opposite to the anti-fresh layer The height of the first surface of the laminated layer is greater than the outer one. The height of the f5 junction relative to the first surface of the layer. The wafer is disposed on the package substrate ‘located on the second surface of the laminate layer and electrically coupled to the package substrate. When the solder ball is connected to the external pad, and the t package substrate is connected to the electronic component via the solder ball, the pad pattern does not contact the electronic component. The invention provides a package substrate comprising a laminate layer, a patterned electrical layer, a solder mask layer, at least an external interface and a pad pattern. The laminate layer has a surface. The patterned electrical layer is disposed on the surface of the 4-layer layer and has at least one internal pad. The solder resist layer is disposed on the surface of the laminated layer, and has an opening to the y, wherein the opening exposes the inner pad. External pads = placed on the solder mask and located inside the opening, where the external pads are connected to the internal pads of the opening. The pad pattern is disposed on the solder resist layer, wherein the height of the 图案 pattern relative to the surface of the stack layer is greater than the height of the outer pad relative to the surface of the contiguous layer. And based on the above, the package substrate of the present invention has an external connection with the internal pads, so that the contact area of the solder balls and the contacts can be increased to improve the reliability after the ball is connected to the package substrate. In addition, the package base of the present invention also has a padding® case and the height of the pad pattern minus the surface of the laminate layer is greater than the height of the outer pad relative to the surface of the laminate layer. Therefore, the 201125096 V1T1O-O005 33658^-f.doc/n package substrate is placed on the pad contact carrier via the padding pattern to enhance the crystal timing, and the above-mentioned advantages and advantages of the external connection can be avoided. In the following, the example of the invention is described in detail with reference to the accompanying drawings. [1] 1A is a brake surface of a chip package structure according to an embodiment of the present invention: FIG. 1B is a bottom view of the package substrate of FIG. Please first, the chip package structure 2 includes a package substrate 1 and a crystal, and the wafer 200 is assembled onto the package substrate 1 . In particular, in the present embodiment, the package substrate 2 or the wafer package structure 2G on which the wafer 2 (10) has been assembled is adapted to be placed on the carrier 1 (), for example, for transporting and transporting in the process. Carrier. The package substrate 100 includes a stacked layer 110, a patterned conductive layer 12A, a solder resist layer 130, at least one external pad 14A (shown schematically in FIG. 1A), and a pad pattern 150 (FIG. 1A). Two are schematically shown. The laminate layer 110 has a first surface 112 and a second surface 114 opposite the first surface 112. In this embodiment, the laminated layer 11 () is formed by alternately laminating a plurality of dielectric patterned conductive layers 113 and a plurality of dielectric layers 115, and at least one conductive hole is permeable between the patterned conductive layers 113. 117 is electrically connected to each other. The outer patterned conductive layer 12 is disposed on the first surface 112 of the stacked layer 11 , and the patterned conductive layer 120 of the outer layer has at least one inner pad 122 (a plurality of which are schematically illustrated in FIG. 1A ). The solder resist layer 130 is disposed on the first surface s 112 of the 201125096 Villl MKXb 33658 twf.doc/n superposed layer 110, and the solder resist layer 13 has at least one opening 132 (shown schematically in FIG. 1A in green), wherein these The openings (3) respectively expose the corresponding inner ports 122. The external interfaces (10) are disposed on the anti-friction layer 13G and are located in the corresponding openings 132. The external pads M0 and the corresponding openings σ 132 are exposed to the structural and electrical properties of the internal pads 122. Connected on. In the present embodiment, the 'per-external interface 14' includes a main body portion 142 and a metal protective layer 144', wherein the main body portions 142 are respectively connected to the inner pads I22, and the metal protective layers m respectively cover the main portions The surface exposed by 142 is used as the anti-emulsification layer of these main body portions 142. The metal protective layers m described herein are, for example, a recording/gold layer, a recording/pushing/gold layer, a nickel/tin layer, a palladium layer, a gold layer or other suitable metal, which is not limited. These pad pattern 150 is disposed on the first surface 112 of the laminated layer 11A. In this implementation, the record _ 15G is placed on the anti-fresh layer 13〇. In particular, the height H1 of the pad pattern 15 〇 relative to the first surface 112 of the laminate layer 〇 is greater than the height H2 of the outer surface 14 〇 relative to the first surface 112 of the laminate layer 110. In other words, the top surface of these pad pattern 15 turns is higher than the top ® of the outer pad 140 with respect to the first surface 112 of the laminated layer ιι. Therefore, when the package substrate (10) passes through these pad pattern 150. When placed on the reducer 10, the external joints (10) do not contact the carrier 10', that is, the external joints 14〇 and the carrier 1〇 are separated by a gap _D, which is replaced by these raised patterns. 15() is in contact with the carrier 10. These external connections are H0 4 conductive structures and are based on the design of 201125096 V1T10-0005 33658twf.doc/n
需求會與外層的圖案化導電層l2〇、疊合層u〇的多個圖 案化導電層113、晶片200電性連接。若承載器1〇(例如： 用於製程輸送的承載器）上存有靜電電流或是其他非預期 的電流，透過這些墊高圖案15〇的配置，則可以有效避免 因這些外部接墊140與承載器1〇接觸，而使靜電電流或是 其他非預期的電流透過外部接墊14〇、外層的圖案化導電 層120、疊合層11〇的多個圖案化導電層113而導通至^ 片200，進而造成晶片2〇〇損傷的問題。 阳 "月參考圖1B，在本實施例中，這些塾高圖案Mo包 括多個墊高點152(圖1B中僅示意地繪示四個），其中這 些墊高點152分別分佈於防銲層13〇的多個角落134 (圖 1B中僅示意地繪相個）。也就是說，本實施例之這些^ 高圖案15〇是呈現點狀分佈或非連續分佈_ g分佈於 在干層m的這些角落I%上。此外，在其他未綠示的實施 例中，這些塾高_ 15Q亦可呈現連續分佈的型態分佈於 防銲層130的周H，例如這些墊高圖帛⑽為條狀分佈、' 或是點狀與條狀雜合來分佈。射之，本發明在此並不 限定的這錄高瞧15G㈣構職，已知的其他能 =荨提升聽基板⑽之可靠度的結構設計，仍屬於本發 月可^用的技術方案’不脫離本發明所欲保護的範圍。此 外，這些墊高圖案150的材質例如是防銲材料。 晶片位於疊合層110的第二表面114，且電性 ^至封I基板1GG。在本實施例中，封裝基板·更包括 一防銲層160 ’其配置於疊合層11〇的第二表自ιΐ4上， 201125096 vuiu-uuud 33658twf.doc/n 且防銲層160具有至少一開口 162(圖1Α中示意地繪示多 個），其中這些開口 162分別暴露出配置於第二表面114 的部份圖案化導電層113。The requirements are electrically connected to the patterned conductive layer 12 of the outer layer, the plurality of patterned conductive layers 113 of the laminated layer u, and the wafer 200. If the carrier 1〇 (for example: the carrier for process delivery) has static current or other unintended current, the configuration of these padding patterns 15 有效 can effectively avoid the external pads 140 and The carrier 1 is in contact with each other, and an electrostatic current or other unintended current is transmitted through the external pad 14 , the patterned conductive layer 120 of the outer layer, and the plurality of patterned conductive layers 113 of the stacked layer 11 导 to be turned on to the film. 200, which in turn causes problems with wafer 2 defects. Referring to FIG. 1B, in the present embodiment, the height pattern Mo includes a plurality of pad height points 152 (only four are schematically shown in FIG. 1B), wherein the pad height points 152 are respectively distributed on the solder resist. A plurality of corners 134 of layer 13 (only schematically depicted in Figure 1B). That is to say, these high pattern 15 本 of the present embodiment is distributed in a dot-like distribution or a discontinuous distribution _ g distributed on these corners I% of the dry layer m. In addition, in other embodiments not shown in green, these 塾 15 15Q may also be in a continuous distribution pattern distributed over the circumference H of the solder resist layer 130, for example, these pad height maps (10) are strip-shaped, 'or Point and strip hybrids are distributed. According to the invention, the invention is not limited to the recording of the high-rise 15G (four) structure, and the other structural design that can improve the reliability of the listening substrate (10) is still a technical solution that can be used in this month. It is within the scope of the claimed invention. Further, the material of these pad pattern 150 is, for example, a solder resist material. The wafer is located on the second surface 114 of the laminated layer 110 and electrically connected to the I substrate 1GG. In this embodiment, the package substrate further includes a solder resist layer 160' disposed on the second surface of the laminated layer 11A from ΐ4, 201125096 vuiu-uuud 33658twf.doc/n and the solder resist layer 160 has at least one Openings 162 (shown schematically in FIG. 1A) are disclosed, wherein the openings 162 respectively expose a portion of the patterned conductive layer 113 disposed on the second surface 114.
曰曰片封裝結構20更包括多個凸塊21〇及一封裝膠體 〇 /、中运些凸塊210配置於晶片200與封裝基板1〇〇 之間且分別位於這些開口 162所暴露出的部份圖案化導電 層113上，而晶片200透過這些凸塊21〇與封裝基板1〇〇 相電性連接。此外’縣雜22G填充於晶片2G0與封裝 基板1〇〇之間，且封裝膠體220包覆這些凸塊21〇。 基於上述，在本實施例中，晶片200以覆晶接合（flip chip bonding)的方式電性連接至封裝基板1〇〇。在另一未 緣示實施例中’晶片可以打線接合（wkebQnding)或 其他的方式電性連接至封裝基板100。 由於本貫施例之封裝基板100具有分別與這些内部4 塾122連接的這些外部接墊14〇，目此相對於習知由防產 層之開口所定A的接墊區域而言，本實施例之配置於啦 層130上的攻些外部接塾14〇卩具有較大的接塾面積。The cymbal package structure 20 further includes a plurality of bumps 21 and an encapsulant 〇, and the bumps 210 are disposed between the wafer 200 and the package substrate 1 且 and are respectively located at the portions of the openings 162 The portion of the conductive layer 113 is patterned, and the wafer 200 is electrically connected to the package substrate 1 through the bumps 21A. Further, the county 22G is filled between the wafer 2G0 and the package substrate 1A, and the encapsulant 220 covers the bumps 21A. Based on the above, in the present embodiment, the wafer 200 is electrically connected to the package substrate 1 in a flip chip bonding manner. In another embodiment, the wafer may be electrically connected to the package substrate 100 by wire bonding or other means. Since the package substrate 100 of the present embodiment has the external pads 14A respectively connected to the internal electrodes 122, the present embodiment is the same as the pad region defined by the opening of the anti-production layer. The external interface 14〇卩 disposed on the layer 130 has a large interface area.
此外，由於本實施例之封裝基板100具有這些墊高E 案150, 士這些墊高圖案15〇相對於疊合層ιι〇之第一^ ，112的南度大於這些外部接墊刚相對於疊合層n =表面112的南度(即這些塾高圖案15〇的頂面高於這; 古^墊⑽_面）°因此’當封裝基板1GG經由這些， :二150放置在承載器10上時，可避免這些外部接1 接觸承載H 1G，以降低靜電電流或是其他非預期的, 10 201125096 νιιιυ-υ005 33658twf.doc/n 流經由外部接墊140而導入晶片200的可能性，因而提升 晶片200組裝至封裝基板1〇〇後的可靠度。 圖2為本發明之另一實施例之一種晶片封裂結構的剖 面示思圖。本實施例沿用前述實施例的元件標號與部分内 容’其中採用相同的標號來表示相同或近似的元件，並且 省略了相同技術内容的說明。關於省略部分的說明可參照 前述實施例，本實施例不再重複贅述。 喷參考圖2，本實施例的晶片封裝結構3〇與前述實施 例之晶片封裝結構20相似，其主要的差異在於：圖2之晶 片封裝結構30更包括至少一銲球300(圖2中示意地繪示 多個），其中這些銲球3〇〇分別連接至這些外部接塾14^ 以透過這些銲球300與外部元件相電性連接。 詳細來說，這些墊高圖案150相對於疊合層11〇之第 一表面112的高度H1小於這些銲球300相對於θ疊入戶 之第—表面112的高度m。換言之，相對於4合層曰In addition, since the package substrate 100 of the present embodiment has these pad heights E 150, the heights of the pad patterns 15 〇 relative to the first layer 112 of the laminated layer ιι are larger than the outer pads just opposite to the stack. The layer n = the south degree of the surface 112 (ie, the top surface of these 塾 high pattern 15 高于 is higher than this; the ancient pad (10) _ face) ° thus 'when the package substrate 1GG passes through these, the second 150 is placed on the carrier 10 When these external contacts 1 contact H 1G are avoided, the possibility of static current or other unintended, 10 201125096 ν ι ι υ 33 33 33 33 658 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 The reliability of the wafer 200 after assembly to the package substrate 1 . Figure 2 is a cross-sectional view showing a wafer cracking structure in accordance with another embodiment of the present invention. The same reference numerals are used to denote the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted portions, reference may be made to the foregoing embodiments, and the description of the embodiments will not be repeated. Referring to FIG. 2, the chip package structure 3 of the present embodiment is similar to the chip package structure 20 of the previous embodiment, and the main difference is that the chip package structure 30 of FIG. 2 further includes at least one solder ball 300 (illustrated in FIG. 2). A plurality of solder balls 3 are respectively connected to the external interfaces 14 to be electrically connected to the external components through the solder balls 300. In detail, the height H1 of the pad pattern 150 with respect to the first surface 112 of the laminated layer 11 is smaller than the height m of the solder balls 300 with respect to the first surface 112 of the θ stack. In other words, relative to the 4-layer 曰
3之00弟2面112，這些墊高圖案15G的頂面低於這^旱球 的頂面。在依實關巾，這錄高料15Q = 的高度至少小於這些銲球獅相對於 、 因此，當晶片封裝結構3()之銲球‘ 4之—电子元件12欲連接時，這些墊高圖筆丨 ^外 ft子元件12接觸，意即塾高圖案⑼與外部之g外 之間存有一間隔距離D2，故會 =疋 部之電子元件㈣接合。在—實施例中，;卜==與外 12例如是—電路基板、一電子封裝體或是其他 201125096 vii ιυ-υν/vJ 33658twf.doc/n 件 :部接塾相連接的這些;心:封 層之開口所定蠢的桩執二丄 ㈢知由防知 對應的外部接墊可I有G接^本實施例之每―銲球與 至封裝基板靠故可提升銲球組裝 轉古心、1 卜，本發明之封裝基板具有這 &於mi且1""些塾高圖案相對於疊合層之表面的高度 外部接餘對於疊合層之表面的高度。因此，ΐ 高圖案放置在承載器上時，可避免這 d陽塾接觸承载器’可提升晶片聽至封裝基板後的 ϋ另外，本發明之封裝基板具有這些塾高圖案，且 疊合層之表面的高度小於這些銲球相 球盘“:電二::度。因此，當封裳基板經由這些銲 變連接時，這錄高圖錢配置不會影 曰&些1干球與外部之電子元件的接合。 二、:本么月已以貫施例揭露如上，然其並非用以限定 太1明，任何所屬技術領域中具有通常知識者，在不脫離 取二月之精!ί和1(1圍内’當可作些許之更動與潤飾，故本 χ之保濩1巳圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 一圖1Α為本發明之—實施例之一種晶片封裝結構的剖 口示意圖。 圖1Β為圖ιΑ之封裝基板的仰視示意圖。 201125096 vjli iu-u005 33658twf.doc/n 圖2為本發明之另一實施例之一種晶片封裝結構的剖 面示意圖。 【主要元件符號說明】 10 :承載器 12 :電子元件 20、30 :晶片封裝結構 100 :封裝基板 • 110 :疊合層 112 :第一表面 113 :導電層 114 :第二表面 115 :介電層 1Π ··導電孔 120 :圖案化導電層 122 :内部接墊 鲁 130、160 :防錄層 132、162 :開口 134 :角落 140 :外部接墊 142 :主體部 144 :金屬保護層 150 :墊高圖案 152 :墊高點 13 33658twf.doc/n 201125096 200 :晶片 210 :凸塊 220 :封裝膠體 300 :銲球3 of the 00 brothers 2 faces 112, the top surface of these padding patterns 15G is lower than the top surface of the dry ball. In the actual cover towel, the height of the recorded material 15Q = is at least smaller than that of the solder ball lions. Therefore, when the solder ball 4 of the chip package structure 3 is connected, the height of the electronic component 12 is to be connected. The pen 丨 ft sub-element 12 is in contact, which means that there is a distance D2 between the 塾 high pattern (9) and the outer g, so that the electronic component (four) of the 疋 part is joined. In the embodiment, the b == and the outer 12 are, for example, a circuit substrate, an electronic package or other 201125096 vii ιυ-υν/vJ 33658twf.doc/n pieces: these are connected; The opening of the sealing layer is stupid. (3) It is known that the external pads corresponding to the anti-knowledge can be G-connected. Each of the solder balls and the package substrate in this embodiment can improve the assembly of the solder balls. 1b, the package substrate of the present invention has the height of the height of the outer layer of the laminate layer with respect to the height of the surface of the laminate layer. Therefore, when the ΐ high pattern is placed on the carrier, the d yaw contact carrier can be prevented from being able to lift the 晶片 after the wafer is heard to the package substrate. In addition, the package substrate of the present invention has these embossed patterns, and the laminated layer The height of the surface is smaller than the ball phase of the solder ball ": 2:: degrees. Therefore, when the sealing substrate is connected via these welding, this high-profile configuration does not affect the & 1 dry ball and the outside The joining of electronic components. Second, this month has been disclosed in the above examples, but it is not intended to limit the Taiyi, any general knowledge in the technical field, without leaving the essence of February! 1 (1 inside the 'when you can make some changes and retouching, so the original 濩 χ 巳 巳 当 当 当 当 当 当 当 。 。 。 。 。 。 。 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 FIG. 1 is a schematic top view of a package substrate of FIG. 1A. FIG. 2 is a schematic view of a package of a package according to another embodiment of the present invention. Schematic diagram of the structure. DESCRIPTION OF SYMBOLS 10: Carrier 12: Electronic components 20, 30: Wafer package structure 100: Package substrate • 110: Laminated layer 112: First surface 113: Conductive layer 114: Second surface 115: Dielectric layer 1Π·· Conductive hole 120: patterned conductive layer 122: internal pad 105, 160: anti-recording layer 132, 162: opening 134: corner 140: external pad 142: body portion 144: metal protective layer 150: pad pattern 152: Pad High Point 13 33658twf.doc/n 201125096 200 : Wafer 210 : Bump 220 : Package Colloid 300 : Solder Ball
Dl、D2 :間隔距離 m、H2、H3 :高度Dl, D2: separation distance m, H2, H3: height
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