CN100350581C - Integrated wiring and inverse packaged chip structure and process - Google Patents
Integrated wiring and inverse packaged chip structure and process Download PDFInfo
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- CN100350581C CN100350581C CNB2004100118616A CN200410011861A CN100350581C CN 100350581 C CN100350581 C CN 100350581C CN B2004100118616 A CNB2004100118616 A CN B2004100118616A CN 200410011861 A CN200410011861 A CN 200410011861A CN 100350581 C CN100350581 C CN 100350581C
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
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Abstract
The present invention relates to a manufacturing process for an integrated wiring and inverse packaged chip. The manufacturing process comprises the following steps that a chip is firstly provided, wherein a protective layer and a plurality of chip welding pads are arranged on the chip, and the chip welding pads are exposed out of the protective layer; a metallic layer with a spherical bottom is respectively formed on each of the chip welding pads, and the metallic layer with a spherical bottom is orderly formed from Al/Ni metals and V/Cu metals; then, a Cu layer and a Ni-V layer in the metallic layer with a spherical bottom partially arranged on each of the chip welding pads is removed, so that part of the metallic layer with a spherical bottom on the chip welding pads is only formed from an Al layer; subsequently, a plurality of openings are defined according to optical resistance to expose the metallic layers with a spherical bottom containing Al/Ni-V/Cu metals, and the openings are filled with solder; finally, a step of back welding is carried out to form a plurality of welding balls on the metallic layers with a spherical bottom containing the Al/Ni-V/Cu metals. In addition, the present invention provides the structure of the integrated wiring and the inverse packaged chip which is manufactured by the manufacturing process for the integrated wiring and the inverse packaged chip.
Description
Technical field
The present invention relates to a kind of chip technology and structure of integrating routing and flip-chip packaged, particularly a kind of technology and the integration routing of minimizing process materials and the chip structure and technology of flip-chip packaged simplified.
Background technology
In today of advanced information society, multimedia application market is expansion rapidly constantly, and the integrated circuit encapsulation technology is also thereupon towards digitlization, networking, the zone connectionization of electronic installation and the trend development that uses hommization.For reaching above-mentioned requirement, electronic component must cooperate many-sided requirements such as high speed processingization, multifunction, productive setization, miniaturization and and low priceization, and also therefore the integrated circuit encapsulation technology also and then develops towards microminiaturized, densification.Wherein sphere grid array formula encapsulation (Ball Grid Array, BGA), chip size packages (Chip-ScalePackage, CSP), and flip-chip packaged (Flip Chip, F/C), multi-chip module (Multi-ChipModule, MCM) etc. high density integrated circuit encapsulation technology also in response to and give birth to.
Wherein flip-chip packaged technology (Flip Chip Packaging Technology) mainly is the arrangement mode that utilizes face array (area array), a plurality of chip pad (bonding pad) are disposed at the active surface (active surface) of chip (die), and on each chip pad, form projection (bump), then more afterwards, utilize the projection on the chip pad to distinguish the surperficial pairing joint sheet (mounting pad) that electrical (electrically) and mechanical (mechanically) is connected to substrate (substrate) or printed circuit board (PCB) (PCB) with chip turn-over (flip).Moreover, because the flip-chip bonded technology can be applicable to the chip-packaging structure of high pin number (High Pin Count), and have multiple advantages such as the package area of dwindling and shortening signal transmission path simultaneously, so the flip-chip bonded technology has been widely used in the Chip Packaging field at present.Yet in multichip package structure, chip not only needs to engage with another flip-chip, the mode and the substrate that more need to engage by routing electrically connect, and therefore integrate development priority of the chip structure of routing and flip-chip packaged and next generation that technology also becomes the flip-chip packaged technology natch.
And the chip structure and the technology of so-called integration routing and flip-chip packaged, be common in the flip chip technology (flip chip), mainly be to be formed with upward formation ball substrate layer (UBM of contact external on the wafer of a plurality of chips (normally chip pad), Under Bump Metallurgy), another then is set again thereon on the ball substrate layer of part for the wetting layer of making gold thread (conductor wire) joint and barrier layer.Then, then then form a plurality of projections or implantation soldered ball connecting interface on not being provided with to electrically conduct as follow-up chip (or wafer) and substrate (substrate) flip-chip bonded for the ball substrate layer of the wetting layer of making the gold thread joint and barrier layer.From the above, generally speaking, when chip pad was the aluminium pad, ball substrate layer was made up of aluminium/nickel-vanadium/copper metal usually in regular turn, and the above-mentioned confession of carrying is beaten the wetting layer and the barrier layer of gold thread joint and then is made up of nickel metal layer and gold layer institute usually.
Please refer to Fig. 1, be the chip technology of existing integration routing and flip-chip packaged, it comprises the following step.At first, provide a chip 100, and have a plurality of chip pad 102 on each chip and expose the protective layer 104 of described chip pad 102.Then, form a ball substrate layer 106 respectively on each described chip pad 102.Wherein, chip pad 102 is an aluminum metal, and ball substrate layer 106 is aluminium 106a/ nickel-vanadium alloy 106b/ copper 106c three-layer metal structure, it utilize to be electroplated or modes such as sputter are formed at crystal column surface, continue again utilize photoresistance to be covered on the ball substrate layer and utilize develop and mode patterning photoresist layer such as etching and ball substrate layer to define required ball substrate layer structure.Afterwards, on the copper metal layer 106c of part ball substrate layer, form nickel metal layer 107a and gold layer 107b in regular turn.Then, form a photoresist layer 109 on chip, to expose on the ball substrate layer 106 that is not provided with nickel metal layer 106a and gold layer 106b covering.Moreover, fill scolder in opening, to form a plurality of projections 110.At last, carry out a reflow step, so that projection 110 and ball substrate layer 106 fixed engagement are as shown in Figure 2.
From the above, ball substrate layer 106 is formed at the ball substrate layer that can be patterning on the chip pad 102 or not patterned ball substrate layer, and earlier patterned when the ball substrate, then scolder can be arranged on the ball substrate layer by the mode of printing; And not patterned when the ball substrate, then scolder can be arranged on the ball substrate layer by the mode of electroplating, and only this step is the standard technology in the projection technology, so do not give unnecessary details in addition at this.
Because the above-mentioned integration routing and the chip structure of flip-chip packaged need to form in addition nickel metal layer and gold layer for the usefulness of making gold thread joints on the ball substrate, thus not only increase the step of technology, and must the increase nickel metal layer and golden layer material expend and use.Therefore, provide the shortcoming of the chip structure that solves above-mentioned existing integration routing and flip-chip packaged and the method for related process thereof, real is important topic of the present invention.
Summary of the invention
Because above-mentioned problem, the objective of the invention is to overcome the deficiencies in the prior art and defective, provide a kind of chip structure and technology of integrating routing and flip-chip packaged, particularly a kind of technology and the integration routing of minimizing process materials and the chip structure and technology of flip-chip packaged simplified.
For reaching above-mentioned purpose, the present invention proposes a kind of chip technology of integrating routing and flip-chip packaged, and it comprises the following step.At first, provide a wafer, have the protective layer that a plurality of chip pad and expose described chip pad on this wafer.Then, form a ball substrate layer respectively on each described chip pad, wherein ball substrate layer is made up of adhesion layer, barrier layer and wetting layer.Moreover, barrier layer and wetting layer on the ball substrate layer that partly is arranged on the chip pad are removed, to expose the usefulness of adhesion layer as the conductor wire joint.Afterwards, the wetting layer on the ball substrate layer that does not remove barrier layer and wetting layer is provided with projection.At last, carry out a reflow step, so that projection engages with ball substrate layer.Generally speaking, when chip pad was the aluminium pad, adhesion layer was an aluminum metal layer, and barrier layer is nickel-vanadium layer, and wetting layer is a copper metal layer.
Moreover, the present invention proposes the chip structure of formed integration routing of a kind of chip technology by above-mentioned integration routing and flip-chip packaged and flip-chip packaged in addition, it comprises: a chip, it has an active surface, a protective layer, a plurality of chip pad and a ball substrate layer, wherein this protective layer and described chip pad are formed on this active surface, this protective layer exposes described chip pad, and this ball substrate layer is arranged on the described chip pad; Barrier layer and wetting layer are not set with usefulness on the ball substrate layer of part as the conductor wire joint; In addition, a plurality of projections, its ball substrate layer that is provided with barrier layer and wetting layer that is formed on each described chip pad engages.
Described before combining, when chip pad is the aluminium pad, adhesion layer is generally formed by aluminum metal layer, so can engage end points by direct routing as gold thread, so the present invention is specially adapted to integrate the aluminium chip structure and the technology of routing and flip-chip packaged, yet when chip is copper packing, still can utilize technology of the present invention, at the barrier layer of part and after wetting layer removes, on the adhesion layer that exposes, form an aluminum metal layer or other in addition and be suitable as the metal level that routing engages and get final product.
Description of drawings
Fig. 1 to Fig. 2 is an existing generalized section of integrating the chip technology of routing and flip-chip packaged;
Fig. 3 is according to the integration routing of preferred embodiment of the present invention and the chip structure generalized section of flip-chip packaged;
Fig. 4 to Fig. 8 is the generalized section of the chip technology of an integration routing and flip-chip packaged, is shown as according to the integration routing of preferred embodiment of the present invention and the chip structure and the technology of flip-chip packaged;
Fig. 8 to Figure 13 is shown as according to the integration routing of preferred embodiment of the present invention and the chip structure and the technology of flip-chip packaged for another generalized section of integrating the chip technology of routing and flip-chip packaged.
Symbol description among the figure
100 chips
102 chip pad
104 protective layers
106 ball substrate layers
106a adhesion layer (aluminum metal layer)
106b barrier layer (nickel-vanadium alloy)
106c wetting layer (copper metal layer)
The wetting layer that 107a share for routing
The barrier layer that 107b share for routing
109 photoresist layers
110 solder projections
200 chips
202 chip pad
204 protective layers
206 ball substrate layers
The 206a adhesion layer
The 206b barrier layer
The 206c wetting layer
208 solder projections
300 chips
302 chip pad
304 protective layers
306 ball substrate layers
The 306a adhesion layer
The 306b barrier layer
The 306c wetting layer
307 photoresist layers
308 photoresist layers
309 solder projections
400 chips
402 chip pad
403 protective layers
404a is the adhesion layer of patterning not
404b is the barrier layer of patterning not
404c is the wetting layer of patterning not
405 photoresist layers
406 solder projections
407 patterning ball substrate layers
The adhesion layer of 407a patterning
The barrier layer of 407b patterning
The wetting layer of 407c patterning
410 photoresist layers
411 patterning photoresist layers
Embodiment
Hereinafter with reference to relevant drawings, illustrate according to the integration routing of preferred embodiment of the present invention and the chip structure and the technology of flip-chip packaged.
Please refer to Fig. 3, it shows according to the integration routing of preferred embodiment of the present invention and the generalized section of flip chip structure.
Please refer to Fig. 3, be the part-structure schematic diagram of expression chip 200.Chip 200 has chip pad 202, protective layer 204 and is formed at ball substrate layer 206 on the chip pad 202.Wherein, protective layer 204 is disposed on the chip surface; in order to protection chip 200 surface and expose weld pad 202, and the ball substrate layer of part is made up of adhesion layer 206a, barrier layer 206b and wetting layer 206c, the jointing metal layer that engages with chip pad 202 as projection 208.In addition, wetting layer 206c in the ball substrate layer 206 on the chip pad 202 of part and barrier layer 206b all are removed and only expose adhesion layer 206a, with the usefulness as the conductor wire joint.
It should be noted that ball substrate layer 206 generally is aluminium lamination/nickel-vanadium layer/copper layer in regular turn when chip pad 202 is aluminium welding pad, only only be provided with the ball substrate layer that comprises aluminium lamination on the chip pad 202 in order to conductor wire joint usefulness.When chip pad 202 is copper pad, ball substrate layer 206 generally is titanium layer/nickel-vanadium layer/copper layer in regular turn, yet when chip pad 202 tops remove nickel-vanadium layer/copper layer and desire to engage the end points of usefulness as the chip routing, engage the end points of usefulness as conductor wire except that keeping titanium layer, (that is only including titanium coating on the ball substrate layer) also can be provided with one again and engage and the aluminum metal layer preferable with the titanium layer joint capacity with gold thread on titanium layer, engage the end points of usefulness as conductor wire.
Then, please refer to Fig. 4 to Fig. 7, it shows integration routing and the chip structure of flip-chip packaged and the generalized section of technology according to preferred embodiment of the present invention.
At first, please refer to Fig. 4, a chip 300 is provided, be formed with a plurality of chip pad 302 and protective layer 304 on the chip 300.Wherein, protective layer 304 is disposed on chip 300 surfaces, in order to protect chip 300 surfaces and weld pad 302 is exposed.
Then, please continue again, form ball substrate layer 306 on this chip 300 and cover chip pad 302 with reference to Fig. 4.Wherein, ball substrate layer 306 comprises adhesion layer 306a, barrier layer 306b and wetting layer 306c.Wherein, ball substrate layer 306 can form the metal of adhesion layer 306a, barrier layer 306b and wetting layer 306c earlier on chip 300 in regular turn, utilize photoresistance to carry out little shadow and etch process again, so that this metal pattern and make 306 on ball substrate layer be formed at chip pad 302 tops.Then, refer again to Fig. 4, form another photoresist layer 307 on chip 300, and expose the ball substrate layer 306 that part is positioned at chip pad 302 tops.Then, use suitable etching solution, remove, and make adhesion layer 306a still keep somewhere on the chip pad of part 302 with wetting layer 306c and barrier layer 306b that will part.Then, photoresist layer 307 is removed, as shown in Figure 5.
Then, as shown in Figure 6, another photoresist layer 308 is set on chip 300, and forms a plurality of openings to expose the ball substrate layer that does not remove barrier layer 306b and wetting layer 306c.Afterwards, scolder is inserted in the photoresist layer 308 defined opening, to form a plurality of solder projections 309.At last, photoresist layer 308 is removed and carry out the reflow step, so that solder projection 309 and ball substrate layer 306 affixed (as shown in Figure 7).
From the above, ball substrate layer is formed at the ball substrate layer that can be patterning on the chip pad or not patterned ball substrate layer, and earlier patterned when the ball substrate, then scolder can be arranged on the ball substrate layer by the mode of printing; And when the ball substrate not patterned, then scolder can be arranged on the ball substrate layer by the mode of electroplating, and can continue by established solder projection to shielding, with patterning ball substrate layer and remove wetting layer and the barrier layer of desiring to engage the weld pad top of usefulness as conductor wire, only this step can utilize the standard step in the projection electroplating technology to implement, as Fig. 8 to step shown in Figure 13.
Then, please refer to Fig. 8, a chip 400 is provided, be formed with a plurality of chip pad 402 and protective layer 403 on the chip 400.Wherein, protective layer 403 is disposed on chip 400 surfaces, in order to protect chip 400 surfaces and weld pad 402 is exposed.
Afterwards, please continue with reference to Fig. 8, the metal that will form adhesion layer 404a, barrier layer 404b and wetting layer 404c in regular turn is formed on the chip 400 and covers chip pad 402 again.Then, be provided with a photoresist layer 405 on ball substrate layer and define a plurality of openings with expose the part wetting layer 404c.Afterwards, scolder is inserted in the photoresist layer 405 defined opening, to form a plurality of solder projections 406.When solder projection 406 is when forming in the mode of electroplating, can be about to photoresist layer 405 this moment earlier remove.Then, serve as shielding and cooperate the etching solution that is fit to that wetting layer 404c and barrier layer 404b are removed or remove simultaneously (as shown in Figure 9) in regular turn with solder projection 406, to form the wetting layer 407c and the barrier layer 407b of patterning.
Please follow with reference to Figure 10, form another photoresist layer 410 (as shown in figure 10) on chip 400, and with patterning photoresist layer 410 the photoresist layer 411 of patterning is covered on the adhesion layer 404a on the chip pad 402 that is not coated with solder projection 406 by little shadow and etched mode.Afterwards, photoresist layer 411 and the solder projection 406 with patterning is shielding forms patterning with patterning adhesion layer 404a adhesion layer 407a (as Figure 11 and shown in Figure 12).At last, patterning photoresist layer 411 removed and carry out the reflow step, so that solder projection 406 and patterning ball substrate layer 407 affixed (as shown in figure 13), the chip structure that forms integration routing of the present invention and flip-chip packaged to finish the chip technology of integrating routing and flip-chip packaged.
In the present embodiment, because the chip structure of integration routing of the present invention and flip-chip packaged, do not need on the ball substrate, to form in addition barrier layer and the wetting layer (as nickel metal layer and gold layer) that engages usefulness for the conductor wire routing, so not only can simplify processing step, the material that more can exempt nickel metal layer and gold layer expends and uses.Therefore, real is to solve the shortcoming of the chip structure that has integration routing and flip-chip packaged now and the best approach of related process thereof.
The specific embodiment that is proposed in the detailed description of present embodiment is only in order to be easy to illustrate technology contents of the present invention, and be not with narrow sense of the present invention be limited to this embodiment, therefore, in the situation that does not exceed spirit of the present invention and claims, can make many variations and implement.
Claims (27)
1. a chip technology of integrating routing and flip-chip packaged is characterized in that, comprises:
One chip is provided, have a protective layer and a plurality of chip pad on this chip, and this protective layer exposes described chip pad;
Form a patterning ball substrate layer on each described chip pad, wherein this patterning ball substrate layer comprises a patterning adhesion layer, a patterning barrier layer and a patterning wetting layer;
Remove this patterning barrier layer and the patterning wetting layer of the top that is arranged at one of described chip pad; And
A plurality of projections are set on the ball substrate layer that does not remove this patterning barrier layer and this patterning wetting layer.
2. the chip technology of integration routing as claimed in claim 1 and flip-chip packaged, wherein, this patterning adhesion layer is an aluminum metal layer or is a titanium coating.
3. the chip technology of integration routing as claimed in claim 1 and flip-chip packaged, wherein, this patterning barrier layer is a nickel vanadium metal layer.
4. the chip technology of integration routing as claimed in claim 1 and flip-chip packaged, wherein, this patterning wetting layer is a copper metal layer.
5. the chip technology of integration routing as claimed in claim 1 and flip-chip packaged, wherein, described projection is a solder projection.
6. the chip technology of integration routing as claimed in claim 5 and flip-chip packaged wherein, more comprises a reflow step, so that described solder projection is fixed on this patterning wetting layer.
7. the chip technology of integration routing as claimed in claim 1 and flip-chip packaged, wherein, the material of this protective layer comprises nitride or comprises phosphorosilicate glass or comprise silica.
8. the integration routing described in claim 2 and the chip technology of flip-chip packaged, wherein, when the patterning adhesion layer is aluminum metal layer, after this patterning barrier layer that removes the top that is arranged at one of described chip pad and patterning wettable layer, a gold medal layer is set on this patterning adhesion layer.
9. the integration routing described in claim 2 and the chip technology of flip-chip packaged wherein, after this patterning barrier layer that removes the top that is arranged at one of described chip pad and patterning wettable layer, are provided with an aluminium lamination on this patterning adhesion layer.
10. a chip technology of integrating routing and flip-chip packaged is characterized in that, comprises:
One chip is provided, have a protective layer and a plurality of chip pad on this chip, and this protective layer exposes described chip pad;
Form a ball substrate layer on each described chip pad, wherein this ball substrate layer comprises an adhesion layer, a barrier layer and a wetting layer;
One projection is set on the ball substrate layer of the top of one of described chip pad;
With this projection serves as that shielding removes not the barrier layer that covered by this projection and wetting layer to form a patterning barrier layer and a patterning wetting layer;
One photoresist layer is set on this adhesion layer that is not covered and be arranged at described chip pad top by projection; And
With this projection and this photoresist layer is that this adhesion layer of shielding patternization is to form a patterning adhesion layer.
11. the chip technology of integration routing as claimed in claim 10 and flip-chip packaged wherein, more comprises a reflow step, so that described projection is fixed on this patterning wetting layer.
12. the chip technology of integration routing as claimed in claim 11 and flip-chip packaged wherein, before carrying out the reflow step, more comprises the step of removing this photoresist layer.
13. the chip technology of integration routing as claimed in claim 10 and flip-chip packaged, wherein, this patterning adhesion layer is an aluminum metal layer or is a titanium coating.
14. the chip technology of integration routing as claimed in claim 10 and flip-chip packaged, wherein, this patterning barrier layer is a nickel vanadium metal layer.
15. the chip technology of integration routing as claimed in claim 10 and flip-chip packaged, wherein, this patterning wetting layer is a copper metal layer.
16. the chip technology of integration routing as claimed in claim 10 and flip-chip packaged, wherein, described projection is a solder projection.
17. the chip technology of integration routing as claimed in claim 10 and flip-chip packaged, wherein, the material of this protective layer comprises nitride or comprises phosphorosilicate glass or comprise silica.
18. the integration routing described in claim 13 and the chip technology of flip-chip packaged wherein, when the patterning adhesion layer is aluminum metal layer, after forming this patterning adhesion layer, are provided with a gold medal layer on this patterning adhesion layer.
19. the integration routing described in claim 13 and the chip technology of flip-chip packaged wherein, after forming this patterning adhesion layer, are provided with an aluminium lamination on this patterning adhesion layer.
20. a chip structure of integrating routing and flip-chip packaged is characterized in that, comprises:
One chip, it has an active surface, a protective layer, a plurality of chip pad, and wherein this protective layer and described chip pad are formed on this active surface, and this protective layer exposes described chip pad;
One patterning adhesion layer, a patterning barrier layer and a patterning wetting layer are arranged at the top of one of described chip pad in regular turn, only are provided with this patterning adhesion layer on remaining described chip pad; And
One solder projection is formed on this patterning wetting layer.
21. the chip structure of integration routing as claimed in claim 20 and flip-chip packaged, wherein, this patterning adhesion layer is an aluminum metal layer or is a titanium coating.
22. the chip structure of integration routing as claimed in claim 20 and flip-chip packaged, wherein, this patterning barrier layer is a nickel vanadium metal layer.
23. the chip structure of integration routing as claimed in claim 20 and flip-chip packaged, wherein, this patterning wetting layer is a copper metal layer.
24. the chip structure of integration routing as claimed in claim 20 and flip-chip packaged, wherein, described projection is a solder projection.
25. the chip structure of integration routing as claimed in claim 20 and flip-chip packaged, wherein, the material of this protective layer comprises nitride or comprises phosphorosilicate glass or comprise silica.
26. the integration routing described in claim 21 and the chip technology of flip-chip packaged, wherein, when the patterning adhesion layer is aluminum metal layer, a gold medal layer is set on this patterning adhesion layer on all the other described chip pad that only are provided with this patterning adhesion layer.
27. the integration routing described in claim 21 and the chip technology of flip-chip packaged wherein, are provided with an aluminium lamination on this patterning adhesion layer on all the other described chip pad that only are provided with this patterning adhesion layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100118616A CN100350581C (en) | 2004-09-22 | 2004-09-22 | Integrated wiring and inverse packaged chip structure and process |
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Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100464399C (en) * | 2006-04-05 | 2009-02-25 | 日月光半导体制造股份有限公司 | Lug process and wafer structure of protective detection welding pad |
| US8110931B2 (en) | 2008-07-11 | 2012-02-07 | Advanced Semiconductor Engineering, Inc. | Wafer and semiconductor package |
| TWI372453B (en) | 2008-09-01 | 2012-09-11 | Advanced Semiconductor Eng | Copper bonding wire, wire bonding structure and method for processing and bonding a wire |
| CN101771015B (en) * | 2008-12-31 | 2011-10-12 | 奇景光电股份有限公司 | Wafer structure and wafer packaging structure |
| TWI402955B (en) * | 2010-01-13 | 2013-07-21 | Via Tech Inc | Chip package structure and package substrate |
| US20130241058A1 (en) * | 2012-03-16 | 2013-09-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Wire Bonding Structures for Integrated Circuits |
| TWI490994B (en) * | 2012-09-03 | 2015-07-01 | 矽品精密工業股份有限公司 | Inter-connecting structure for semiconductor package |
| CN103107155A (en) * | 2013-01-29 | 2013-05-15 | 福州瑞芯微电子有限公司 | Double aluminum pad structure and achieving method thereof |
| CN109065459A (en) * | 2018-07-27 | 2018-12-21 | 大连德豪光电科技有限公司 | The production method of pad |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6462426B1 (en) * | 2000-12-14 | 2002-10-08 | National Semiconductor Corporation | Barrier pad for wafer level chip scale packages |
| CN1402304A (en) * | 2001-08-06 | 2003-03-12 | 联华电子股份有限公司 | laser repair process |
| US6630736B1 (en) * | 2000-07-27 | 2003-10-07 | National Semiconductor Corporation | Light barrier for light sensitive semiconductor devices |
| US6664128B2 (en) * | 2002-03-01 | 2003-12-16 | Advanced Semiconductor Engineering, Inc. | Bump fabrication process |
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2004
- 2004-09-22 CN CNB2004100118616A patent/CN100350581C/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6630736B1 (en) * | 2000-07-27 | 2003-10-07 | National Semiconductor Corporation | Light barrier for light sensitive semiconductor devices |
| US6462426B1 (en) * | 2000-12-14 | 2002-10-08 | National Semiconductor Corporation | Barrier pad for wafer level chip scale packages |
| CN1402304A (en) * | 2001-08-06 | 2003-03-12 | 联华电子股份有限公司 | laser repair process |
| US6664128B2 (en) * | 2002-03-01 | 2003-12-16 | Advanced Semiconductor Engineering, Inc. | Bump fabrication process |
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