200816428 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種封裝基板表面結構及其製作方法， 尤指一種適用於提高接點機械強度之封裝基板表面結構及 5 其製作方法。 【先前技術】 隨著電子產業的蓬勃發展，電子產品亦逐漸進入多功 能、南性能的研發方向。為滿足半導體封裝件南積集度 10 (Integration)以及微型化（Miniaturization)的封裝要求，提供 多數主被動元件及線路連接之電路板，亦逐漸由單層板演 變成多層板，以使在有限的空間下，藉由層間連接技術 (Interlayer connection)擴大電路板上可利用的佈線面積而 配合高電子密度之積體電路（Integrated circuit)需求。 15 一般半導體裝置之製程，首先係击晶片載板製造業者 生產適用於該半導體裝置之晶片載板，如基板或導線架。 > 之後再將該些晶片載板交由半導體封裝業者進行置晶、壓 模、以及植球等製程。 半導體封裝結構是將半導體晶片黏貼於基板頂面，進 20 行打線接合（wire bonding)或覆晶（Flip chip)封裝，再於基板 之背面植以錫球以進行電性連接。因此，習知的封裝基板 表面結構請參考圖1A，1B，如圖1A所示，其包括一基板11， 該基板11的表面具有複數電性連接墊12與具有複數開口之 防焊層13，該防焊層之開口係顯露出該電性連接墊12。再 200816428 者於此包ί生連接塾12表面利用電鍵或無電電鍍的方式形 成=屬塾14 ’此金屬塾14的材料可為錫或錄/金等。如圖m 所不，於金屬塾14表面形成一焊料凸塊i5(s〇iderbump)， 最後此焊料凸塊15再經由迴焊㈣㈣⑽此ring)而可與 5 一晶片接合。 4 、、Ό構及製程雖可達到電性連接的目的。然而，此 種習知封裝基板的表面結構，在半導體封裝件高積集度以 及微型化的封裝要求下，此種製程在線路的關鍵尺寸 (critical dimension，如·田 ϊ 〜、 如·取小線寬）不斷縮小的趨勢中，面 臨到接點強度已經不足以承受結構的應力， 式傳播裂紋’因而無法達到可靠度的需求。 直線 【發明内容】 15 20 鑑於上述習知技術之缺點，本發明之主要目的 供-種封裝基板表面結構及其垃^ 紋，能提高封裝牡構之可線式傳播裂 门了衣、、口構之可罪度，俾以符合基板中 鍵尺寸不斷縮小的趨勢。 、、、 關 為達成上揭及其他目的，本發 構’包括有一基板，其表面具有複數;面結 焊層，該防焊層具有複㈣防 二及複數頂端具相面結構之金μ,形成^整声 開口内之該等電性連接墊表面。 寺防谇層 在本發明的封裝基板表面結财，復包括—烊料凸 6 200816428 塊，係形成於該金屬柱之表面。 又上述之結構中，復包括一金屬黏著層，係形成於該 金屬柱表面及該焊料凸塊之間。 在本發明的結構中，該等防焊層開口係顯露出之該等 電性連接墊之部分表面或全部表面。 本發明所提供之封裝基板係可為單層或多層電路板。 15 20 、依上述之結構，本發明之一種封装基板表面結構之製 法：例如可由下述但不限於此之步驟，其包括：提供一基 …表面〃、有複數電性連接墊及一防焊層，該防焊層具 開口以顯露出該等電性連接墊；於該基板表面形成 -導電層；於該導電層表面形成一第一阻層，於該第一阻 層形成複數第一開口，該等第一開口係對應於該等防焊層 開口，於該等第一開口内電鑛形成一金屬才主；移除該第一 二及後盍之導電層；於形成有該等金屬柱之基板表 Π一第二阻層，並於對應於該等金屬柱之處形成複數 、上咏^且該等第二開口之尺寸係小於該等第一開口； 二 '…開口内對该金屬柱進行蝕刻，以形成一頂端具 凹面、、:構之金屬柱；以及移除該第二阻層。 在前述的製法中，復包括於該金屬柱表面形 料 凸塊。 製法中’復包括於形成該焊料凸塊前，於該 金屬柱表面形成一金屬黏著層。 尊防焊爲I明的製法中，該等第一開口之尺寸係不小於該 、、9開口之尺寸，且該等防烊層開口之尺寸係小於或 7 200816428 大於該等電性連接墊之尺寸。 本發月巾此種封裝基板在表面形成頂端具有凹面結 構之金屬柱，藉以提高接點機械強度，可避免習知方法中 接點容易發生之直線式傳_紋，能提高封裝結構之可靠 度俾以付合基板中線路之關鍵尺寸不斷縮小的趨勢。 【實施方式】 二下係藉由特疋的具體實施例說明本發明之實施方 热習此技蟄之人士可由本說明書所揭示之内容輕易地 10 了解本發明之其他優點與功效。本發明亦可藉由其他不同 的具體實施例加以施行或應用，本說明書中的各項細節亦 可基於不同觀點與應用，在不悖離本發明之精神下進行各 種修飾與變更。 口 製法貫施例1 15 請參考圖2A，首先，提供—基板21，其表面具有複數 们迅^連接墊22及一防焊層23，該防焊層23具有複數開口 1 23似顯露出該等電性連接墊22。在此，電性連接墊22的材 料為鋼、錫、鎳、鉻、鈦、銅_鉻合金以及錫、鉛合金中所組 成之群組之一者，本實施例則使用銅。 '〇 接者，如圖2]5至2了所示，乃於圖2A中的A區域之放大 圖，其所揭示者係相關之製作流程。請參考圖2B，於該基 板21表面形成一導電層24。此導電層24的材料可為銅、錫、 鎳鉻、鈦、銅_鉻合金以及錫_鉛合金中所組成之群組之一 者’且其製法係可為物理沉積或化學沈積方式，例如：濺 8 200816428200816428 IX. Description of the Invention: [Technical Field] The present invention relates to a surface structure of a package substrate and a method of fabricating the same, and more particularly to a surface structure of a package substrate suitable for improving the mechanical strength of a joint and a method of fabricating the same. [Prior Art] With the rapid development of the electronics industry, electronic products have gradually entered the research and development direction of multi-function and south performance. In order to meet the packaging requirements of semiconductor package 10 (Integration) and miniaturization (Miniturization), most active and passive components and circuit-connected circuit boards are provided, and gradually evolved from single-layer boards to multi-layer boards to make them limited. Under the space, the interlayer area is used to expand the available wiring area on the board to meet the high electron density integrated circuit requirements. 15 The general semiconductor device process, first of all, is to force the wafer carrier manufacturer to produce a wafer carrier, such as a substrate or lead frame, suitable for the semiconductor device. > These wafer carriers are then transferred to a semiconductor package manufacturer for processing such as crystallization, stamping, and ball placement. In the semiconductor package structure, the semiconductor wafer is adhered to the top surface of the substrate, and 20 rows of wire bonding or Flip chip packages are placed, and then solder balls are implanted on the back surface of the substrate for electrical connection. Therefore, the surface structure of the conventional package substrate is as shown in FIG. 1A, FIG. 1B, which includes a substrate 11 having a plurality of electrical connection pads 12 and a solder resist layer 13 having a plurality of openings. The opening of the solder resist layer reveals the electrical connection pad 12. Further, in 200816428, the surface of the package 12 is formed by a key or electroless plating. The material of the metal crucible 14 may be tin or gold/gold. As shown in FIG. m, a solder bump i5 (s〇iderbump) is formed on the surface of the metal crucible 14, and finally the solder bump 15 is bonded to the fifth wafer via reflow soldering (4) (4) (10). 4, the structure and process can achieve the purpose of electrical connection. However, the surface structure of such a conventional package substrate, in the high degree of integration of the semiconductor package and the miniaturized package requirements, the critical dimension of the process in the line (such as · Tian Hao ~, such as · take small In the trend of shrinking the line width, the contact strength is insufficient to withstand the stress of the structure, and the propagation crack is not able to meet the reliability requirement. Straight line [Summary of the Invention] 15 20 In view of the above disadvantages of the prior art, the main object of the present invention is to provide a surface structure and a pattern of the package substrate, which can improve the linear propagation of the packaged ridge structure, and the mouth. The degree of guilt of the structure is consistent with the trend of shrinking the size of the keys in the substrate. The present invention comprises a substrate having a plurality of surfaces thereon; a surface solder layer having a complex (four) anti-two and a plurality of apical gold structures having a phase structure; Forming the surface of the electrical connection pads within the acoustic opening. The temple anti-mite layer is rich in the surface of the package substrate of the present invention, and includes a block of the material 6 200816428 formed on the surface of the metal column. In the above structure, a metal adhesive layer is formed on the surface of the metal post and between the solder bumps. In the construction of the present invention, the solder mask openings expose portions of the surface or all of the surface of the electrically connected pads. The package substrate provided by the present invention may be a single layer or a multilayer circuit board. 15 20, according to the above structure, a method for fabricating the surface structure of the package substrate of the present invention: for example, the following steps are not limited thereto, including: providing a substrate, a surface, a plurality of electrical connection pads, and a solder resist a layer, the solder resist layer has an opening to expose the electrical connection pad; a conductive layer is formed on the surface of the substrate; a first resist layer is formed on the surface of the conductive layer, and a plurality of first openings are formed in the first resist layer The first openings correspond to the openings of the solder resist layers, and the first or the latter is electrically formed into a metal; the conductive layers of the first and second turns are removed; and the metal is formed The substrate of the column is formed with a second resist layer, and a plurality of upper electrodes are formed at positions corresponding to the metal pillars, and the second openings are smaller in size than the first openings; The metal pillar is etched to form a top surface having a concave surface, a metal pillar; and the second resist layer is removed. In the foregoing method, the bumps are formed on the surface of the metal post. The method of forming includes a metal adhesion layer formed on the surface of the metal post before forming the solder bump. In the method of controlling the welding, the size of the first openings is not less than the size of the opening and the opening of the 9th, and the size of the opening of the anti-mite layer is less than or 7 200816428 is larger than the electrical connection pads. size. The package substrate of the present invention forms a metal column having a concave structure at the top end on the surface, thereby improving the mechanical strength of the contact, thereby avoiding the linear transmission pattern which is easy to occur in the conventional method, and improving the reliability of the package structure.关键 The trend of shrinking key dimensions of the lines in the bonded substrates. [Embodiment] The embodiments of the present invention are described by the specific embodiments of the present invention. Those skilled in the art can easily understand the other advantages and effects of the present invention from the disclosure of the present specification. The present invention may be embodied or applied in various other specific embodiments, and various modifications and changes may be made without departing from the spirit and scope of the invention. Orientation Method 1 15 Referring to FIG. 2A, firstly, a substrate 21 is provided having a plurality of surface pads 22 and a solder resist layer 23 on the surface thereof. The solder resist layer 23 has a plurality of openings 1 23 as shown. The electrical connection pad 22 is electrically connected. Here, the material of the electrical connection pad 22 is one of a group consisting of steel, tin, nickel, chromium, titanium, copper-chromium alloy, and tin or lead alloy. In this embodiment, copper is used. The 'connector', as shown in Fig. 2, 5 to 2, is an enlarged view of the area A in Fig. 2A, which is disclosed in the related production flow. Referring to FIG. 2B, a conductive layer 24 is formed on the surface of the substrate 21. The material of the conductive layer 24 may be one of a group consisting of copper, tin, nickel chrome, titanium, copper-chromium alloy and tin-lead alloy, and the manufacturing method thereof may be physical deposition or chemical deposition, for example, : Splash 8 200816428
程所需之電流傳導路徑。 以曝光及顯影形成第一開口 25a， 於該等防焊層開口 23a，且該第一 再者三請參考圖2C，於該導電層24表面形成-第-阻 層25 ’此第-阻層25的材料係可為乾膜或液態光阻，之後 該等第一開口 25a係對應 開口 25a的尺寸不小於該The current conduction path required for the process. The first opening 25a is formed by exposure and development, and the solder resist layer opening 23a is formed, and the first third is referred to FIG. 2C, and a first-resist layer 25' is formed on the surface of the conductive layer 24. The material of 25 may be a dry film or a liquid photoresist, and then the first openings 25a are not smaller than the size of the opening 25a.
20 等防焊層開口 23a的尺寸。 然後，請參考圖2D，於該第一開口25a内利用電鍍方式 形成一金屬柱26。此金屬柱26使用的材料係可為銅、鎳、 鉻鈦、銅/鉻合金以及錫/鉛合金所組成之群組之一者。 接著，如圖2E所示，移除在圖2D中之第一阻層25及其 所覆蓋之導電層24。 再如圖2F所示，於具有此金屬柱26之基板21表面形成 一第二阻層27，此第二阻層27的材料可為乾膜或液態光 阻’之後於對應該金屬柱26之處以曝光及顯影形成一第二 開口27a，且該等第二開口 27a之尺寸係小於該等第一開口 25a之尺寸。 接著，如圖2G所示，於第二開口 27a内對金屬柱26進行 濕式蝕刻（wet etching)以於該金屬柱26頂端形成一凹面結 構26a。再如圖2H所示，移除圖2G中之第二阻層27。 此外，如圖21所示，於此金屬柱26表面利用物理沉積咬 化學沈積方式，例如··_鍵、蒸鍍、電鍍、無電鑛等方式 形成一金屬黏著層28。此金屬黏著層28的材料可為有機保 9 200816428 焊劑（Organic Solderability Preservatives ; OSP)、錫、銀或 金等等材料。本實施例則使用無電鍍的方式將一有機保焊 劑沈積於該金屬柱26表面。 最後，如圖2 J所示，再利用電鍍或印刷等方式以形成一 5 焊料凸塊29。 製法實施例2 本實施例與製法實施例1之不同處，係在於本實施例中 該等防焊層開口 23a之尺寸係大於該等電性連接墊22之尺 寸，請參見圖2J’ ；而製法實施例1中該等防焊層開口 23a之 10 尺寸係小於該等電性連接墊22之尺寸，請見圖2 J。本實施 例製法之相關說明可參考製法實施例1之說明及圖2 A至2 J 而得知，故不贅述。 結構實施例1 本實施例如圖2J所示，本發明之一種封裝基板表面結 15 構，係包括：一基板21，其表面具有複數電性連接墊22及 一防焊層23，該防焊層23具有複數開口 23a以顯露出該等電 丨性連接墊22;以及複數金屬柱26,係形成於該等防焊層開 口 23a内之該等電性連接墊22表面上，該金屬柱26頂端係具 有凹面結構26a。 20 上述之結構，復包括一焊料凸塊29，係形成於該金屬 柱26之表面。 上述之結構，復包括一金屬黏著層28，係形成於該金 屬柱26表面及該焊料凸塊29之間。 上述之結構，其中，該金屬黏著層28使用的材料係為 200816428 有機保燁劑、錫或銀。 上述之結構，其中，該等防焊層開口 23a係顯露出之該 等電性連接墊22之部分表面。 上述之結構，其中，該等金屬柱26使用的材料係為銅、 5 鎳、鉻、鈦、銅/鉻合金以及錫/鉛合金所組成之群組之一者。 結構實施例2 本實施例如圖2J，所示，其與結構實施例1之不同處， 係在於其中該等防焊層開口 2 3 a係顯露出之該等電性連接 墊22之全部表面。本實施例相關内容說明可參考結構實施 10 例1之說明及圖2 J而得知，故不贅述。 、 綜上所述，此種封裝基板的結構及製程，係形成在頂 端具有凹面結構之金屬柱，藉以提高接點機械強度，可避 免習知方法中接點容易發生之直線式傳播裂紋，能提高封 裝結構之可靠度，俾以符合基板中線路之關鍵尺寸不斷縮 舉例而已，本發明所 所述為準，而非僅限20 etc. Size of the solder mask opening 23a. Then, referring to FIG. 2D, a metal post 26 is formed by electroplating in the first opening 25a. The material used for the metal post 26 can be one of a group consisting of copper, nickel, chrome titanium, copper/chromium alloy, and tin/lead alloy. Next, as shown in Fig. 2E, the first resist layer 25 and its conductive layer 24 are removed in Fig. 2D. As shown in FIG. 2F, a second resist layer 27 is formed on the surface of the substrate 21 having the metal pillars 26. The material of the second resistive layer 27 may be a dry film or a liquid photoresist 'after the corresponding metal pillars 26 A second opening 27a is formed by exposure and development, and the second openings 27a are smaller in size than the first openings 25a. Next, as shown in Fig. 2G, the metal pillars 26 are wet-etched in the second opening 27a to form a concave surface structure 26a at the top end of the metal pillars 26. As shown in FIG. 2H, the second resist layer 27 in FIG. 2G is removed. Further, as shown in Fig. 21, a metal adhesive layer 28 is formed on the surface of the metal post 26 by physical deposition bite chemical deposition, for example, bonding, vapor deposition, electroplating, electroless ore plating. The material of the metal adhesion layer 28 may be a material such as Organic Solderability Preservatives (OSP), tin, silver or gold. In this embodiment, an organic solder resist is deposited on the surface of the metal pillar 26 by electroless plating. Finally, as shown in Fig. 2J, a plating bump 29 is formed by electroplating or printing. The second embodiment of the present invention is different from the manufacturing method embodiment 1 in that the size of the solder resist layer opening 23a is larger than the size of the electrical connection pads 22, see FIG. 2J'; In the first embodiment of the method, the size of the solder resist layer opening 23a is smaller than the size of the electrical connection pads 22, as shown in Fig. 2J. For a description of the method of the present embodiment, reference may be made to the description of the method of the first embodiment and to the drawings of FIGS. 2A to 2J, and thus the description is omitted. Structure Embodiment 1 This embodiment, as shown in FIG. 2J, is a package substrate surface structure 15 comprising: a substrate 21 having a plurality of electrical connection pads 22 and a solder resist layer 23 on the surface thereof, the solder resist layer 23 has a plurality of openings 23a to expose the electrical connection pads 22; and a plurality of metal posts 26 formed on the surfaces of the electrical connection pads 22 in the solder mask openings 23a, the tops of the metal posts 26 It has a concave structure 26a. The above structure includes a solder bump 29 formed on the surface of the metal post 26. The above structure includes a metal adhesive layer 28 formed between the surface of the metal pillar 26 and the solder bumps 29. In the above structure, the material used for the metal adhesive layer 28 is 200816428 organic protective agent, tin or silver. In the above structure, the solder resist opening 23a exposes a part of the surface of the electrical connection pad 22. In the above structure, the material used for the metal pillars 26 is one of a group consisting of copper, 5 nickel, chromium, titanium, copper/chromium alloy, and tin/lead alloy. Structural Embodiment 2 This embodiment, as shown in Fig. 2J, differs from the structural embodiment 1 in that the entire surface of the electrical connection pads 22 in which the solder resist openings 2 3 a are exposed. The description of the related content of the embodiment can be referred to the description of the configuration of the first embodiment and the description of FIG. 2J, and therefore will not be described again. In summary, the structure and process of the package substrate are formed by forming a metal pillar having a concave structure at the top end, thereby improving the mechanical strength of the joint, and avoiding the linear propagation crack which is easy to occur in the conventional method. Increasing the reliability of the package structure, which is exemplified by the critical dimensions of the lines in the substrate, as described in the present invention, and not limited to
上述實施例僅係為了方便說明而 主張之權利範圍自應以申請專利範圍 於上述實施例。 2〇 【圖式簡單說明】 圖1AWB係習知之封装基板表面結構 面結構 圖係本發明一較佳實施例之封 : 製作流程剖視圖。 '"土板表 圖⑽本發明另-較佳實施例之封裝基板表面結構剖 200816428 視圖。 【主要元件符號說明】 11,21 基板 12,22 電性連接墊 13,23 防焊層 14 金屬墊 15 焊料凸塊 23a 防焊層開口 24 導電層 25 第一阻層 25a 第一開口 26 金屬柱 27 第二阻層 27a 第二開口 28 金屬黏著層 29 焊料凸塊 12The above-described embodiments are only for the convenience of the description, and the claims are intended to cover the above embodiments. 2A BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1AWB is a conventional package substrate surface structure. FIG. 1A is a cross-sectional view of a process flow of a preferred embodiment of the present invention. '" Soil Board Table (10) A cross-sectional view of the surface of the package substrate of another preferred embodiment of the present invention. [Main component symbol description] 11,21 substrate 12, 22 electrical connection pad 13, 23 solder resist layer 14 metal pad 15 solder bump 23a solder resist opening 24 conductive layer 25 first resist layer 25a first opening 26 metal pillar 27 second resistive layer 27a second opening 28 metal adhesive layer 29 solder bump 12