TW200840429A - Circuit board structure having buffer layer and method for fabricating the same - Google Patents

Abstract

A circuit board structure having a buffer layer is disclosed. The structure comprises a circuit board and a buffer layer. The surface of the circuit board includes a plurality of conductive pads and a solder mask. The solder mask has a plurality of openings to expose the conductive pads. The buffer layer corresponds to the conductive pads and is disposed inbetween the conductive pads and the surface of the circuit board. The present invention further comprises a method for fabricating the same. The buffer layer of the present invention has a buffer effect to avoid the break-down of the electricity of the circuit board structure.

Description

200840429 IX. Description of the Invention: [Technical Field] The present invention relates to a circuit board structure having a buffer layer and a method of manufacturing a pot, and particularly to an electrical connection with an electronic component, and avoiding a 5 break. The failure of the circuit board structure with buffer layer and its maker, go to [previous technology], (4) the booming development of the electronics industry, electronic products have gradually entered the direction of multi-functional, high-performance research and development. In order to meet the packaging requirements of semiconductor package 10 (Integratl) and miniaturization, the majority of active and passive components and circuit-connected circuit boards are also evolving from two-layer boards. Multi-layer boards are used to expand the integrated circuit area of high electron density (Integrated coffee calling requirements) by enlarging the available wiring area on the circuit board by the interlayer connection technique (here α __1〇η) in a limited space. The process of the semiconductor device is firstly produced by a wafer carrier manufacturer to produce a wafer carrier board suitable for the semiconductor device, such as a circuit board or a wire*, and then the 3x wafer carrier board is placed by a +conductor packager for crystallization. Processes such as stamping, ball-planting, etc. The semi-V body package structure is to adhere the wafer to the top surface of the circuit board, perform 20-wire bonding, or package the wafer in a flip-chip bonding manner (Fllpchlp). The board is electrically connected. The solder ball is implanted on the back of the circuit board to electrically connect to an external electronic device such as a printed circuit board. For the surface structure of the flip chip bonded circuit board, please refer to FIG. 1A and FIG. 1A The surface of the circuit board 1 1 includes a plurality of electrical connection pads 12 5 200840429 solder layer 13 , and the solder resist layer 13 reveals the connection pads 2 . Furthermore, as shown in FIG. 1B In the electrical connection pad 12 =::: material bump 14 (solderbump), and finally the solder bump 14 is further π, 烊 (reficrn soldering) can be bonded to a wafer. ", the circuit of this structure Plate, hot material (ie cooling or port due to the wafer's rate of shrinkage is slower than the board and the solder bumps are sheared due to temperature 10 h, the board will produce (10), and the solder ≎ The joint between the pads is broken, and the appearance of the electrical connection between the circuit board and the wafer is broken. Therefore, the electrical connection between the circuit board and the wafer is f, and the electrical properties of the circuit board are strengthened. In view of the above, the present invention provides a circuit board structure having a buffer layer, comprising: a circuit board and a buffer layer. The surface of the circuit board has a plurality of electrical connection pads and a solder mask layer. The solder layer has a plurality of openings to expose the electrical connection pads. The buffer layer configuration corresponds to the electrical connection pads 'and between the electrical connection pads and the surface of the circuit board. _ In the present invention, The circuit board includes a dielectric layer and an inner layer line, and the buffer layer is formed on the dielectric layer on the surface of the circuit board, wherein the buffer layer is entangled in the dielectric layer and is less likely to be roughened by the etching liquid. Here, the dielectric layer included in the circuit board may be, for example, selected from the group consisting of ABF (Ajin〇m〇t〇Build_Up Film), bis-succinimide bismuth imide/trinitrogen trap (this job 14 is as heart 1^_ ;]81[), benzoxene butadiene (benZ〇Cyl〇butene; BCB), liquid crystal polymer (Liquid 6 200840429

Crystal Polymer), polyamidamine (p〇lyimide; ρι), polyvinyl ether (P〇iy (Phenylene ether)), polytetrafluoroethylene (p〇iy (_bu f-thy丨ene)), aromatic nylon The group of (Aramide), epoxy resin and glass fiber. Preferably, the dielectric layer can be abf. Further, the buffer layer may be a polymer material, and preferably an anthracene group. For example, the following formula 1 is shown: Formula 1 ch3 ch3

10

20 —(Ar —(S丨卜〇一寺一)m—) “ch3 ch3 followed by... 2 said 1 TM — solder bumps or —metals ^ can be formed on the electrical connections z. A connection pad Here, the group formed by the solder bumps is two: silver, gold, gold, turn, and the materials used thereof, preferably tin, and the metal layer is used for example. It may be one of a group consisting of organic/palladium/gold and tin-silver-silver, nickel, nickel/gold, nickel-tin: preferably tin. In the circuit board of the present invention, a tie plate. The fishing layer or the multi-layer circuit is manufactured according to the above-mentioned invention by the following, but not limited to, the circuit board structure, for example, the steps of the board: the board is completed. Then, the teacher completes the '& The electric layer to be completed. Then, the surface of the surface forms a patterned metal layer to the dance: slow::: the surface of the board forms a metal layer and the layer of the layer is to be completed, ▲ Wherein, in the formation of the gold buffer layer, a plurality of shell-out metal layers are formed as electricity 7 200840429 5 Γ 10 15 20 The surface of the circuit board structure of the present invention is formed by forming a patterned buffer layer on the surface of the circuit board: or is formed by a lithography process. The screen includes a dielectric layer and a dielectric layer. The inner layer circuit, Qian Chong: on the dielectric layer on the surface of the circuit board board board completed by the temple, its t, slow = (4) is formed in the circuit to be completed is roughened by the corrosive liquid. A mesh is less difficult than the dielectric layer The material of the circuit board structure of the invention is copper, nickel, complex, titanium, copper/chromium alloy and:: 丄: a group of materials of the genus layer. Preferably, it may be copper. The circuit of the present invention is formed after the buffer layer is formed into a buffer layer, and the metal layer is formed by: = zhong ' complex is included in the shape of the circuit board and the surface of the buffer layer is roughened. Before the fabrication of the circuit board structure of the present invention, the surface of the circuit board to be completed is roughened on the surface of the circuit board to be completed. The circuit board of the present invention is completed: The surface of the connection pad forms an i-bump or a gold== tan bump is formed, for example. In the present invention, the size of the buffer layer is larger than that of the electrical connection pad, and the metal layer may be formed by printing or electron microscopy. The circuit board structure with the buffer layer can be used as the core "compared to the dielectric layer, which is less susceptible to coarsening of the rot

The process makes the buffer; I combine the bonding of the layer or the buffer layer with the electrical connection pad. For example, first roughen the dielectric layer, then the buffer layer and the electrical connection (4) ^ re-open / into the buffer layer and electrical connection塾, resultant force, or first opening: What is the bonding strength of the buffer layer and the dielectric layer is less than Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ Μ 粗 粗 粗 粗 粗 粗 粗 粗 粗 粗 粗 粗 粗 粗 粗 粗 粗 粗 粗 粗 粗 粗 粗 粗 粗 粗 粗 粗Electric Lianyou Punch Layer " Private layer, buffer layer blood mine material Kui j Ο 10 15 The overall structure of the human mantle and electrical connection pad has:: Force small buffer space to release stress, can reduce deer ... The dry bumps and the electrical connections are broken. Because of the ~, Mingzhi has the reliability of the product. 9 Further, the circuit board structure can be strong. [Embodiment] The present invention will be described by way of specific embodiments, and those skilled in the art can understand other advantages and effects of the present invention from the disclosure of the present specification. Specific embodiments of the present invention are implemented or applied. In the present specification: = also: the same may be based on different viewpoints and applications, and may not be modified or changed from the present invention. In the embodiments of the present invention, the drawings are simplified. The drawings show only the components related to the present invention, and the indications are obvious: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The number of components::= The example is - selective design, and its component layout type may be more complicated. Please refer to Figure 2 以及 please and 20 200840429 " 2D is a cross-sectional view of the process of forming a circuit board with a buffer layer, 3Α to 3D is a partial enlarged process top view in which the electrical connection pads are formed in FIGS. 2A to 2D. First, please refer to FIG. 2A and FIG. 3A simultaneously to provide a circuit board 20 to be completed. The circuit board 20 to be completed may be two or more layers of the circuit board 20 to be completed, and the inside thereof contains a dielectric. Layer 201 and inner layer lines (not shown). Here, the dielectric layer 201 may be, for example, selected from the group consisting of ABF (Ajinomoto Build-up Film), Bismaleimide triazine (BT), and benzocylobutene (BT). BCB), 10 Liquid Crystal Polymer, Polyimide (PI), Poly (phenylene ether), Poly (tetra-fluoro-ethylene) One of the groups consisting of aromatic polyamide, epoxy resin, and glass fiber, in this embodiment, ABF is used. The surface of the circuit board 20 to be completed can be formed into a patterned buffer layer 21 by screen printing. The patterned buffer layer 21 can also be formed by using lithography technology, that is, the circuit board 20 to be completed first. The surface is first formed into a & buffer layer 21, followed by exposure and development processes to form the patterned buffer layer 21. In Fig. 3A, there is shown a partially enlarged top view of the patterned buffer layer 21, which is formed on the circuit board 20 to be completed. Further, the material of the buffer layer 21 to be used may be an amphoteric oxygen polymer having an aromatic group. For example, the following formula 1 is shown: Formula 1 ch3 ch3

/ I I —(Ar — (Si-〇-Si—)m—)n—

II ch3 ch3 10 200840429 Here, in this embodiment, before the buffer layer 21 is formed on the surface of the +-way plate to be completed, a surface etching liquid such as potassium permanganate may be added to the circuit board to be completed. (_4) Perform a roughening process, and then form this buffer: 2 or ^ ' can be formed on the buffer layer 21 after the circuit board to be completed: 5 and then use potassium permanganate (KMn〇4) for roughening Process. Among them, the characteristics of the buffer layer u ^ material are relatively thinner than the dielectric layer on the surface of the circuit board 20 to be completed, and have characteristics that are less likely to be roughened by the etching liquid. Therefore, the roughening and the technology can be used to form an electrical connection pad on the buffer layer in the subsequent process, so that the bonding force between the buffer layer and the dielectric layer or the buffer layer and the electrical connection pad becomes small, for example, First, the dielectric layer is roughened to form a buffer layer and an electrical connection layer, and the bonding force between the buffer layer and the electrical connection pad is smaller than that of the buffer layer and the dielectric layer #, and then the dielectric layer and the buffer layer are formed first. The electrical layer and the buffer layer, and the electrical connection pad is formed on the buffer layer, the bonding force between the buffer layer and the dielectric layer is less than the bonding force between the buffer layer and the electrical connection pad, so the dielectric layer is subjected to stress caused by thermal shock, The buffer structure and the overall structure of the electrical connection have a buffer space with less bonding force to release stress. [Next, please refer to FIG. 2A and FIG. 3Β at the same time, the surface of the circuit board 20 to be completed is formed into a metal layer 22, and a part of the metal layer corresponds to the surface of the buffer layer 21. This metal layer 22 can be formed by electric forging. The material of the gold 20 layer 22 can be used for one of the group consisting of copper, lanthanum, lanthanum, chin, copper/coalloy and tin/garland. Copper is used in this embodiment. Then, referring to FIG. 2C and FIG. 3C, the surface of the circuit board 2G to be completed on which the metal layer 22 is formed is coated with a solder resist layer 23. The material that can be used for this solder resist layer 23 is green lacquer. 11 200840429 Finally, while referring to FIG. 2D and FIG. 3D, the solder resist layer 23 forms a plurality of openings 231 and exposes the metal layer 22 as an electrical connection pad at the corresponding buffer layer 21 by exposure and development. 221. Here, the buffer layer 21 corresponding to the electrical connection pad 221 has a size larger than that of the electrical connection pad 5^21. After the completion of the foregoing process, the structure of the circuit board 2 of one of the present invention is completed.

C 10 15 20 Therefore, as shown in Fig. 2D, the present invention can provide a circuit board structure having a buffer layer via the foregoing method, but is not limited thereto, and includes: a circuit board 2 and a buffer layer 21. The surface of the circuit board 2 has a plurality of electrical connection pads and a solder mask layer 23, and the solder resist layer 23 has a plurality of openings 23 to expose the temple electrical connection pads 22, and the buffer layer 21 is configured to correspond to the electricity. The connection (4) 221 is between the electrical connection pad 221 and the surface of the circuit board 2. However, please refer to FIG. 4, the electrical connection pad 221 in the circuit board 2 = surface formation - the solder bump 31' can be electrically connected to the external electronic device. For the wafer. Here, the shape of the welding shaft 31 can be formed by screen printing or electric ore, and the material used for the material bump 31 is, for example, copper, tin, silver, silver, ruthenium, gold, platinum, and the like. One of the alloys formed uses tin. In this embodiment, the distance is far lower. Referring to Fig. 5, the solder bumps 31' as shown in Fig. 4 are not used, and the surface is formed with a metal back layer 32. The metal back layer is as follows! 2: Electrical connection of external electronic components 'This external electronic component is an example: ^, the formation of this metal backing layer 32 is the formation of no electric power f. The metal back layer 32 is such that the (four) material is a group consisting of tin, silver, nickel, nickel/gold, nickel/palladium/gold, and tin/lead, in this embodiment. Use tin. In summary, the present invention forms a buffer layer between the electrical connection pads and the material on the circuit board to separate the electrical connection pads. The slowness: "Good ground can be an aromatic-based helium-oxygen polymer, and has characteristics that are less likely to be roughened compared with dielectric materials. The present invention has a buffer layer: a plate structure, when the circuit When the board is electrically connected via a bump or a metal, such as a wafer, since the buffer layer 10 15 20 is not easily roughened (four), the roughening process can be used to buffer the dielectric layer. Or the bonding force between the buffer layer and the electrical connection pad becomes small, and the thermal shock generates stress, so that the dielectric layer, the buffer layer and the electrical connection are further 塾=the structure has a buffer space with less bonding force, and the solder should be reduced to be in the solder. The failure between the bump and the electrical connection pad or the metal connection is broken. Therefore, b, the structure of the invention can enhance the reliability of the product. The circuit board of the above embodiment is for convenience of explanation. For example, the scope of the claims is intended to apply for a patent; in the above embodiments, and not limited to [simplified description of the drawings] Figs. 1A to 1B are conventionally known as the surface structure of the ία The electrograms 2A to 2D of the diagram buffer layer are the same as the present invention. The preferred embodiment having a flow path cross-sectional plate structure shown in FIG. FIGS. 3 A to 3 D _ based on the clever respectively correspond to FIGS. 2A to 2D of a buffer layer 13200840429

Figure 4 is a cross-sectional view showing the formation of solder bumps on the surface of a circuit board having a buffer layer in accordance with a preferred embodiment of the present invention. Figure 5 is a cross-sectional view showing the formation of a metal back layer on the surface of a circuit board structure having a buffer layer in accordance with a preferred embodiment of the present invention. [Main component symbol description]

12 Electrical connection pads H Solder bumps 20 Board to be completed 21 Buffer layer 221 Electrical connection pads 231 Opening holes 32 Metal back layers 14

Claims (1)

200840429 X. Patent application scope: h ~ a circuit board structure with a buffer layer, including: a circuit board, i: the day of the work, / the surface has a plurality of electrical connection pads and a solder mask, 曰, Β μ垾The layer has a plurality of openings to expose the electrical connection pads; and the balance layer is disposed between the electrical connection pads of the electrical connection pads and the surface of the circuit board. And the circuit board having a buffer layer as described in the patent application scope, *|J" 1 y ^ Uhai pen board includes a dielectric layer and an inner layer line, and The buffer layer is formed on the dielectric layer on the surface of the circuit board. In the crucible, the buffer layer is coarser than the dielectric layer. ^3. A circuit board structure having a buffer layer as described in claim 2, wherein the 'Hi-buffer layer' is a fluorinated polymer having an aromatic group. The female board stated that the circuit board with the buffer layer described in the second paragraph of the patent scope is °F, Zhonghehai; the electric layer is selected from ABF (Ajinomoto Build-up Film), bissuccinimide bismuth imide/three Nitrogen trap (9) with iazine, BT), benzidine, biphenylbutene (Bcb), liquid crystal polymer, polypyridamine (p〇iyimide; PI), One of a group consisting of P〇ly (phenyiene ether), p〇iy (tetra-fluoroethylene), aromatic polyamide (Aramide), epoxy resin, and glass fiber. 5. The circuit board structure having a buffer layer according to claim 1, wherein the buffer layer has a size larger than a size of the electrical connection pad. 6. The circuit board with a buffer layer as described in claim 1 of the Shenqing patent scope 15 200840429 The structure includes a solder % "& t枓 bump formed on the surface of the electrical connection pads. 7. The circuit board structure having a buffer layer as described in claim 1 of the patent application includes a metal-bonding layer formed on the electrical connection: 塾ί face 0 and 槿8 bean ^ Γ patent range 7 The circuit board with buffer layer described in the item: the material used for the base metal back layer may be a group consisting of organic solder resist, de-ruthenium, niobium, nickel, nickel/gold, nickel/le/gold, and tin/wrong. One#. 10 15 20 叫二如: Please specify: the circuit board with buffer layer mentioned in item 1 of J range ° 〃, 5 hai circuit board is a two-layer or multi-layer circuit board. The invention comprises a method for manufacturing a circuit board structure with a buffer layer, the steps of which provide a circuit board to be completed, === a buffer layer formed on the surface of the road surface - patterned; 2: a surface of the second board is formed - a metal layer, And a part of the metal layer corresponds to the surface of the buffer layer; and in the main layer + the second solder layer formed with the metal layer, the solder resist layer is formed in the corresponding: punch:: surface of the circuit board - anti-exposure $ + M Μ, , % layer is formed into a plurality of openings and * negative 5 ohm metal layer as an electrical connection pad. The material used in the buffer layer according to claim 10 of the patent application scope may be a money-based polymer having an aromatic group, which is to be produced by the method described in Patent No. _1G, wherein the book of the -π成成The surface of the board is made up of a buffer layer of screen printing. The pattern is formed by a spoon method. 16 10 15 20 200840429 / -13. As described in the patent application, the surface of the circuit board to be completed is a layer. The U-shirt process is used to form the patterning delay. 14. The circuit board to be completed as described by the café of the patent application includes a dielectric layer and an inner layer circuit, and is formed on the surface of the circuit board to be completed. Layer: The buffer layer is less susceptible to corrosion (4) than the dielectric layer. The manufacturing method according to the first aspect of the invention, wherein the friend, (1), and the size are larger than the size of the electrical connection pad. Please refer to the production method described in (1) 1G. In 1st, the material of the metal layer is one of the group consisting of copper, rhetoric, and gold. Chin, copper/coalloy, and tin/mismatch 7. After the method of forming the buffer layer and forming the metal layer, the method of forming and roughening is performed to roughen the surface of the circuit board and the buffer layer. . The manufacturing method described in the first aspect of the invention is incorporated in the first aspect of the circuit board to be completed before the roughening of the surface of the circuit board to be completed. The manufacturing method described in the item 1G includes forming a solder bump on the surface of the 3-layer connection pad. 20. The manufacturing method according to claim 19, wherein the solder bump is formed by printing. 21· The solder bumps are formed by electroplating according to the method described in Item 19 of the 4th (4), respectively. , A series 17 200840429 22. The manufacturing method described in claim 10 of the patent application is included in The surface of the electrical connection pad forms a metal backing layer. The method of manufacturing according to claim 22, wherein the metal back layer is formed by electroless plating.