TWI693874B - Circuit carrier board structure and manufacturing method thereof - Google Patents

Abstract

A circuit carrier board structure includes a first substrate, a second substrate, an adhesive layer and a plurality of pads. The first substrate includes a first surface and a second surface opposite to the first surface, and also includes a plurality of first build-up layers stacked sequentially. The first build up layer includes a first dielectric layer and a first circuit layer, and the first build-up layers electrically connect with each other. The second substrate includes a third surface and a fourth surface opposite to the third surface, and also includes a plurality of second build-up layers stacked sequentially. The second build-up layer includes a second dielectric layer and a second circuit layer, and the second build-up layers electrically connect with each other. The adhesive layer is between the first substrate and the second substrate. The second surface is configured to the third surface. The pads are on the first surface electrically connect with the first circuit layer. The first substrate electrically connects to the second substrate. A manufacturing method of the circuit carrier board structure is also provided.

Description

Line carrier board structure and manufacturing method thereof

The invention relates to a carrier board structure and a manufacturing method thereof, and particularly relates to a circuit carrier board structure and a manufacturing method thereof.

Generally speaking, the multi-layer circuit structure of the circuit board is mostly produced by a build-up method or a laminated method, so it has the characteristics of high circuit density and reduced circuit spacing. For example, the manufacturing method of the multilayer circuit structure is that copper foil (Copper foil) and film (PrePreg) are formed into a layered structure, and the layered structure is repeatedly laminated and stacked on the core layer to form a multilayer circuit In order to increase the internal wiring space of the multilayer circuit structure, the conductive material on the build-up structure can form a conductive circuit according to the required circuit layout, and the blind hole or the through hole of the build-up structure can be additionally filled with conductive material to conduct the layers . In this way, the multi-layer circuit structure can be adjusted according to the number of circuit structures required and manufactured by the above method.

With the advancement of technology, all types of electronic products are developing towards high speed, high efficiency, and thin, light, and short. Under this trend, the number of layers of the multilayer circuit structure has also increased to meet the design of more complex electronic products. However, as the number of layers of the multilayer circuit structure increases, the warpage issue of the multilayer circuit structure will become more serious. In addition, the manufacturing process of the multi-layer circuit structure is complicated, which increases the difficulty of the manufacturing process of the ultra-fine circuit, which can not reduce the cost, and has the problem of poor production yield.

The invention provides a circuit carrier board structure and a manufacturing method thereof, which can improve the warpage problem of the circuit carrier board structure, reduce manufacturing difficulty, manufacturing cost, and increase production yield, and have good quality.

The manufacturing method of the circuit board structure of the present invention includes the following steps. Provide temporary carrier board. A first substrate is formed on the temporary carrier. The first substrate has a first surface and a second surface opposite to the first surface. A second substrate is provided, having a third surface and a fourth surface opposite to the third surface. An adhesive layer is provided on one of the first substrate and the second substrate, and the adhesive layer is located between the first substrate and the second substrate. The second surface of the first substrate is combined with the third surface of the second substrate. And, the temporary carrier board is removed, wherein the first substrate is electrically connected to the second substrate.

In an embodiment of the invention, the above step of forming the first substrate includes forming a release layer on the temporary carrier. And, a plurality of first build-up layers are sequentially stacked on the release layer. Each first build-up layer includes a first dielectric layer and a first circuit layer. The first build-up layers are electrically connected to each other.

In an embodiment of the invention, the step of providing the second substrate includes providing a second base. A plurality of second build-up layers are sequentially stacked on the second substrate, wherein each second build-up layer includes a second dielectric layer and a second circuit layer. And, a plurality of conductive pads are formed on the third surface, and the conductive pads are electrically connected to the second circuit layer. The second build-up layers are electrically connected to each other.

In an embodiment of the invention, the above manufacturing method further includes the following steps. A plurality of through holes are formed to penetrate the first substrate and expose the conductive pads. A seed layer is formed on the first surface, and a through hole is filled to contact the conductive pad. A photoresist pattern covering part of the seed layer is formed to expose part of the seed layer. A plurality of conductive structures are formed from the partially exposed seed layer, and each conductive structure is electrically connected to each conductive pad and the first circuit layer. The photoresist pattern and the seed layer covered by the photoresist pattern are removed.

In an embodiment of the invention, the step of forming the first substrate further includes forming a plurality of conductive pillars on the second surface and electrically connecting the first circuit layer.

In an embodiment of the invention, the step of providing the second substrate includes providing a second base. A plurality of second build-up layers are sequentially stacked on the second substrate, wherein each second build-up layer includes a second dielectric layer and a second circuit layer. And, a plurality of conductive blind holes are formed on the third surface, and the conductive blind holes are electrically connected to the second circuit layer. The second build-up layers are electrically connected to each other.

In an embodiment of the present invention, the above-mentioned step of combining the first substrate to the second substrate further includes combining the conductive pillar to the conductive blind hole to electrically connect the conductive pillar and fill the conductive blind hole to form a conductive structure. The conductive structure is electrically connected to the second circuit layer and the first circuit layer.

In an embodiment of the invention, the above manufacturing method further includes forming a plurality of connection pads on the first surface, the connection pads are electrically connected to the first circuit layer, wherein the line width of the first circuit layer is smaller than the lines of the connection pads width. A solder resist layer is formed to cover the first surface and the fourth surface, and the solder resist layer exposes a portion of the connection pad, the first circuit layer, and the second circuit layer. And, perform surface treatment procedures.

In an embodiment of the invention, the above-mentioned manufacturing method further includes placing a plurality of electronic components on the first surface of the first substrate, and the electronic components are electrically connected to the connection pad and the first circuit layer. And, a plurality of solder balls are provided to electrically connect the second circuit layer.

The circuit board structure of the present invention includes a first substrate, a second substrate, an adhesive layer, and a plurality of connection pads. The first substrate has a first surface and a second surface opposite to the first surface, including a plurality of first build-up layers stacked sequentially, each first build-up layer includes a first dielectric layer and a first circuit layer, and each of the first build-up layers The layers are electrically connected to each other. The second substrate has a third surface and a fourth surface opposite to the third surface, including a plurality of second build-up layers stacked sequentially, each second build-up layer includes a second dielectric layer and a second circuit layer, and each second build-up layer The layers are electrically connected to each other. The adhesive layer is located between the first substrate and the second substrate. The second surface is combined to the third surface. The connection pad is located on the first surface and is electrically connected to the first circuit layer. The first substrate is electrically connected to the second substrate, the line width of the first circuit layer is less than the line width of each connection pad, and the line width of the first circuit layer is less than or equal to 10 microns.

In an embodiment of the invention, the above-mentioned first substrate further includes a plurality of through holes penetrating the first substrate. The second substrate further includes a second substrate and the second build-up layer is disposed on the second substrate, and a plurality of conductive pads are located on the third surface and are electrically connected to the second circuit layer. The through hole exposes the conductive pad, and the conductive pad fills in the through hole to electrically connect the connection pad, the conductive pad, the first circuit layer and the second circuit layer.

In an embodiment of the invention, the top surface of each conductive structure is close to the first surface, the bottom surface of the conductive structure is close to the second surface, and the diameter of the top surface of the conductive structure is larger than the diameter of the bottom surface. The top surface of the first circuit layer is close to the second surface, the bottom surface of the first circuit layer is close to the first surface, and the diameter of the top surface of the first circuit layer is larger than the diameter of the bottom surface.

In an embodiment of the invention, the above-mentioned first substrate further includes a plurality of conductive posts on the second surface to electrically connect the first circuit layer. The second substrate further includes a second substrate and the second build-up layer is disposed on the second substrate, and a plurality of conductive blind holes are located on the third surface and are electrically connected to the second circuit layer. The conductive posts are filled with conductive blind holes to form a plurality of conductive structures, and the conductive structures are electrically connected to the first circuit layer and the second circuit layer.

In an embodiment of the invention, the circuit board structure described above further includes a solder mask covering the first surface and the fourth surface. The solder resist layer exposes part of the connection pad, the first circuit layer and the second circuit layer.

In an embodiment of the invention, the circuit board structure described above further includes a plurality of electronic components located on the first surface of the first substrate, and a plurality of solder balls electrically connected to the second circuit layer. The electronic component is electrically connected to the connection pad and the first circuit layer.

Based on the above, the circuit carrier structure and the manufacturing method of the present invention can be provided by placing multiple first build-up layers and second build-up layers in the first substrate and the second substrate, respectively. In this way, the number of layers formed on the same substrate can be reduced, the warpage problem caused by the production of multiple layers can be improved, and the production difficulty, production cost, and production yield can be reduced. In addition, the circuit board structure of the present invention can further electrically connect the first substrate and the second substrate through the conductive structure and the connection pad. In this way, the circuit board structure can achieve the requirement of fine contact bonding with electronic components without an additional interconnection board structure, and can be more comprehensively provided through the first substrate on the second substrate and the first substrate The conductive structure in is electrically connected to the second substrate. Therefore, the wiring margin of the circuit board structure can be greatly improved, and the signal integrity of the signal transmission between multiple electronic components can also be improved, so that the circuit board structure has good quality.

In order to make the above-mentioned features and advantages of the present invention more obvious and understandable, the embodiments are specifically described below in conjunction with the accompanying drawings for detailed description as follows.

The following lists some embodiments and details in conjunction with the accompanying drawings, but the provided embodiments are not intended to limit the scope of the present invention. In addition, the drawings are for illustrative purposes only, and are not drawn according to the original dimensions. For ease of understanding, the same elements in the following description will be described with the same symbols.

In addition, the terms "first", "second", etc. used in the text do not mean order or order, and it should be understood that they are used to distinguish elements or operations described in the same technical terms.

Secondly, the terms "include", "include", "have", etc. used in this article are all open terms; that is, they include but are not limited to.

Furthermore, the terms "contact", "joint", "joint", etc. used in this article, unless otherwise specified, can represent direct contact or indirect contact through other membrane layers.

FIG. 1 is a schematic cross-sectional view of a circuit carrier structure according to an embodiment of the invention. Please refer to FIG. 1. In this embodiment, the circuit board structure 1 includes a first substrate 100 having a first surface 102 and a second surface 104 opposite to the first surface 102, and a second substrate 200 having a third surface 202 and opposite third The fourth surface 204 of the three surfaces 202, the adhesive layer 170 are located between the first surface 102 of the first substrate 100 and the third surface 202 of the second substrate 200, and the plurality of connection pads 142 are located on the first surface 102. The first substrate 100 includes a plurality of first build-up layers 120 stacked in sequence, and each first build-up layer 120 includes a first dielectric layer 122 and a first circuit layer 124. The first build-up layers 120 are electrically connected to each other. The second substrate 200 includes a plurality of second build-up layers 220 stacked in sequence, and each second build-up layer 220 includes a second dielectric layer 222 and a second circuit layer 224, and each second build-up layer 220 is electrically connected to each other. For example, the second substrate 200 further includes a second base 210, and the second build-up layer 220 is disposed on the second base 210. The connection pads 142 are electrically connected to the first circuit layer 124. The first substrate 100 is electrically connected to the second substrate 200.

In this embodiment, the circuit board structure 1 further includes a solder resist layer 180 covering the first surface 102 and the fourth surface 204, and the solder resist layer 180 exposes a portion of the connection pad 142, the first circuit layer 124 and the second circuit layer 224 . The circuit board structure 1 further includes a plurality of electronic components 500 located on the first surface 102 of the first substrate 100 and a plurality of solder balls SB electrically connected to the second circuit layer 224. The electronic component 500 is electrically connected to the connection pad 142 and the first circuit layer 124. The manufacturing method of the circuit board structure 1 will be described below with an embodiment.

2A to 2D are schematic cross-sectional views of a manufacturing process of a first substrate according to an embodiment of the invention. Please refer to FIGS. 2A to 2D. The manufacturing method of the circuit carrier structure 1 includes the following steps. First, a temporary carrier 110 is provided, and then a first substrate 100 is formed on the temporary carrier 110. In this embodiment, the first substrate 100 has a first surface 102 and a second surface 104 opposite to the first surface 102 (shown in FIG. 1D).

In this embodiment, the method of forming the first substrate 100 includes the following steps. Please refer to FIG. 2A again to form the release layer 130 on the temporary carrier 110. In this embodiment, the temporary carrier 110 may be a glass substrate, a silicon substrate, a ceramic substrate, or a combination thereof, and the invention is not limited thereto. The release layer 130 may be a photo-curable release film or a thermal curable release film, but the invention is not limited thereto. The viscosity of the photocured release film will be reduced by a photo-curing process; the viscosity of the thermally cured release film will be reduced by a thermal-curing process. In other embodiments, the release layer 130 may also be a laser debond release film.

Next, please refer to FIGS. 2B, 2C, and 2D to perform a plating process to form a plurality of first build-up layers 120 to be sequentially stacked on the release layer 130. In this embodiment, the first build-up layer 120 includes a first dielectric layer 122 and a first circuit layer 124. For example, the first circuit layer 124 is embedded in the first dielectric layer 122, but the invention is not limited thereto. In this embodiment, as shown in FIG. 2B, a first build-up layer 120 is first disposed on the release layer 130. Next, please refer to FIGS. 2C and 2D, and then sequentially combine multiple first build-up layers 120 to stack on the first build-up layer 120 described above. As shown in FIG. 2D, the first substrate 100 in this embodiment is exemplified by a stack of three first build-up layers 120, but the invention is not limited thereto. In other embodiments, the number of the first additional layer 120 may be a single layer or multiple layers, which is designed according to user needs.

After the step of forming the first substrate 100, an adhesive layer 170 is then disposed on the first substrate 100. In this embodiment, the adhesive layer 170 is provided as the first dielectric layer 122 in the first build-up layer 120, for example. In other words, the adhesive layer and the dielectric layer are made of the same material, for example, in the subsequent assembly process, the first substrate 100 and the second substrate 200 can be directly combined without the additional step of providing an adhesive material, to simplify Process. In this embodiment, the second surface 104 of the adhesive layer 170 (eg, the first dielectric layer 122 at the outermost layer) is combined to the third surface 202 of the second substrate 200. The material of the adhesive layer 170 includes a dielectric material including one selected from the group consisting of film, flame-resistant glass fiber (FR4), adhesive-coated copper foil, ABF film, adhesive, solder resist material, and photosensitive dielectric material However, the invention is not limited to this.

In this embodiment, the first substrate 100 is, for example, a redistribution layer (redistribution layer, RDL), and the first circuit layer 124 of the first build-up layer 120 of each layer can be applied as a rearrangement circuit, but the present invention does not take this as limit. In this embodiment, the first circuit layer 124 is provided by the process of ultra-fine circuit, and its line width is less than or equal to 10 microns, but the invention is not limited to this. The first build-up layers 120 are electrically connected to each other. In this embodiment, the material of the first circuit layer 124 includes a metal material, which may be, for example, copper or the like. The material of the first dielectric layer 122 includes a dielectric material. The dielectric material is, for example, a film (PrePreg), a photosensitive dielectric material (PID), a photosensitive polymer (such as Benzocyclobutene, Benzocyclobutene), ABF film (Ajinomoto build-up film), back Resin coated cooper foil (RCC), glass fiber resin composite material or a combination thereof, the invention is not limited thereto.

3A to 3E are schematic cross-sectional views of a manufacturing process of a second substrate according to an embodiment of the invention. Next, please refer to FIGS. 3A to 3E to provide a second substrate 200. The second substrate 200 has a third surface 202 and a fourth surface 204 opposite to the third surface 202 (shown in FIG. 3E). The second substrate 200 of this embodiment is described by taking a high-density interconnect (HDI) as an example, but the invention is not limited thereto. In other embodiments, the second substrate 200 may also be a coreless substrate, a printed circuit board (PCB), or any-layer printed circuit board.

In this embodiment, the method of providing the second substrate 200 includes the following steps. Please refer to FIG. 3A again. First, the second substrate 210 is provided. The second substrate 210 includes a core substrate or a coreless substrate. In this embodiment, the second base 210 may be an insulating substrate, a glass substrate, or a combination thereof, and the invention is not limited thereto. In other embodiments, the second substrate may also be a film (PrePreg) or other suitable dielectric materials.

In this embodiment, a photoresist pattern (not labeled) may be selectively provided on the second substrate 210 to form a plurality of openings (not labeled) through the second substrate 210 in the second substrate 210, but this The invention is not limited to this. In other embodiments, the opening may also be formed by mechanical drilling, laser drilling, or other suitable methods.

Next, a plating process is performed to form a plurality of second build-up layers 220 that are sequentially stacked on two opposite surfaces of the second substrate 210. In this embodiment, the second build-up layer 220 includes a second dielectric layer 222 and a second circuit layer 224. For example, the second circuit layer 224 is embedded in the second dielectric layer 222, but the invention is not limited thereto. In this embodiment, as shown in FIG. 3C, a second build-up layer 220 is first disposed on the second substrate 210. Next, please refer to FIG. 3C and FIG. 3D, and then sequentially combine a plurality of second build-up layers 220 to be stacked on the second build-up layer 220 described above. As shown in FIG. 3E, the second substrate 200 of this embodiment includes three stacks of second build-up layers 220 respectively disposed on two opposite surfaces of the second base 210, but the invention is not limited thereto. In other embodiments, the number of the second additional layer 220 may be a single layer or multiple layers, which is designed according to user needs. In other embodiments, the second build-up layer 220 may also be provided on only one surface of the second substrate 210, and the invention is not limited thereto.

Referring to FIG. 3E, a plurality of conductive pads 240 are formed on the third surface 202 of the second substrate 200. In this embodiment, the conductive pad 240 is electrically connected to the second circuit layer 224. In this embodiment, the third surface 202 is, for example, the uppermost surface of the second substrate 200, and the third surface 202 faces the first substrate 100 (shown in FIG. 4A). In this embodiment, the material of the conductive pad 240 includes a metal material, which may be, for example, copper or the like.

In this embodiment, the second build-up layers 220 are electrically connected to each other. In this embodiment, the material of the second circuit layer 224 includes a metal material, which may be, for example, copper or the like. The material of the second dielectric layer 222 includes a dielectric material. The dielectric material is, for example, a film (PrePreg), a photosensitive dielectric material (PID), a photosensitive polymer (such as Benzocyclobutene, Benzocyclobutene), ABF film (Ajinomoto build-up film), back Resin coated cooper foil (RCC), glass fiber resin composite material or a combination thereof, the invention is not limited thereto.

4A to 4G are schematic cross-sectional views of a manufacturing process of a circuit carrier board according to an embodiment of the invention. Referring to FIG. 4A, after the steps of forming the first substrate 100 and providing the second substrate 200, the second surface 104 of the first substrate 100 to the third surface 202 of the second substrate 200 are combined. Before the above-mentioned combined steps, in this embodiment, the adhesive layer 170 is first disposed on the first substrate 100 as the first dielectric layer 122, but the invention is not limited thereto. In some embodiments, an adhesive layer 170 may be provided on one of the first substrate 100 and the second substrate 200. For example, the adhesive layer can also be used as the outermost second dielectric layer 222 to be disposed on the second substrate 200, but the invention is not limited thereto.

4A and 4B, after combining the second surface 104 of the first substrate 100 to the third surface 202 of the second substrate 200, then, the temporary carrier 110 and the temporary carrier 110 formed on the temporary carrier 110 are removed From the layer 130. In this embodiment, the first circuit layer 124 closest to the first surface 102 can be regarded as a bump structure, but the invention is not limited thereto. In other embodiments, the first circuit layer 124 may also be an under bump metallurgy (UBM) layer. In this embodiment, the line width of the second circuit layer 224 is greater than the line width of the first circuit layer 124, and the line width of the second circuit layer is 10 microns to hundreds of microns, but the invention is not limited thereto.

It is worth noting that the present invention can form the first substrate 100 and the second substrate 200 separately, and then combine the first substrate 100 to the second substrate 200. In this way, multiple build-up layers can be formed in different substrates and then combined into one. Furthermore, the number of layers formed on the same substrate can be reduced, the warpage problem caused by the production of multiple layers can be improved, and the production difficulty, production cost and production yield can be reduced.

Please refer to FIG. 4C. In this embodiment, the manufacturing method of the circuit board structure 1 further includes the following steps. After the temporary carrier 110 is removed, a plurality of through holes 150 are formed through the first substrate 100 and expose the conductive pads 240. For example, the through hole 150 is formed in the plurality of first build-up layers 120 and penetrates the aforementioned stack of the plurality of first build-up layers 120. In this embodiment, the forming method of the through hole 150 may be mechanical drilling, laser drilling or other suitable methods, and the invention is not limited thereto. The cross section of the through hole 150 is, for example, tapered, but the invention is not limited thereto.

Next, referring to FIG. 4D, a seed layer 140' (seed layer) is formed on the first surface 102 of the first substrate 100, and a through hole 150 is filled to contact the conductive pad 240. For example, the seed layer 140' conformally covers the surfaces of the first surface 102 and the through holes 150. In this embodiment, the material of the seed layer 140' includes a metallic material, which may be copper or titanium/copper. The method for forming the seed layer 140' includes electroless plating, sputtering, or a combination thereof, and the invention is not limited thereto.

Then, referring to FIG. 4E, a photoresist pattern 160 covering a portion of the seed layer 140 is formed to expose a portion of the seed layer 140'. For example, the photoresist pattern 160 exposes a part of the seed layer 140' filled in the through hole 150, and exposes a part of the seed layer 140' covering the first circuit layer 124. In this embodiment, the photoresist pattern 160 can be used to define the position of the conductive structure 140 (shown in FIG. 4F) to be formed later. The material of the photoresist pattern 160 includes a photosensitive dielectric material, polyimide, or polybenzoxazole (PBO), silicone, epoxy, benzocyclobutene (BCB ) Or other suitable materials, but the invention is not limited thereto.

Next, referring to FIGS. 4E and 4F, a plating process is performed to form a plurality of conductive structures 140 from a part of the exposed seed layer 140'. For example, the conductive structure 140 may be formed in the through hole 150 through electroplating or electroless plating. In other words, the conductive structure 140 is filled into the through hole 150 and electrically connected to the conductive pad 240. Next, the photoresist pattern 160 and the seed layer 140' covered by the photoresist pattern 160 are removed.

In this embodiment, before removing the photoresist pattern 160, it further includes forming a plurality of connection pads 142 on the first surface 102, and the connection pads 142 are electrically connected to the first circuit layer 124. In this embodiment, the connection pad 142 and the conductive structure 140 are completed at the same time, but the invention is not limited thereto. For example, while forming a plurality of conductive structures 140, the partially exposed seed layer 140' may also simultaneously form connection pads 142 on the first circuit layer 124, and the connection pads 142 are electrically connected to the conductive structures 140. In this way, the conductive structure 140 and the connection pad 142 can be formed in one plating process at the same time to be regarded as an integrated structure. In this embodiment, the conductive structure 140 is electrically connected to the conductive pad 240 and the first circuit layer 124. Since the first circuit layer 124 can be electrically connected to the conductive pad 240 and the second circuit layer 224 through the connection pad 142 and the conductive structure 140, the first substrate 100 is electrically connected to the second substrate 200.

In this embodiment, the top surface 141 of the conductive structure 140 and the top surface 123 of the first circuit layer 124 are different from each other. For example, the top surface 141 of the conductive structure 140 is close to the first surface 102, the bottom surface 143 of the conductive structure 140 is close to the fourth surface 204, and the diameter of the top surface 141 of the conductive structure 140 is larger than the diameter of the bottom surface 143. The top surface 123 of the first circuit layer 124 is close to the fourth surface 204, the bottom surface 121 of the first circuit layer 124 is close to the first surface 102, and the diameter of the top surface 123 of the first circuit layer 124 is larger than the diameter of the bottom surface 121. The cross-section of the conductive structure 140 is tapered, but the invention is not limited thereto.

It is worth noting that in the present invention, after the first substrate 100 is assembled to the second substrate 200, a through hole 150 is formed in the first substrate 100 to provide the conductive structure 140 and the connection pad 142. Under the above configuration, the present invention can first fabricate the first circuit layer 124 of the ultra-fine circuit, and then fabricate the conductive structure 140 and the connection pad 142 of general line width. In this way, the present invention can produce a first circuit layer 124, a conductive structure 140 and a connection pad 142 with different line widths on the first substrate 100 in a simple manufacturing method. For example, the line width of the first circuit layer 124 is smaller than the line width of the connection pad 142. Since the first substrate 100 can have both the ultra-fine line width of the first circuit layer 124 and the general line width of the connection pad 142, no additional interconnection board structure can be achieved to achieve fine routing of fine contacts on the wafer Wire requirements (such as UBM), and the general wiring requirements for conducting the first substrate 100 and the second substrate 200, thereby improving the margin of the circuit layout, so that the circuit board structure 1 has good quality.

Next, please continue to refer to FIG. 4G to form a solder mask 180 to cover the first surface 102 and the fourth surface 204. In this embodiment, the solder resist layer 180 exposes a portion of the connection pad 142, the first circuit layer 124, and the second circuit layer 224. The material of the solder mask 180 includes green paint, photosensitive dielectric material, ABF film, and polymer resin material, and the invention is not limited thereto.

Next, in this embodiment, the surface treatment process is selectively performed. Surface treatment procedures include electroless nickel/electroless palladium/immersion gold (ENEPIG), electroless nickel autocatalytic gold (ENAG), immersion tin (IT), Micro-ball and Micro-ball, and 305 tin-silver-copper alloy solder paste (SAC 305). At this point, the circuit board 10 of the present invention is completed.

Then, referring to FIGS. 1 and 4G, a plurality of electronic components 500 are disposed on the first surface 102 of the first substrate 100. The electronic device 500 is electrically connected to the connection pad 142 and the first circuit layer 124. Finally, multiple solder balls SB are provided to electrically connect the second circuit layer 224. So far, the production of the circuit board structure 1 has been completed. In this embodiment, the electronic device 500 is a chip, for example, and has fine line width contacts and general line width contacts (not labeled), which are electrically connected to the first circuit layer 124 and the connection pad 142, respectively. With the above arrangement, the circuit carrier 10 of the present invention can achieve fine contact bonding on the wafer without additional interconnection structure. The plurality of electronic components 500 can be electrically connected to each other through the first substrate 100, and can be electrically connected to the second substrate 200 through the conductive structure 140, thereby improving the wiring margin of the circuit board structure 1 and further improving the plurality of electronic components 500 The integrity of the signal transmitted between the signals.

In short, the circuit board structure 1 of the present invention can be provided in the first substrate 100 and the second substrate 200 by multi-layering the first build-up layer 120 and the second build-up layer 220, respectively. In this way, the number of layers formed on the same substrate can be reduced, the warpage problem caused by the production of multiple layers can be improved, and the production difficulty, production cost, and production yield can be reduced. In addition, the circuit board structure 1 of the present invention may further include a conductive structure 140 and a connection pad 142 on the first substrate 100 after the first substrate 100 is combined with the second substrate 200 to electrically connect the first substrate 100 and the second substrate 200 Second substrate 200. In this way, the circuit board structure 1 can be electrically connected to the electronic component 500 (such as a chip) through the ultra-fine first circuit layer 124 and the connection pad 142 of the first substrate 100 without an additional interconnect structure. In this way, in addition to achieving the need for fine contact bonding on the electronic component 500, the circuit board structure 1 can also be provided through the first substrate 100 provided on the second substrate 200 and the conductive provided in the first substrate 100 The structure 140 is electrically connected to the second substrate 200. Therefore, the wiring margin of the circuit board structure 1 can be greatly improved, and the signal integrity of the signal transmission between the multiple electronic components 500 can be improved, so that the circuit board structure 1 has good quality.

It must be noted here that the following embodiments follow the element numbers and partial contents of the foregoing embodiments, wherein the same reference numerals are used to indicate the same or similar elements. For the description of the parts that omit the same technical contents, refer to the foregoing embodiments. Details are not repeated in the following embodiments.

5A to 5D are schematic cross-sectional views of a manufacturing process of a circuit carrier board according to another embodiment of the invention. Please refer to FIGS. 4G and 5D first. The circuit board 10A of this embodiment is similar to the circuit board 10 of FIG. 4G. The main difference is that the first substrate 100A of the circuit board 10A further includes a plurality of conductive posts 300, The second substrate 200A further includes a plurality of conductive blind holes 260. The conductive pillar 300 is filled into the conductive blind hole 260 to form a conductive structure 320, and the conductive structure 320 is electrically connected to the first circuit layer 124 and the second circuit layer 224. The manufacturing method of the circuit board 10A will be described below with an embodiment.

Referring to FIG. 5A, a plurality of conductive pillars 300 are formed on the second surface 104, and are electrically connected to the first circuit layer 124. The method of forming the conductive pillar 300 is to form the conductive pillar 300 on the first circuit layer 124 through a plating process, for example. The materials of the conductive pillar 300 and the first circuit layer 124 include metal materials, which may be, for example, copper or similar materials. In this embodiment, the plurality of conductive pillars 300 are separated from each other and have a cylindrical cross section. In this embodiment, when the first build-up layer 120 closest to the temporary carrier 110 is formed, the first circuit layer 124 and the connection pad 142A may be formed at the same time. For example, the first circuit layer 124 and the connection pad 142A may be actually formed integrally, but the invention is not limited thereto. In other embodiments, the connection pad 142A may also be formed after removing the temporary carrier 110.

Next, referring to FIG. 5B, a plurality of conductive blind holes 260 are formed on the third surface 202 and electrically connected to the second circuit layer 224. The material of the conductive blind hole 260 includes a metal material, which may be copper or titanium/copper. The forming method of the conductive blind hole 260 includes electroless plating, sputtering, or a combination thereof, and the invention is not limited thereto.

Next, please refer to FIGS. 5B and 5C to combine the first substrate 100A to the second substrate 200A. Then, the temporary carrier 110 and the release layer 130 formed on the temporary carrier 110 are removed. Then, referring to FIG. 5D, a solder resist layer 180 is formed to cover the first surface 102 and the fourth surface 204, and expose the connection pad 142A, the first circuit layer 124, and the second circuit layer 224. In this way, in the subsequent process of disposing electronic components and solder balls (shown in FIG. 1 ), the electronic components can be directly electrically connected to the first circuit layer 124 and the solder balls are electrically connected to the second circuit layer 224 to reduce manufacturing difficulty , Production costs, and improve production yield.

It is worth noting that the step of combining the first substrate 100A to the second substrate 200A includes combining the conductive pillar 300 to the conductive blind hole 260 with a certain temperature and pressure, so that the conductive pillar 300 is electrically connected and filled into the conductive blind The hole 260 forms a conductive structure 320. In this embodiment, the temperature and pressure of the combination step can be adjusted according to material or process requirements. In this embodiment, the materials of the conductive pillar 300 and the conductive blind hole 260 are the same. For example, the material of the conductive pillar 300 and the material of the conductive blind hole 260 are both metallic copper. Therefore, in this embodiment, the first substrate 100A and the second substrate 200A can be bonded together by copper-to-copper bonding to form the circuit carrier 10A.

In this embodiment, the cross-section of the conductive structure 320 is tapered or cylindrical, but the invention is not limited thereto. For example, the diameter of the top surface (not labeled) of the conductive structure 320 near the first surface 102 may be greater than or equal to the diameter of the bottom surface (not labeled) near the fourth surface 204. In this way, the conductive structure 320 may be formed into a tapered shape with a diameter of the bottom surface smaller than that of the top surface according to design requirements, or a columnar shape having the same diameter as the bottom surface and the top surface. In this way, the conductive structure 320 can be electrically connected to the second circuit layer 224 and the first circuit layer, further provide good bonding reliability and quality, reduce manufacturing difficulty, manufacturing cost, and increase production yield. In addition, with the above-mentioned design, the circuit carrier 10A of this embodiment can also obtain the same effect as the above embodiment, which will not be repeated here.

6A to 6H are schematic cross-sectional views of a manufacturing process of a circuit carrier board according to yet another embodiment of the invention. Please refer to FIGS. 4G and 6H first. The circuit carrier board 10B of this embodiment is similar to the circuit carrier board 10 of FIG. 4G. The main difference is that the second substrate 200B of this embodiment does not include the second base. Specifically, the second substrate 200B of this embodiment is described by taking a coreless substrate as an example.

Please refer to FIG. 4A and FIG. 6A. The first substrate 100 of this embodiment is the same as the first substrate 100 of FIG. 4A, which will not be repeated here. The second substrate 200B includes a plurality of second build-up layers 22 stacked in sequence, and disposed on two opposite surfaces of the second base 210A. For example, the fourth surfaces 204 of the two upper and lower second substrates 200B are disposed on opposite surfaces of the second base 210A. The material of the second substrate 210A may include glass, ceramics, polymer materials, flexible dielectric materials or other suitable materials, and the invention is not limited thereto. In other embodiments, the material of the second substrate 210A may also include a film (PrePreg).

Next, as shown in FIG. 6A, the second surfaces 104 of the upper and lower first substrates 100 are combined to the third surfaces 202 of the upper and lower second substrates 200B, respectively. Then, referring to FIG. 6B, the temporary carrier 110 is removed. The detailed steps of joining and removing have been described in the above paragraphs, and will not be repeated here.

Next, referring to FIG. 6C, the second substrate 210A is removed to obtain two coreless second substrates 200B. In this way, it can improve production efficiency, reduce costs and increase production yield.

Next, please refer to FIG. 6D, FIG. 6E, FIG. 6F, FIG. 6G and FIG. 6H, forming a plurality of conductive structures 140 to fill the through holes 150 to electrically connect the connection pad 142, the conductive pad 240, the first circuit layer 120 and the first Second line layer 224. The detailed forming steps have been described in the above paragraphs, and will not be repeated here. In this way, the first substrate 100 of the circuit board 10B can be electrically connected to the second substrate 200B, and the same effect as the above-mentioned embodiment is achieved.

7 is a schematic cross-sectional view of a circuit carrier board according to another embodiment of the invention. Please refer to FIG. 6H and FIG. 7, the circuit carrier 10C of this embodiment is similar to the circuit carrier 10B of FIG. 6H, the main difference is that the first substrate 100A of this embodiment is combined with the second substrate 200C to fill the conductive pillars A conductive blind hole (shown in FIG. 5B) is inserted to form a conductive structure 320, and the conductive structure 320 is electrically connected to the first circuit layer 124 and the second circuit layer 224. The detailed combination steps have been described in the above paragraphs, and will not be repeated here. In this way, the first substrate 100A of the circuit board 10C can be electrically connected to the second substrate 200C, and the same effect as the above-mentioned embodiment is achieved.

8A is a schematic cross-sectional view of a manufacturing process of a circuit carrier board according to yet another embodiment of the invention. 4G and FIG. 8A, the circuit carrier 10D of this embodiment is similar to the circuit carrier 10 of FIG. 4G, the main difference is that the second substrate 400 of this embodiment is a printed circuit board. Specifically, the second substrate 400 includes a second base 410 and a plurality of second build-up layers 420 are sequentially stacked on the second base 410. The second build-up layer 420 includes a second dielectric layer 422 and a second circuit layer 424, and the second build-up layers 420 are electrically connected to each other. The first substrate 100 is disposed on the second substrate 400 and the first substrate 100 is electrically connected to the second substrate 400. The detailed forming steps have been described in the above paragraphs, and will not be repeated here. In this way, the first substrate 100 of the circuit carrier 10D can be electrically connected to the second substrate 400, and the same effect as the above-mentioned embodiment can be obtained. In the present embodiment, the second substrate 400 is described using a printed circuit board as an example, but the invention is not limited thereto. In other embodiments, the second substrate may also be any printed circuit board.

8B is a schematic cross-sectional view of a manufacturing process of a circuit carrier board according to yet another embodiment of the invention. Please refer to FIGS. 8A and 8B. The circuit board 10E of this embodiment is similar to the circuit board 10D of FIG. 8A. The main difference is that the first substrate 100A of this embodiment is combined with the second substrate 400A to fill the conductive pillars. A conductive blind hole (shown in FIG. 5B) is inserted to form a conductive structure 320, and the conductive structure 320 is electrically connected to the first circuit layer 124 and the second circuit layer 424. The detailed combination steps have been described in the above paragraphs, and will not be repeated here. In this way, the first substrate 100A of the circuit board 10E can be electrically connected to the second substrate 400A, and the same effect as the above-mentioned embodiment is achieved. In this embodiment, the second substrate 400A is described by using a printed circuit board as an example, but the invention is not limited thereto. In other embodiments, the second substrate may also be any printed circuit board.

In summary, the circuit board structure and the manufacturing method of the present invention can be implemented by arranging multiple first build-up layers and second build-up layers in the first substrate and the second substrate, respectively. In this way, the number of layers formed on the same substrate can be reduced, the warpage problem caused by the production of multiple layers can be improved, and the production difficulty, production cost, and production yield can be reduced. In addition, the circuit board structure of the present invention can further electrically connect the first substrate and the second substrate through the conductive structure and the connection pad. In this way, the circuit carrier structure can be electrically connected to the electronic component (such as a chip) through the ultra-fine first circuit layer of the first substrate and the connection pad without additional interconnection structure. In this way, in addition to meeting the demand for fine contact bonding on electronic components, the circuit carrier structure can be electrically connected through the first substrate provided on the second substrate and the conductive structure provided in the first substrate Second substrate. Therefore, the wiring margin of the circuit board structure can be greatly improved, and the signal integrity of the signal transmission between multiple electronic components can also be improved, so that the circuit board structure has good quality. In addition, the circuit board structure may further include a conductive structure formed by a conductive pillar and a conductive blind hole formed by copper-to-copper bonding, which can further provide good bonding reliability and quality, reduce manufacturing difficulty, manufacturing cost, and increase production yield. In addition, the manufacturing method of the circuit carrier structure of the present invention can be applied to high-density connection boards, coreless substrates, printed circuit boards, or printed circuit boards of arbitrary layers, and has excellent applicability.

Although the present invention has been disclosed as above with examples, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be subject to the scope defined in the appended patent application.

1‧‧‧ Line carrier structure 10, 10A, 10B, 10C, 10D, 10E‧‧‧ Line carrier 100, 100A‧‧‧ First substrate 102‧‧‧ First surface 104‧‧‧ Second surface 110‧ ‧‧Temporary carrier board 120‧‧‧First build-up layers 121, 143‧‧‧‧Bottom surface 122‧‧‧First dielectric layer 123, 141‧‧‧Top surface 124‧‧‧ First circuit layer 130‧‧‧ Shape layer 140, 320 ‧‧‧ conductive structure 140′‧‧‧ seed layer 142, 142A ‧‧‧ connection pad 150‧‧‧ through hole 160‧‧‧ photoresist pattern 170‧‧‧ adhesion layer 180‧‧‧ solder Layers 200, 200A, 200B, 200C, 400, 400A ‧‧‧ second substrate 202 ‧ ‧ ‧ third surface 204 ‧ ‧ ‧ fourth surface 210, 210A ‧ ‧ ‧ second substrate 220, 420 ‧ ‧ ‧ second increase Layer 222, 422‧‧‧ Second dielectric layer 224, 424‧‧‧ Second circuit layer 240‧‧‧ Conductive pad 260‧‧‧ Conductive blind hole 300‧‧‧Conducting post 500‧‧‧Electronic component SB‧ ‧‧Solder Ball

FIG. 1 is a schematic cross-sectional view of a circuit carrier structure according to an embodiment of the invention. 2A to 2D are schematic cross-sectional views of a manufacturing process of a first substrate according to an embodiment of the invention. 3A to 3E are schematic cross-sectional views of a manufacturing process of a second substrate according to an embodiment of the invention. 4A to 4G are schematic cross-sectional views of a manufacturing process of a circuit carrier board according to an embodiment of the invention. 5A to 5D are schematic cross-sectional views of a manufacturing process of a circuit carrier board according to another embodiment of the invention. 6A to 6H are schematic cross-sectional views of a manufacturing process of a circuit carrier board according to yet another embodiment of the invention. 7 is a schematic cross-sectional view of a circuit carrier board according to another embodiment of the invention. 8A is a schematic cross-sectional view of a manufacturing process of a circuit carrier board according to yet another embodiment of the invention. 8B is a schematic cross-sectional view of a manufacturing process of a circuit carrier board according to yet another embodiment of the invention.

1‧‧‧ Line carrier board structure

100‧‧‧The first substrate

102‧‧‧First surface

104‧‧‧Second surface

120‧‧‧The first layer

122‧‧‧First dielectric layer

124‧‧‧ First circuit layer

140‧‧‧conductive structure

142‧‧‧ connection pad

180‧‧‧Soldering layer

200‧‧‧Second substrate

202‧‧‧The third surface

204‧‧‧Fourth surface

210‧‧‧Second base

220‧‧‧The second layer

222‧‧‧Second dielectric layer

224‧‧‧ Second circuit layer

240‧‧‧Conductive pad

500‧‧‧Electronic components

SB‧‧‧Solder ball

Claims (20)

A method for manufacturing a circuit carrier structure includes: providing a temporary carrier; forming a first substrate on the temporary carrier, the first substrate having a first surface and a second surface opposite to the first surface, The first substrate includes a plurality of first build-up layers, and each of the first build-up layers includes a first dielectric layer and a first circuit layer; a second substrate is provided with a third surface and opposite to the third A fourth surface of the surface, wherein the second substrate includes a plurality of second build-up layers, and each of the second build-up layers includes a second dielectric layer and a second circuit layer, and the line width of the second circuit layer is large Line width of the first circuit layer; providing an adhesive layer on one of the first substrate and the second substrate, and the adhesive layer is located between the first substrate and the second substrate; combining the The second surface of the first substrate to the third surface of the second substrate; and removing the temporary carrier, wherein the first substrate is electrically connected to the second substrate. The method for manufacturing a circuit board structure as described in item 1 of the patent application scope, wherein the step of forming the first substrate includes: forming a release layer on the temporary carrier board; and forming the first build-up layers in sequence Stacked on the release layer, wherein each of the first build-up layers is electrically connected to each other. The method for manufacturing a circuit carrier structure as described in item 2 of the patent application scope, wherein the step of providing the second substrate includes: providing a second substrate; forming the second build-up layers and sequentially stacking on the second substrate And forming a plurality of conductive pads on the third surface, the conductive pads are electrically connected to the second circuit layer, wherein each of the second build-up layers are electrically connected to each other. The method for manufacturing a circuit board structure as described in item 3 of the patent application scope further includes: forming a plurality of through holes penetrating the first substrate and exposing the conductive pads; forming a sub-layer on the first surface, Filling the through holes to contact the conductive pads; forming a photoresist pattern covering part of the seed layer to expose part of the seed layer; forming a plurality of conductive structures from the exposed part of the seed layer, each The conductive structure is electrically connected to the conductive pads and the first circuit layer; and the photoresist pattern and the seed layer covered by the photoresist pattern are removed. The method for manufacturing a circuit carrier structure as described in item 2 of the patent application scope, wherein the step of forming the first substrate further comprises: forming a plurality of conductive pillars on the second surface and electrically connecting the first circuit layer . The method for manufacturing a circuit carrier structure as described in item 5 of the patent application scope, wherein the step of providing the second substrate includes: Providing a second substrate; forming a plurality of second build-up layers sequentially stacked on the second substrate, wherein each of the second build-up layers includes a second dielectric layer and a second circuit layer; and forming a plurality of conductive blinds The holes are on the third surface, and the conductive blind holes are electrically connected to the second circuit layer, wherein each of the second build-up layers is electrically connected to each other. The method for manufacturing a circuit carrier structure as described in item 6 of the patent application scope, wherein the step of combining the first substrate to the second substrate further includes: combining the conductive pillars to the conductive blind holes to make the The conductive pillars are electrically connected and filled into the conductive blind holes to form a plurality of conductive structures, wherein the conductive structures are electrically connected to the second circuit layer and the first circuit layer. The method for manufacturing a circuit board structure as described in item 6 of the patent application scope further includes: forming a plurality of connection pads on the first surface, the connection pads are electrically connected to the first circuit layer, wherein the first The line width of the circuit layer is smaller than the line width of each of the connection pads; a solder mask is formed to cover the first surface and the fourth surface, and the solder mask exposes portions of the connection pads, the first circuit layer, and the first Two circuit layers; and a surface treatment procedure. The method for manufacturing a circuit board structure as described in item 8 of the scope of the patent application further includes: disposing a plurality of electronic components on the first surface of the first substrate, and the electronic components The sub-elements are electrically connected to the connection pads and the first circuit layer; and a plurality of solder balls are provided to electrically connect the second circuit layer. A circuit board structure includes: a first substrate having a first surface and a second surface opposite to the first surface, including: a plurality of first build-up layers are sequentially stacked, and each of the first build-up layers includes a first A dielectric layer and a first circuit layer, each of the first build-up layers is electrically connected to each other; a second substrate has a third surface and a fourth surface opposite to the third surface, including: a plurality of second build-up layers The layers are stacked in sequence, each of the second build-up layers includes a second dielectric layer and a second circuit layer, each of the second build-up layers is electrically connected to each other; an adhesive layer is located between the first substrate and the second substrate The second surface is combined to the third surface; and a plurality of connection pads on the first surface are electrically connected to the first circuit layer, wherein the first substrate is electrically connected to the second substrate, wherein the first The line width of the circuit layer is smaller than the line width of each connection pad, wherein the line width of the first circuit layer is less than or equal to 10 microns, and the line width of the second circuit layer is greater than the line width of the first circuit layer. The circuit board structure of claim 10, wherein the first substrate further includes a plurality of through holes penetrating the first substrate, the second substrate further includes a second base and the second build-up layers are provided On the second substrate, and a plurality of conductive pads on the third surface are electrically connected to the second circuit layer, the through holes expose the Conductive pads, and a plurality of conductive structures are filled into the through holes to electrically connect the connection pads, the conductive pads, the first circuit layer and the second circuit layer. The circuit board structure as described in item 11 of the patent application range, wherein the top surface of each conductive structure is close to the first surface, the bottom surface of each conductive structure is close to the second surface, and the top surface of each conductive structure The diameter is greater than the diameter of the bottom surface, wherein the top surface of the first circuit layer is close to the second surface, the bottom surface of the first circuit layer is close to the first surface, and the diameter of the top surface of the first circuit layer is greater than the diameter of the bottom surface. The circuit board structure as described in item 12 of the patent application scope, wherein each of the conductive structures has a tapered cross section. The circuit board structure of claim 10, wherein the first substrate further includes a plurality of conductive posts on the second surface to electrically connect the first circuit layer, and the second substrate further includes a second The substrate and the second build-up layers are disposed on the second substrate, and a plurality of conductive blind holes on the third surface are electrically connected to the second circuit layer, and the conductive pillars are filled into the conductive blind holes to form A plurality of conductive structures, and the conductive structures are electrically connected to the first circuit layer and the second circuit layer. The circuit board structure as described in item 14 of the patent application scope, wherein the cross section of each conductive structure is tapered or cylindrical. The circuit board structure as described in item 10 of the patent application scope further includes: a solder mask covering the first surface and the fourth surface, and the solder mask exposes portions of the connection pads and the first circuit layer And the second circuit layer. The circuit board structure as described in item 10 of the patent application scope further includes: A plurality of electronic components are located on the first surface of the first substrate, and the electronic components are electrically connected to the connection pads and the first circuit layer; and a plurality of solder balls are electrically connected to the second circuit layer. The circuit board structure as described in any one of items 11 or 14 of the patent application scope, wherein the second substrate includes a core substrate or a coreless substrate. The circuit board structure of claim 10, wherein the first circuit layer is embedded in the first dielectric layer, and the second circuit layer is embedded in the second dielectric layer. The circuit board structure as described in item 10 of the patent application scope, wherein the materials of the first dielectric layer, the second dielectric layer and the adhesive layer include a film selected from the group consisting of film, flame-resistant glass fiber, adhesive-coated copper foil, and ABF One of film, adhesive, solder resist material or photosensitive dielectric material.

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