TWI701981B - Circuit carrier board and manufacturing method thereof - Google Patents

Abstract

A circuit carrier board includes a first substrate and a second substrate bonding to the first substrate. The first substrate includes a first circuit layer and a plurality of conductive structure electrically connecting to the first circuit layer. The conductive structures are suitable for electrically connecting to a plurality of electronic elements. The second substrate contacts the first circuit layer. The second substrate includes a plurality of dielectric layers sequentially stacking onto the first substrate, and a plurality of second circuit layers disposed in the dielectric layers. The bottom most layer of the second circuit layers is exposed outside of the dielectric layers, and the top most layer of the dielectric layers is electrically connected to the first circuit layer. The conductive structure includes a pad and a via. The pad electrically connects to the first circuit layer through the via. A line width of the first circuit layer is smaller than a line width of the second circuit layer. A manufacturing method of the circuit carrier board is also provided.

Description

Circuit carrier board and manufacturing method thereof

The invention relates to a circuit carrier board and a manufacturing method thereof, and more particularly to a circuit carrier board with circuit layers with different line widths.

Generally speaking, the multi-layer circuit structure of the circuit board is mostly made by build up or laminated method, so it has the characteristics of high circuit density and reduced circuit spacing. For example, the manufacturing method of a multilayer circuit structure is to form a build-up structure of copper foil and film (PrePreg), and stack the build-up structure on the core layer to form a multilayer circuit. Structure to increase the internal wiring space of the multilayer circuit structure, where the conductive material on the build-up structure can form conductive lines according to the required circuit layout, and the blind holes or through holes of the build-up structure can be additionally filled with conductive materials to conduct each layer . In this way, the multi-layer circuit structure can be produced by adjusting the number of circuit structures according to requirements and using the above-mentioned method.

With the advancement of science and technology, all kinds of electronic products are developing towards high-speed, high-efficiency, and thin and short trends. Under this trend, how to design circuit boards so that multiple high-density circuit chips can communicate and improve signal transmission efficiency is an urgent issue in this field.

The invention provides a circuit carrier board and a manufacturing method thereof, which is suitable for interconnecting a plurality of high-density circuit electronic components, reduces signal delay and improves the performance of the circuit carrier board.

The manufacturing method of the circuit carrier board of the present invention includes the following steps. Provide the first temporary carrier board. A first substrate is formed on the first temporary carrier. The first substrate includes a first circuit layer and a plurality of conductive structures, and the conductive structure is suitable for electrically connecting to a plurality of electronic components. The bonding step is performed to bond the first substrate to the second temporary carrier. The conductive structure is located between the first circuit layer and the second temporary carrier board. Remove the first temporary carrier board. A second substrate is formed on the first substrate to bond the second substrate to the first substrate. The second substrate includes a plurality of dielectric layers and a plurality of second circuit layers are arranged in the dielectric layer. The bottom layer of the second circuit layer is exposed to the dielectric layer, and the top layer of the second circuit layer is electrically connected to the first circuit layer. And, remove the second temporary carrier board.

In an embodiment of the present invention, the above-mentioned step of forming the first substrate includes forming a release layer on the first temporary carrier. A first circuit layer is formed on the release layer. An insulating layer is formed on the release layer and covers the first circuit layer. A conductive structure is formed on the insulating layer, and the conductive structure is electrically connected to the first circuit layer. And, an insulating adhesive material is formed on the insulating layer, and the conductive structure is located between the insulating adhesive material and the insulating layer.

In an embodiment of the present invention, the above-mentioned step of forming the first substrate further includes performing a thinning process to remove part of the insulating adhesive material to form an insulating adhesive layer and exposing the conductive structure.

In an embodiment of the present invention, the above-mentioned step of forming the second substrate includes forming a dielectric layer sequentially stacked on the first substrate. And, forming a second circuit layer in the dielectric layer, and the second circuit layer is electrically connected to each other.

In an embodiment of the present invention, the above-mentioned step of forming the first substrate includes forming a release layer on the first temporary carrier. A first circuit layer is formed on the release layer. And, forming an insulating adhesive material on the first circuit layer.

In an embodiment of the present invention, the step of forming the first substrate described above further includes, after the step of forming the second substrate on the first substrate, forming a plurality of contact windows in the insulating adhesive material to form an insulating adhesive layer . And, a conductive structure is formed in the insulating adhesive layer, and the conductive structure is electrically connected to the first circuit layer through the contact window.

In an embodiment of the present invention, the above-mentioned manufacturing method of the circuit carrier further includes forming a plurality of solder resist layers on the first substrate and the second substrate, respectively, to partially cover the conductive structure and the bottom layer of the second circuit layer. And, a plurality of solder balls are arranged to be electrically connected to the bottommost layer of the second circuit layer.

The circuit carrier of the present invention includes a first substrate and a second substrate joined to the first substrate. The first substrate includes a first circuit layer and a plurality of conductive structures are electrically connected to the first circuit layer. The conductive structure is suitable for electrically connecting to a plurality of electronic components. The second substrate contacts the first circuit layer, and includes a plurality of dielectric layers sequentially stacked on the first substrate and a plurality of second circuit layers disposed in the dielectric layer. The bottommost layer of the second circuit layers is exposed to the dielectric layers, and the topmost layer of the second circuit layers is electrically connected to the first circuit layer. The conductive structure includes pads and conductive vias. The pad is electrically connected to the first circuit layer through the conductive via. The orthographic projection of each conductive via contacting the bottom surface of the first circuit layer on the second substrate is within the orthographic projection of the top surface of each pad on the second substrate. The line width of the first circuit layer is smaller than the line width of the second circuit layer.

In an embodiment of the present invention, the aforementioned first substrate further includes an insulating layer and an insulating adhesive layer. The first circuit layer is embedded on a surface of the insulating layer. The insulating adhesive layer is arranged on the opposite surface of the insulating layer. The conductive structure is arranged in the insulating layer, a part of each pad is arranged on the other surface, and the insulating adhesive layer surrounds each pad.

In an embodiment of the present invention, the aforementioned first substrate further includes an insulating adhesive layer. The first circuit layer is embedded on a surface of the insulating adhesive layer, and the insulating adhesive layer has a plurality of contact windows. The conductive structure is arranged in the insulating adhesive layer, and the pad part is arranged on the other surface of the opposite surface. The conductive via is filled in the contact window to contact the first circuit layer.

In an embodiment of the present invention, the above-mentioned circuit carrier further includes a plurality of solder masks respectively disposed on the first substrate and the second substrate, and a plurality of solder balls are disposed on the second substrate. The solder mask partially covers the conductive structure and the bottommost layer of these second circuit layers. The solder balls are electrically connected to the bottom layer of the second circuit layer.

In an embodiment of the present invention, the aforementioned circuit carrier further includes a plurality of surface-treated metal pads. The metal pads are respectively contacted and arranged on the pads and on the bottom layer of the second circuit layers.

Based on the foregoing, the circuit carrier and the manufacturing method thereof according to an embodiment of the present invention can directly form a second substrate with a general line width and bond the entire surface to the first substrate of the first circuit layer with ultra-fine circuits. Therefore, it is possible to directly integrate the first circuit layer and the second circuit layer manufactured with different finenesses on the circuit carrier board, thereby simplifying the manufacturing process, reducing the cost and improving the wiring margin. In addition, a plurality of electronic components with high-density circuits can be directly electrically connected to the conductive structure of the first substrate, so these electronic components can be interconnected through the first circuit layer. In this way, the signal delay between the interconnected electronic components can be reduced and the performance of the circuit carrier board can be improved. In addition, the multiple build-up layers of the second substrate can further support the first substrate, thereby improving the overall rigidity of the circuit carrier and the reliability of the structure.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

Hereinafter, some embodiments are listed and described in detail with the accompanying drawings, but the provided embodiments are not intended to limit the scope of the present invention. In addition, the drawings are for illustrative purposes only and are not drawn according to the original size. To facilitate understanding, the same elements in the following description will be described with the same symbols.

In addition, the terms "first", "second"... etc. used in the text do not mean order or sequence, and it should be understood that they are used to distinguish elements or operations described in the same technical terms.

Secondly, the terms "include", "include", "have" and so on used in this article are all open terms; that is, include but are not limited to.

Furthermore, the terms "contact", "connecting", "joining", etc. used in this text, unless otherwise specified, can mean direct contact or indirect contact through other layers.

1A to 1K are schematic cross-sectional views of a manufacturing process of a circuit carrier board according to an embodiment of the invention. Please refer to FIG. 1K first. In this embodiment, the circuit carrier 1 includes a first substrate 100 and a second substrate 200 bonded to the first substrate 100. The first substrate 100 includes a first circuit layer 110 and a plurality of conductive structures 130 electrically connected to the first circuit layer 110. These conductive structures 130 are suitable for being electrically connected to a plurality of electronic components 300 disposed on the first substrate 100. The second substrate 200 contacts the first circuit layer 110, and includes a plurality of dielectric layers 220 sequentially stacked on the first substrate 100, and a plurality of second circuit layers 210 are disposed in the dielectric layers 220. The bottommost layer 212 of the second circuit layers 210 is exposed to the dielectric layer 220, and the topmost layer 211 of the second circuit layers 210 is electrically connected to the first circuit layer 110. The circuit carrier board 1 further includes a plurality of solder mask layers SR respectively disposed on the first substrate 100 and the second substrate 200, and a plurality of solder balls SB disposed on the second substrate 200 to be electrically connected to these second circuit layers 210 the bottom layer 212. Hereinafter, the manufacturing method of the circuit carrier 1 will be briefly described according to the embodiments.

Please refer to FIG. 1A, FIG. 1B and FIG. 1C. The manufacturing method of the circuit carrier board 1 (shown in FIG. 1K) includes the following steps. First, as shown in FIG. 1A, a first temporary carrier 10 is provided.

Next, a first substrate 100' is formed on the first temporary carrier 10 (shown in FIG. 1C). In this embodiment, the first substrate 100' may have a single-layer or multi-layer stacked structure. As shown in FIG. 1A, the step of forming the first substrate 100' includes forming a release layer 12 on the first temporary carrier 10, and then forming a first circuit layer 110 on the release layer 12. The release layer 12 may be a photo-curable release film or a thermal curable release film, but the invention is not limited thereto. The viscosity of the photo-curable release film will be reduced through a photo-curing process; and the viscosity of the thermally cured release film will be reduced through a thermal-curing process. In other embodiments, the release layer 12 may also be a laser debond release film.

In this embodiment, the first circuit layer 110 is arranged in an ultra-fine line (ultra-fine line) process. For example, the line width D1 (marked in FIG. 2B) of the first circuit layer 110 may be less than or equal to 5 microns. In some embodiments, the line width D1 of the first circuit layer 110 can be selectively between 1 μm and 5 μm, but the invention is not limited thereto. Under the above configuration, the first circuit layer 110 can meet the requirements of ultra-fine circuits. Based on the consideration of conductivity, the first circuit layer 110 generally uses metal materials, such as copper, aluminum, silver, gold, or other suitable materials, but the present invention is not limited thereto. According to other embodiments, the first circuit layer 110 may also use other conductive materials, such as alloys, oxides of metal materials, nitrides of metal materials, oxynitrides of metal materials, or stacked layers of metal materials and other conductive materials. . In this embodiment, the method of forming the first circuit layer 110 includes electroplating or chemical plating or electroless plating, but the invention is not limited thereto.

Then, referring to FIG. 1B, a plating process is performed to form an insulating layer 120 on the release layer 12 and cover the first circuit layer 110. In other words, the insulating layer 120 and the first circuit layer 110 can serve as one of the build-up layers in the multilayer structure of the first substrate 100'. In some embodiments, multiple buildup layers composed of the first circuit layer 110 and the insulating layer 120 may be sequentially stacked to form two, three or more buildup layers. The multi-layer first circuit layer 110 in the above-mentioned multi-layer build-up layer can be electrically connected to each other through a plurality of through holes penetrating the insulating layer 120. 1B of the present embodiment, for clarity, only one layer of the first circuit layer 110 and one layer of insulating layer 120 is described. In fact, the number of the first circuit layer 110 and the insulating layer 110 is not limited to the number shown in FIG. 1B .

Next, a plurality of contact windows 122 are formed on the insulating layer 120 to expose part of the first circuit layer 110. Then, a conductive structure 130 is formed on the insulating layer 120, and the conductive structure 130 can be filled in the contact window 122 to be electrically connected to the first circuit layer 110. In this embodiment, the material of the insulating layer 120 includes a dielectric material that does not contain glass fiber cloth, for example, selected from ABF film (Ajinomoto build-up film, ABF), glue, and photosensitive dielectric material (photoimageable dielectric, PID) or photosensitive polymer (such as benzocyclobutene, Benzocyclobutene) or a combination thereof, but the present invention is not limited thereto. In some embodiments, the material of the insulating layer 120 may also include an adhesive dielectric material, such as epoxy resin, but it is not limited thereto. In this embodiment, the method for forming the plurality of contact windows 122 includes photolithography, mechanical drilling, laser drilling or other suitable methods, and the present invention is not limited thereto.

In detail, a part of the conductive structure 130 is formed on the insulating layer 120, and the other part is formed in the insulating layer 120. As shown in FIG. 1B, the conductive structure 130 may include a pad 132 and a conductive via 134 electrically connected to the pad 132. The pad 132 is disposed on the insulating layer 120, and the conductive via 134 is filled in the contact window 122. In this way, the pad 132 located on the insulating layer 120 can be electrically connected to the portion of the first circuit layer 110 exposed by the contact window 122 through the conductive via 134 located in the insulating layer 120. In this embodiment, part of the pads 132 may not contact the conductive vias 134 and serve as a structure for interconnecting other conductive structures 130 on the same plane. The above-mentioned part of the pad 132 and the pad 132 connected to the conductive via 134 can be formed through the same patterning process, and therefore can be regarded as a part of the conductive structure 130, but the invention is not limited thereto. In other words, in some embodiments, the structure of horizontally interconnecting the plurality of conductive vias 134 can also be completed in additional steps as required.

In this embodiment, based on the consideration of conductivity, the conductive structure 130 (including the pad 132 and the conductive via 134) generally includes a metal or metal alloy, such as molybdenum, aluminum, titanium, copper, gold, silver or other metals. The present invention is not limited to conductive materials or stacks of the above two or more materials or alloys of the above two or more materials. In this embodiment, the method for forming the conductive structure 130 includes electroplating or electroless plating, but the invention is not limited thereto. In some embodiments, the conductive structure 130 may also be formed by means of Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), or Atomic Layer Deposition (ALD).

Then, referring to FIG. 1C, an insulating adhesive material 140' is formed on the insulating layer 120 to cover the conductive structure 130 and the insulating layer 120. In other words, the conductive structure 130 will be located between the insulating adhesive material 140' and the insulating layer 120. So far, the fabrication of the first substrate 100' with the pads 132 not yet exposed is substantially completed. In other words, the above-mentioned first substrate 100' is a build-up layer including a first circuit layer 110 and an insulating layer 120, a plurality of conductive structures 130 electrically connected to the first circuit layer 110, and an insulating adhesive covering the conductive structure 130 Material 140' ultra-fine circuit board. From another perspective, the first substrate 100' is, for example, a redistribution layer (RDL) applying ultra-fine circuit technology, but the present invention is not limited to this. In this embodiment, the material of the insulating adhesive material 140' includes a material selected from a thermosetting polymer (thermosetting polymer) or a photopolymer (photopolymer). Thermosetting polymers include, for example, polyester resin, polyurethanes, melamine resin, ABF film (Ajinomoto build-up film), epoxy resin, and polyamide resin. Imine (polyimides), silicone resin (silicone) or vinyl ester (vinyl ester). The photocurable polymer includes, for example, acrylate or epoxy resin. However, the present invention is not limited to this.

Next, referring to FIG. 1D, a bonding step is performed to bond the first substrate 100' to the second temporary carrier 20. In this embodiment, the two opposite surfaces of the second temporary carrier board 20 are provided with metal layers 21, and the release layer 22 is respectively provided on the two metal layers 21. As shown in FIG. 1D, the insulating adhesive material 140' of the first substrate 100' is bonded to the release layer 22 on the second temporary carrier 20. In addition, the conductive structure 130 is located between the first circuit layer 110 and the second temporary carrier board 20. From another perspective, the first circuit layer 110 is located on the surface 101 of the insulating layer 120 away from the second temporary carrier board 20. In fact, the first circuit layer 110 is embedded in the surface 101 of the insulating layer 120. In addition, the pad 132 may be disposed on the other surface 103 of the insulating layer 120 opposite to the surface 101, and the insulating adhesive material 140' is disposed on the other surface 103 to cover the pad 132, but the invention is not limited thereto.

In this embodiment, the second temporary carrier 20 may be a glass substrate, a silicon substrate (Si substrate), a ceramic substrate (ceramic substrate) or a combination thereof, but the invention is not limited thereto. The material of the metal layer 21 is, for example, a metal or an alloy, including aluminum, copper, silver, gold, or an alloy of the foregoing metals, or other suitable materials, and the present invention is not limited thereto. From another perspective, the second temporary carrier 20 is, for example, a double-sided copper foil substrate (Copper Clad Laminate, CCL), but not limited to this. In this embodiment, the release layer 22 may be a photo-curable release film or a thermal curable release film, but the invention is not limited thereto. In other embodiments, the release layer 22 may also be a laser debond release film.

In this embodiment, as shown in FIG. 1D, the upper and lower first substrates 100' can be simultaneously bonded to the second temporary carrier 20, so that in the subsequent steps, the upper and lower first substrates 100' A second substrate 200 (shown in FIG. 1G) is formed thereon. In this way, the manufacturing process can be simplified and the manufacturing cost can be reduced. Hereinafter, the following process steps will be mainly described with the first substrate 100' under the second temporary carrier 20. Those with ordinary knowledge in the art should understand that the subsequent process steps of the first substrate 100' above the second temporary carrier 20 are the same as the process steps of the first substrate 100' below, so it will not be repeated here. .

Then, referring to FIGS. 1D and 1E, the first temporary carrier 10 and the release layer 12 formed on the first temporary carrier 10 are removed to expose the first circuit layer 110. The method of removing the first temporary carrier 10 includes, for example, illuminating, heating, or laser dissociation to reduce the viscosity of the release layer 12, thereby separating the first temporary carrier 10 from the first substrate 100'.

Next, referring to FIGS. 1F and 1G, the second substrate 200 is formed on the first substrate 100. In this embodiment, the second substrate 200 includes a plurality of stacked layers formed by sequentially staggering a plurality of dielectric layers 220 and a plurality of second circuit layers 210 on the first substrate 100'. For example, as shown in FIGS. 1F and 1G, the step of forming the second substrate 200 includes sequentially stacking multiple dielectric layers 220 on the first substrate 100', and one of these dielectric layers 220 will be It is arranged on the surface 101 of the insulating layer 120. In other words, the second substrate 200 of this embodiment is disposed on the insulating layer 120. Then, multiple second circuit layers 210 are formed in the dielectric layers 220, and the second circuit layers 210 at different levels are electrically connected to each other. From another perspective, each layer of the second circuit layer 210 and each layer of the dielectric layer 220 can define a build-up layer of the second substrate 200, and a plurality of the above-mentioned build-up layers can be sequentially stacked on the first substrate 100' To form the second substrate 200. In this embodiment, the second substrate 200 includes, for example, two buildup layers as described above, but the invention is not limited to this. In some embodiments, the second substrate 200 may also include one, or three or more build-up layers, and is not limited to those shown in FIG. 1G. In the following, the second substrate 200 includes two buildup layers, the upper and lower layers.

In this embodiment, as shown in FIG. 1F and FIG. 1G, the upper build-up layer (not labeled) can be defined as contacting the uppermost dielectric layer 220 of the first substrate 100' and the first layer of the uppermost dielectric layer 220 Two circuit layer 210. The uppermost dielectric layer 220 may form a plurality of contact windows (not labeled) to expose a portion of the first circuit layer 110. The second circuit layer 210 formed on the uppermost dielectric layer 220 can be filled into these contact windows to be electrically connected to the first circuit layer 110. In this embodiment, as shown in FIGS. 1F and 1G, the second circuit layer 210 electrically connected to the first circuit layer 110 can be defined as the topmost layer 211 of the second circuit layer 210.

Then, a lower build-up layer (not shown) is stacked on the surface of the upper build-up layer. For example, the lower build-up layer can be defined as the lowermost dielectric layer 220 contacting the upper buildup layer and the second circuit layer 210 in the lowermost dielectric layer 220. The lowermost dielectric layer 220 may form a plurality of contact windows (not labeled) to expose the part of the uppermost layer 211. The second circuit layer 210 formed on the lowermost dielectric layer 220 can be filled into these contact windows to be electrically connected to the uppermost layer 211. In this embodiment, as shown in FIG. 1G, the second circuit layer 210 electrically connected to the topmost layer 211 can be defined as the bottommost layer 212 of the second circuit layer 210, and the bottommost layer 212 described above can be exposed on the bottommost layer. The lower dielectric layer 220.

In this embodiment, the material of the dielectric layer 220 includes film (PrePreg), photosensitive dielectric material (photoimageable dielectric, PID), photosensitive polymer (such as benzocyclobutene, Benzocyclobutene), ABF film (Ajinomoto build -up film), resin coated cooper foil (RCC), glass fiber resin composite material or a combination thereof, but the present invention is not limited thereto.

In this embodiment, a portion of the multilayer second circuit layer 210 can penetrate through the dielectric layer 220 to electrically connect the second circuit layers 210 of different levels to each other, and the other part of the second circuit layer 210 is only located at the same The horizontal second circuit layer 210 is interconnected. In other words, the second circuit layer 210 can provide the horizontal and vertical wiring requirements of the second substrate 200.

In this embodiment, the second circuit layer 210 may be arranged in a process of general wiring or high-density wiring. For example, the line width of the second circuit layer 210 may be 5 micrometers to hundreds of micrometers, but the invention is not limited thereto. In some embodiments, the thinnest line width of the second circuit layer 210 may optionally be 8 μm to 25 μm, but is not limited thereto. Based on the consideration of conductivity, the second circuit layer 210 generally uses metal materials, such as copper, aluminum, silver, gold or other suitable materials, but the present invention is not limited thereto. According to other embodiments, the second circuit layer 210 may also use other conductive materials such as alloys, oxides of metal materials, nitrides of metal materials, oxynitrides of metal materials, or stacked layers of metal materials and other conductive materials. . In this embodiment, the method for forming the second circuit layer 210 includes electroplating or electroless plating, but the invention is not limited thereto.

Then, referring to FIG. 1G and FIG. 1H, the second temporary carrier board 20 is removed to separate the release layer 22 from the second temporary carrier board 20. The method of removing the second temporary carrier 20 includes, for example, reducing the viscosity of the release layer 22 by illuminating, heating, or dissociating by laser, and then separating the metal layer 21 on the second temporary carrier 20 from the release layer. Layer 22 is separated. So far, the steps of manufacturing the second substrate 200 and bonding the second substrate 200 to the first substrate 100' are substantially completed. In other words, the above-mentioned second substrate 200 is a circuit board including two build-up layers with a second circuit layer 210 and a dielectric layer 220. In this embodiment, the second substrate 200 having the second circuit layer 210 is, for example, a high-density interconnect (HDI), a coreless substrate (coreless) or any-layer printed circuit board (any-layer printed circuit board). board) technology of the substrate.

It is worth noting that, in this embodiment, the second substrate 200 with a general line width that does not apply ultra-fine circuit technology can be directly fabricated on the first substrate 100' with the first circuit layer 110 of ultra-fine circuit. In this way, the present invention can directly electrically connect the first circuit layer 110 with a smaller line width to the second circuit layer 210 with a larger line width in a simple manufacturing method. Therefore, the manufacturing process can be simplified and the cost can be reduced.

Next, referring to FIG. 1H and FIG. 1I, in this embodiment, the step of forming the first substrate 100 further includes a thinning process. The above thinning process can remove part of the insulating adhesive material 140' to form the insulating adhesive layer 140 and expose the pads 132 of the conductive structure 130. In this embodiment, the release layer 22 may be removed before the step of the thinning process. The method of removing the release layer 22 is similar to the method of removing the second temporary carrier 20, so it will not be described again, but it is not limited thereto. In some embodiments, the release layer 22 may be removed at the same time as the thinning process is performed.

In this embodiment, the thinning process includes through a reactive ion plasma etching (Reactive-Ion Etching, RIE) process, through a half tone mask (HTM), gray tone mask (grey tone mask) or phase The phase shift mask is subjected to a development process to remove part of the insulating adhesive material 140', but the invention is not limited thereto. Under the above configuration, the formed insulating adhesive layer 140 can expose the pad 132 and partially contact the sidewall (not labeled) of the pad 132. In short, a thinning process is performed on the first substrate 100' that has not yet exposed the pads 132 to expose the pads 132, thereby completing the production of the first substrate 100. In this embodiment, the insulating adhesive layer 140 surrounds and contacts the edge of the pad 132 (as shown in FIG. 2A ), so that the pad 132 is half exposed so that the pad 132 can be partially embedded in the insulating adhesive layer 140. From another perspective, there is an insulating adhesive layer 140 between the pads 132 of the conductive structures 130. In this way, the insulating adhesive layer 140 can not only increase the structural reliability of the pad 132, but also protect the pad 132 and the insulating layer 120, and can also have a solder resist effect, and the step of providing a solder resist layer SR is omitted to simplify the manufacturing process. And save costs.

Then, referring to FIG. 1J, a plurality of solder resist layers SR are formed on the first substrate 100 and the second substrate 200, respectively. In this embodiment, the two solder mask layers SR partially cover the conductive structure 130 on the first substrate 100 and the bottom layer 212 of the second circuit layer 210 on the second substrate 200 respectively. For example, the solder mask SR on the first substrate 100 and the second substrate 200 may have a plurality of contact windows (not labeled) to expose the pads 132 and the bottom layer 212 of the second circuit layer 210 respectively. In this embodiment, the material of the solder mask SR includes green paint, photosensitive dielectric material, ABF film, and polymer resin material, but the invention is not limited to this.

Next, referring to FIGS. 1J and 1K, a plurality of electronic components 300 are disposed on the first substrate 100 to be electrically connected to the pads 132 and the first circuit layer 110. In this embodiment, the electronic component 300 is an example of a chip. As shown in FIG. 1K, the plurality of electronic components 300 includes, for example, a first electronic component 310 and a second electronic component 320, and the first electronic component 310 and the second electronic component 320 respectively have a plurality of conductive bumps 311, 321. In this embodiment, the first electronic component 310 and the second electronic component 320 further have solder balls 312 and 322 respectively disposed on the conductive bumps 311 and 321, but the invention is not limited thereto. The first electronic component 310 and the second electronic component 320 can be electrically connected to the pad 132 through the conductive bumps 311 and 321 and the solder balls 312 and 322. Based on the consideration of conductivity, the conductive bumps 311 and 321 generally use metal materials or alloys, such as copper, aluminum, silver, gold or alloys of the foregoing metals or other suitable materials, but the present invention is not limited thereto.

Finally, a plurality of solder balls SB are disposed on the second substrate 200 and electrically connected to the bottom layer 212 of the second circuit layer 210. So far, the production of the circuit carrier board 1 has been completed.

FIG. 2A is a partial top view schematic diagram of the top surface of the pad in the region R of FIG. 1A. For the convenience of description and observation, FIG. 2A only schematically illustrates some components. FIG. 2B is a partial top view schematic diagram of the bottom surface of the conductive via and the first circuit layer in the region R of FIG. 1A. For the convenience of description and observation, FIG. 2B only schematically shows some components. Please refer to FIG. 1 and FIG. 2A. FIG. 2A shows that the pad 132 in the region R is located on the plane of the insulating adhesive layer 140. The pad 132 (marked in FIG. 1K) has a top surface 132T. In this embodiment, since the first substrate 100 is, for example, a rearranged circuit layer applying ultra-fine circuit technology, the plurality of conductive structures 130 may have fine pitches between them. For example, the distance W1 between the pads 132 of any two adjacent conductive structures 130 may be less than or equal to 60 microns. In some embodiments, the minimum distance W1 between any two adjacent pads 132 may optionally be 10 μm to 60 μm.

請參考圖1及圖2B，圖2B所繪示的是區域R中的導電通孔134接觸第一線路層110而位於絕緣層120的界面。導電通孔134（標示於圖1K）中具有底面134B。在本實施例中，底面134B的直徑D2可以小於或等於30微米。在一些實施例中，相鄰底面134B的直徑D2可以選擇性地為10微米至30微米。相較於底面134B的直徑D2，第一線路層110的線寬D1可以小於或等於底面134B的直徑D2。

Please refer to FIGS. 1 and 2B. FIG. 2B illustrates that the conductive via 134 in the region R contacts the first circuit layer 110 and is located at the interface of the insulating layer 120. The conductive via 134 (marked in FIG. 1K) has a bottom surface 134B therein. In this embodiment, the diameter D2 of the bottom surface 134B may be less than or equal to 30 microns. In some embodiments, the diameter D2 of the adjacent bottom surface 134B may optionally be 10 μm to 30 μm. Compared with the diameter D2 of the bottom surface 134B, the line width D1 of the first circuit layer 110 may be less than or equal to the diameter D2 of the bottom surface 134B.

Under the above arrangement, please refer to FIGS. 1, 2A and 2B, the orthographic projection of the conductive via 134 contacting the bottom surface 134B of the first circuit layer 110 on the second substrate 200 will be located on the top surface 132T of the pad 132 at the first Within the orthographic projection on the second substrate 200. In other words, the cross-sectional shape of the conductive via 134 is, for example, a tapered shape, and the portion contacting the pad 132 has a larger area, while the portion contacting the first circuit layer 110 has a smaller area. In this way, the first circuit layer 110 can also have a good design margin under the ultra-fine circuit process.

It is worth noting that, in the circuit carrier 1 of an embodiment of the present invention, since the first substrate 100 is a rearranged circuit layer applying ultra-fine circuit technology, the first circuit layer 110 has an ultra-fine line width and a fine pitch Set the pad 132. Under the above configuration, the electronic component 300 (including the first electronic component 310 and the second electronic component 320) with high-density circuits can be directly electrically connected to the pad 132, and interconnection is achieved through the first circuit layer 110 . In other words, the circuit carrier 1 is suitable for interconnecting a plurality of high-density circuit electronic components 300, so that the signal delay can be reduced and the performance of the circuit carrier 1 can be improved.

In addition, the plurality of electronic components 300 can also be directly electrically connected to the second conductive layer 210 (including the topmost layer 211 and the bottommost layer 212) of the second substrate 200 through the first conductive layer 100 of the first substrate 100. Therefore, in addition to bonding the first substrate 100 with ultra-fine circuits on the entire surface to the second substrate 200 to simplify the manufacturing process and increase the wiring margin of the circuit carrier 1, it can also pass through the multiple dielectric layers of the second substrate 200 The build-up layer formed by 220 supports the first substrate 100, thereby improving the overall rigidity of the circuit carrier 1 to improve the reliability of the structure.

In short, due to the manufacturing method of the circuit carrier board 1 of this embodiment, the second substrate 200 with a general line width can be directly formed and bonded to the first substrate of the first circuit layer 110 with ultra-fine circuits. Therefore, it is possible to directly integrate the first circuit layer 110 and the second circuit layer 210 made of different finenesses on the circuit carrier board 1, thereby simplifying the manufacturing process, reducing the cost and improving the wiring margin. In addition, a plurality of electronic components 300 (including the first electronic component 310 and the second electronic component 320) with high-density circuits can be directly and electrically connected to the first substrate 100 of the pads 132 arranged at a fine pitch. Under the above configuration, these electronic components 300 can be interconnected through the first circuit layer 110. In this way, the circuit carrier 1 is suitable for interconnecting a plurality of high-density circuit electronic components 300, thereby reducing signal delay and improving the performance of the circuit carrier 1. In addition, the second substrate 200 can further support the first substrate 100, thereby improving the overall rigidity of the circuit carrier 1 to improve the reliability of the structure.

The following embodiments follow the component numbers and part of the content of the previous embodiments, where the same numbers are used to represent the same or similar components. For the omission of the same technical content, please refer to the aforementioned embodiments. The following embodiments will not Repeat it.

3A to 3K are schematic cross-sectional views of a manufacturing process of a circuit carrier board according to another embodiment of the present invention. Please refer to FIGS. 1K and 3K. The circuit carrier board 1A of this embodiment is similar to the circuit carrier board 1 of FIG. 1K. The main difference is: the circuit carrier board 1A is to complete the second substrate 200 first, and then complete the conductive structure 130 settings. Therefore, in the structure, the first circuit layer 110 can be directly covered with the insulating adhesive layer 140A to serve as a build-up layer of the first substrate 100A, so there is no need to additionally use the insulating layer 120 (shown in FIG. 1K). The manufacturing process of the circuit carrier board 1A will be briefly described below. The same or similar elements and steps will not be repeated.

Please refer to FIG. 3A, the first circuit layer 110 is formed on the first temporary carrier board 10.

Referring to FIG. 3B, an insulating adhesive material 140' is formed on the first circuit layer 110 to form a first substrate 100'. In other words, the first substrate 100'' of this embodiment includes a build-up layer composed of the first circuit layer 110 and the insulating adhesive material 140', but the invention is not limited to this. In some embodiments, the first substrate 100'' may also include a multi-layer build-up layer composed of the first circuit layer 110 and the insulating adhesive material 140' sequentially stacked. The first substrate 100" of this embodiment is, for example, a substrate that has not yet provided the conductive structure 130 on the exposed first circuit layer 110, and in a subsequent step, a first substrate 100A having the conductive structure 130 (shown In Figure 3I).

Please refer to FIG. 3C and FIG. 3D, the first substrate 100'' is disposed on the second temporary carrier 20. Then, the first temporary carrier 10 and the release layer 12 on the first temporary carrier 10 are removed.

3E and 3F, the second substrate 200 is disposed on the surface 101A of the insulating adhesive material 140' of the first substrate 100''. For example, the second substrate 200 includes a plurality of build-up layers (for example, two build-up layers) composed of a dielectric layer 220 and a second circuit layer 210. In detail, a dielectric layer 220 can be first disposed on the surface 101A of the insulating material layer 140', and then the topmost layer 211 of the second circuit layer 210 is formed to be electrically connected to the first through the contact window (not shown) A circuit layer 110. Then, another dielectric layer 220 covers the topmost layer 211, and then the bottommost layer 212 of the second circuit layer 210 is formed to be electrically connected to the topmost layer 211 through a contact window (not shown). 3E and 3F, the insulating adhesive material 140' also has another surface 103A opposite to the surface 101A, and the other surface 103A is located between the insulating adhesive material 140' and the second temporary carrier 20.

Referring to FIG. 3G, the second temporary carrier 20 is removed, and the step of bonding and forming the second substrate 200 on the first substrate 100'' is completed.

Please refer to FIGS. 3G and 3H, a plurality of contact windows 142 are formed in the insulating adhesive material 140' to form an insulating adhesive layer 140A.

Please refer to FIG. 3I, and then, a plurality of conductive structures 130 are formed in the insulating adhesive layer 140A. So far, the setup of the first substrate 100A is completed. In this embodiment, the first substrate 100A includes a first circuit layer 110 embedded on the surface 101A of the insulating adhesive layer 140A, and the conductive structure 130 is disposed in the insulating adhesive layer 140A. The pad 132 of the conductive structure 130 is disposed on the other surface 103A. The plurality of contact windows 142 of the insulating adhesive layer 140A exposes the first circuit layer 110, and the conductive vias 134 of the conductive structure 130 are filled in the contact windows 142 to contact and electrically connect to the first circuit layer 110. In this embodiment, the method for forming the plurality of contact windows 142 includes photolithography, mechanical drilling, laser drilling or other suitable methods, and the present invention is not limited thereto.

Please refer to FIG. 3J. Next, a plurality of solder resist layers SR are formed on the first substrate 100A and the second substrate 200, respectively. In this embodiment, the two solder mask layers SR partially cover the conductive structure 130 on the first substrate 100A and the bottom layer 212 in the second circuit layer 210 on the second substrate 200, respectively.

Please refer to FIG. 3K, and then, a plurality of electronic components 300 are disposed on the first substrate 100 to be electrically connected to the pads 132 and the first circuit layer 110. In this embodiment, the plurality of electronic components 300 includes, for example, a first electronic component 310 and a second electronic component 320, and the first electronic component 310 and the second electronic component 320 respectively have a plurality of conductive bumps 311, 321. In this embodiment, the first electronic component 310 and the second electronic component 320 further have solder balls 312 and 322 respectively disposed on the conductive bumps 311 and 321, but the invention is not limited thereto. The first electronic component 310 and the second electronic component 320 can be electrically connected to the pad 132 through the conductive bumps 311 and 321 and the solder balls 312 and 322.

Finally, a plurality of solder balls SB are disposed on the second substrate 200 and electrically connected to the bottom layer 212 of the second circuit layer 210. So far, the production of the circuit carrier board 1A has been completed. Under the above configuration, since the second substrate 200 can be formed on the insulating adhesive material 140' of the first substrate 100A first, and then the conductive structure 130 can be set up, the insulating adhesive layer 140A can replace the insulating layer 120, which further simplifies the manufacturing process ,cut costs. In addition, with the above-mentioned design, the circuit carrier board 1A of this embodiment can also achieve the same effect as the above-mentioned embodiment, so it will not be repeated here.

4 is a schematic cross-sectional view of a circuit carrier board according to another embodiment of the present invention. Please refer to FIG. 1K and FIG. 4. The circuit carrier board 1B of this embodiment is similar to the circuit carrier board 1 of FIG. 1K. The main difference is that the circuit carrier board 1B further includes a plurality of surface-treated metal pads 160. These metal pads 160 and 260 are respectively in contact with and are disposed on the pad 132 and the bottom layer 212 of the second circuit layer 210. From another perspective, the metal pad 160 may be located between the pad 132 and the solder balls 312 and 322 of the circuit element 300 (including the first circuit element 310 and the second circuit element 320). The metal pad 260 may be located between the bottom layer 212 of the second circuit layer 210 and the solder ball SB.

In this embodiment, the method for forming the metal pads 160 and 260 includes performing surface treatment on the pads 132 and the bottom layer 212 of the second circuit layer 210. Surface treatment includes electroless nickel/electroless palladium/ immersion gold (ENEPIG), electroless nickel autocatalytic gold (ENAG), immersion tin (IT), micro Micro-ball and 305 tin-silver-copper alloy solder paste (SAC 305). Under the above arrangement, the metal pads 160 and 260 can not only protect the pad 132 and the second circuit layer 210, but also improve the conductivity of the pad 132 and the second circuit layer 210, and further improve the overall performance of the circuit carrier 1B . In addition, through the above-mentioned design, the circuit carrier board 1B of this embodiment can also achieve the same effect as the above-mentioned embodiment, so it will not be repeated here.

In summary, the circuit carrier board and the manufacturing method thereof according to an embodiment of the present invention can directly form the second substrate with a general line width and bond the entire surface to the second substrate of the first circuit layer with ultra-fine lines. Therefore, it is possible to directly integrate the first circuit layer and the second circuit layer manufactured with different finenesses on the circuit carrier on a substrate, thereby simplifying the manufacturing process, reducing the cost and improving the wiring margin. In addition, a plurality of electronic components with high-density circuits (including: the first electronic component and the second electronic component) can be directly electrically connected to the first substrate of the pads arranged at a fine pitch. Under the above arrangement, these electronic components can be interconnected through the first circuit layer. In this way, the circuit carrier is suitable for interconnecting multiple high-density circuit electronic components, thereby reducing signal delay and improving the performance of the circuit carrier. In addition, the multiple build-up layers of the second substrate can further support the first substrate, thereby increasing the overall rigidity of the circuit carrier board to improve the reliability of the structure.

In addition, the circuit carrier board can also expose the pad through the insulating adhesive layer to increase the structural reliability of the pad, and it can also protect the pad and the insulating layer. It can also have the effect of soldering and eliminating the need for a solder mask. The steps to simplify the process and save costs.

In addition, the manufacturing method of the circuit carrier can also complete the setup of the second substrate first, and then complete the setup of the conductive structure on the first substrate. Therefore, the first circuit layer can be directly covered with an insulating adhesive layer to replace the insulating layer to further simplify the manufacturing process and save costs.

Furthermore, the circuit carrier may further include metal pads disposed on the pads and the bottom layer of the second circuit layer. Therefore, the metal pad can protect the pad and the second circuit layer, and can also improve the conductivity of the pad and the second circuit layer, thereby further improving the overall performance of the circuit carrier.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.

1, 1A, 1B: circuit carrier board 10: The first temporary carrier board 12, 22: Release layer 20: second temporary carrier board 21: Metal layer 100, 100’, 100’’, 100A: first substrate 101, 101A: Surface 103, 103A: another surface 110: First circuit layer 120: insulating layer 122, 142: contact window 130: conductive structure 132: Pad 132T: Top surface 134: Conductive vias 134B: Bottom 140, 140A: insulating adhesive layer 140’: Insulating adhesive material 160, 260: metal pads 200: second substrate 210: second circuit layer 211: top 212: bottom 220: Dielectric layer 300: electronic components 310: The first electronic component 311, 321: conductive bumps 312, 322, SB: solder ball 320: second electronic component D1: line width D2: diameter R: area SR: Solder mask W1: Spacing

1A to 1K are schematic cross-sectional views of a manufacturing process of a circuit carrier board according to an embodiment of the invention. FIG. 2A is a schematic partial top view of the top surface of the pad in the region R of FIG. 1A. 2B is a schematic partial top view of the bottom surface of the conductive via and the first circuit layer in the region R of FIG. 1A. 3A to 3K are schematic cross-sectional views of a manufacturing process of a circuit carrier board according to another embodiment of the present invention. 4 is a schematic cross-sectional view of a circuit carrier board according to another embodiment of the present invention.

1: Line carrier board

100: first substrate

101: Surface

103: another surface

110: First circuit layer

120: insulating layer

122: contact window

130: conductive structure

132: Pad

132T: Top surface

134: Conductive vias

134B: Bottom

140: insulating adhesive layer

200: second substrate

210: second circuit layer

211: top

212: bottom

220: Dielectric layer

300: electronic components

310: The first electronic component

311, 321: conductive bumps

312, 322, SB: solder ball

320: second electronic component

R: area

SR: Solder mask

W1: Spacing

Claims (20)

A method for manufacturing a circuit carrier board, including: Provide a first temporary carrier board; Forming a first substrate on the first temporary carrier, the first substrate including a first circuit layer and a plurality of conductive structures, and the conductive structures are suitable for electrically connecting to a plurality of electronic components; Performing a bonding step to bond the first substrate to a second temporary carrier, and the conductive structures are located between the first circuit layer and the second temporary carrier; Remove the first temporary carrier board; A second substrate is formed on the first substrate to bond the second substrate to the first substrate, and the second substrate includes: Multiple dielectric layers; and A plurality of second circuit layers are arranged in the dielectric layers, the bottommost layer of the second circuit layers is exposed to the dielectric layers, and the topmost layer of the second circuit layers is electrically connected to the The first circuit layer; and Remove the second temporary carrier board. According to the manufacturing method of the circuit carrier board described in item 1 of the scope of patent application, the step of forming the first substrate includes: Forming a release layer on the first temporary carrier; Forming the first circuit layer on the release layer; Forming an insulating layer on the release layer and covering the first circuit layer; Forming the conductive structures on the insulating layer, and the conductive structures are electrically connected to the first circuit layer; and An insulating adhesive material is formed on the insulating layer, and the conductive structures are located between the insulating adhesive material and the insulating layer. According to the manufacturing method of the circuit carrier board described in claim 2, wherein the step of forming the first substrate further includes performing a thinning process to remove part of the insulating adhesive material to form an insulating adhesive layer and expose These conductive structures. According to the manufacturing method of the circuit carrier board described in item 1 of the scope of patent application, the step of forming the second substrate includes: Forming the dielectric layers to be sequentially stacked on the first substrate; and The second circuit layers are formed in the dielectric layers, and the second circuit layers are electrically connected to each other. According to the manufacturing method of the circuit carrier board described in item 4 of the scope of patent application, the second substrate is disposed on the insulating layer. According to the manufacturing method of the circuit carrier board described in item 1 of the scope of patent application, the step of forming the first substrate includes: Forming a release layer on the first temporary carrier; Forming the first circuit layer on the release layer; and An insulating adhesive material is formed on the first circuit layer. According to the manufacturing method of the circuit carrier board described in item 6 of the scope of patent application, the second substrate is disposed on the insulating adhesive material. According to the manufacturing method of the circuit carrier board described in item 6 of the scope of patent application, the step of forming the first substrate further includes: After the step of forming the second substrate on the first substrate, forming a plurality of contact windows in the insulating adhesive material to form an insulating adhesive layer; and The conductive structures are formed in the insulating adhesive layer, and the conductive structures are electrically connected to the first circuit layer through the contact windows. The manufacturing method of the circuit carrier board described in item 1 of the scope of patent application further includes: Forming a plurality of solder mask layers on the first substrate and the second substrate respectively, partially covering the conductive structures and the bottommost layer of the second circuit layers; and A plurality of solder balls are arranged to be electrically connected to the bottommost layer of the second circuit layers. A circuit carrier board, including: A first substrate including a first circuit layer and a plurality of conductive structures electrically connected to the first circuit layer, the conductive structures being suitable for electrically connecting to a plurality of electronic components; and A second substrate is bonded to the first substrate and contacts the first circuit layer. The second substrate includes: A plurality of dielectric layers are sequentially stacked on the first substrate; and A plurality of second circuit layers are disposed in the dielectric layers, the bottommost layer of the second circuit layers is exposed to the dielectric layers, and the topmost layer of the second circuit layers is electrically connected to the first A circuit layer, The conductive structures include a plurality of pads and a plurality of conductive vias, and the pads are electrically connected to the first circuit layer through the conductive vias, Wherein the orthographic projection of each of the conductive vias contacting a bottom surface of the first circuit layer on the second substrate is within the orthographic projection of a top surface of each of the pads on the second substrate, The line width of the first circuit layer is smaller than the line width of the second circuit layer. The circuit carrier board according to item 10 of the scope of patent application, wherein the first substrate further includes: An insulating layer, the first circuit layer is embedded on a surface of the insulating layer; and An insulating adhesive layer is disposed on the other surface of the insulating layer opposite to the surface, The conductive structures are arranged in the insulating layer, part of each of the pads is arranged on the other surface, and the insulating adhesive layer surrounds each of the pads. The circuit carrier board described in item 11 of the scope of patent application, wherein the material of the insulating layer is selected from ABF film, glue or photosensitive dielectric material. The circuit carrier board described in item 11 of the scope of patent application, wherein the material of the insulating adhesive layer is selected from thermosetting polymers or photosetting polymers. The circuit carrier board according to item 10 of the scope of patent application, wherein the first substrate further includes: An insulating adhesive layer, the first circuit layer is embedded on a surface of the insulating adhesive layer, and the insulating adhesive layer has a plurality of contact windows, The conductive structures are disposed in the insulating adhesive layer, the pads are disposed on the other surface opposite to the surface, and the conductive vias are respectively filled in the contact windows to contact the first Line layer. The circuit carrier board as described in item 10 of the scope of patent application includes: A plurality of solder masks are respectively disposed on the first substrate and the second substrate, partially covering the conductive structures and the bottommost layer of the second circuit layers; and A plurality of solder balls are arranged on the second substrate and are electrically connected to the bottom layer of the second circuit layers. As for the circuit carrier board described in item 10 of the scope of patent application, the distance between any two adjacent ones of the pads is between 10 μm and 60 μm. In the circuit carrier board described in item 10 of the scope of patent application, the line width of the first circuit layer is between 1 μm and 5 μm. The circuit carrier board as described in item 10 of the scope of patent application, wherein the line width of the first circuit layer is less than or equal to the diameter of the bottom surface of each of the conductive vias. For the circuit carrier board described in claim 10, the pads are suitable for electrically connecting to the electronic components. For example, the circuit carrier board described in item 10 of the scope of patent application further includes a plurality of surface-treated metal pads, and the metal pads are respectively in contact with and disposed on the pads and the lowest of the second circuit layers. On the ground floor.

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