JP4726546B2 - Wiring board manufacturing method - Google Patents

Wiring board manufacturing method Download PDF

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JP4726546B2
JP4726546B2 JP2005163673A JP2005163673A JP4726546B2 JP 4726546 B2 JP4726546 B2 JP 4726546B2 JP 2005163673 A JP2005163673 A JP 2005163673A JP 2005163673 A JP2005163673 A JP 2005163673A JP 4726546 B2 JP4726546 B2 JP 4726546B2
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core
layer
sub
ceramic
resin
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JP2006339482A (en
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誠 折口
正樹 村松
伸治 由利
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日本特殊陶業株式会社
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01041Niobium [Nb]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/30107Inductance

Description

The present invention relates to a method of manufacturing a wiring board comprising a core substrate ceramic sub-core made of a ceramic is housed.

  Conventionally, an organic package substrate is used as a wiring substrate on which a semiconductor integrated circuit element (hereinafter referred to as “IC chip”) is mounted. The organic package substrate has a dielectric layer made of a polymer material and a conductor layer made of a metal material alternately laminated on a core substrate mainly made of a polymer material such as an epoxy resin reinforced with glass fiber. It has a structure in which a wiring laminated portion is formed. However, organic package substrates are mainly made of polymer materials, so if thermal history such as solder reflow is added, there is a risk of problems such as disconnection due to differences in the linear expansion coefficient with IC chips mainly made of silicon. . Therefore, in Patent Document 1, in order to reduce the difference in coefficient of linear expansion between the IC chip and the wiring board, a structure in which a sub-core made of ceramic having a smaller coefficient of linear expansion than the core body made of a polymer material is accommodated in the core board. A wiring board having the following has been proposed.

JP 2005-39217 A

  By the way, in the core substrate as described above, after the ceramic sub-core is accommodated in the sub-core accommodating portion formed in the core main body, a filling resin containing an inorganic filler such as silica filler is provided in the gap between the core main body and the ceramic sub-core. It can be obtained by injecting with a known dispenser or the like. Here, the filled resin plays a role of absorbing the difference in linear expansion coefficient between the ceramic sub-core and the core body by its own elastic deformation, and therefore is closer to the linear expansion coefficient of the ceramic sub-core (smaller linear expansion coefficient). Must be used.

  However, in order to obtain a filled resin having a small linear expansion coefficient, it is necessary to contain a large amount of inorganic filler. However, as the content of the inorganic filler increases, the viscosity of the filled resin increases accordingly. When the viscosity of the filling resin is excessively high, injection by a dispenser or the like becomes difficult, and there is a problem that voids (voids) are easily generated inside during injection.

  The present invention has been made in view of the above problems, and when forming a core substrate containing a ceramic sub-core in a core body, even if it is a filled resin with a high content of inorganic filler and a high viscosity, It is an object of the present invention to provide a method of manufacturing a wiring board capable of easily filling a gap between a main body and a ceramic sub-core.

Means for Solving the Problems and Effects of the Invention

In order to solve the above problems, a method for manufacturing a wiring board according to the present invention includes:
A plate-like core body made of a polymer material is formed with a sub-core housing portion as a through hole penetrating between the principal surfaces or a recess opening in the first principal surface, and a plate-like shape made of ceramic inside And a wiring laminate formed by alternately laminating dielectric layers and conductor layers made of a polymer material on the main surface of the core substrate. A method for manufacturing a wiring board, comprising:
A sub core housing step of housing the ceramic sub core from the opening side of the first main surface of the sub core housing portion;
A resin paste is press-fitted with a squeegee from the first main surface side of the ceramic sub-core and the core main body, and the resin paste is filled in a gap between the ceramic sub-core and the core main body, and on the first main surface of the ceramic sub-core. A press-fitting printing step of forming a coating and forming a continuous resin layer continuous with the resin paste ;
Are included in this order.

  According to the method for manufacturing a wiring board of the present invention, a resin paste is press-fitted (filled) into the gap between the ceramic sub-core and the core body using a squeegee, thereby filling the gap between the ceramic sub-core and the core body. The filling resin to be fixed can be favorably formed without generating voids.

  Here, the viscosity of the resin paste is preferably 3 Pa · s or more and 60 Pa · s or less at room temperature (for example, 25 ° C.) or more and 120 ° C. or less (more preferably 5 Pa · s or more and 58 Pa · s or less). In order to perform press-fitting printing with a squeegee, it is preferable to have a viscosity equal to or higher than the lower limit. On the other hand, when the upper limit is exceeded, the fluidity of the resin paste is too low, and there is a possibility that the resin paste cannot be satisfactorily filled even by press-fitting printing with a squeegee. In order to obtain such a viscosity, the filler content of the resin paste is preferably 50 wt% or more and 80 wt% or less (more preferably 52 wt% or more and 78 wt% or less).

  Next, in the method for manufacturing a wiring board of the present invention, in the press-fitting printing step, at least the first main surface of the ceramic sub-core is directly press-fitted with a resin paste without using a mask material, and the ceramic sub-core and the core main body are printed. The gap is filled with the resin paste, and at least a layer continuous with the resin paste is formed on the first main surface of the ceramic sub-core to form a filled resin continuous layer. According to this, since press-fitting printing can be performed without using a mask material on at least the first main surface of the ceramic sub-core, the process is simplified. Further, the filled resin continuous layer can be formed simultaneously with the filling of the resin paste into the gap between the ceramic sub-core and the core body.

  Furthermore, in the method for manufacturing a wiring board according to the present invention, in the press-fitting printing step, the resin sub-core and the core are directly press-fitted and printed on the first main surface of the ceramic sub-core and the core body without using a mask material. A resin paste is filled in the gaps of the main body, and a layer continuous with the resin paste is formed on the entire surface of the ceramic sub-core and the first main surface of the core main body to form a filled resin continuous layer. According to this, since press-fitting printing can be performed without using any mask material, the process is simplified. Moreover, it contributes to planarization of the wiring board obtained by forming the filling resin continuous layer which covered the whole main surface of such a core board | substrate.

  Next, in the method for manufacturing a wiring board according to the present invention, the opening on the second main surface side of the sub core housing portion formed as a through-hole penetrating between the main surfaces of the core body is performed on the surface before the sub core housing step. And a closing step of closing the adhesive so that the adhesive is exposed to the inside of the sub-core housing portion. In the sub-core housing step, the ceramic sub-core is connected to the first main surface of the sub-core housing portion. In this state, the press-fitting printing process can be performed. According to this, when the sub core housing part is formed as the through hole, the press-fitting printing process can be performed in a state where the ceramic sub core is fixed by the adhesive on the surface of the sheet material.

  Further, in the method for manufacturing a wiring board according to the present invention, a dielectric layer forming step of forming a dielectric layer, which is a lowermost layer of the wiring laminated portion, on the filled resin continuous layer after the press-fitting printing process, and the dielectric layer And a multi-layer through via hole forming step for forming a multi-layer through via hole penetrating across the filling resin continuous layer and exposing a conductor pad on the main surface of the ceramic sub-core, and a multi-layer in the multi-layer through via hole And a multi-layer through via conductor forming step of filling and forming the through via conductor. According to this, even if the filling resin continuous layer is interposed between the ceramic sub-core and the wiring laminated portion formed on the main surface, each has by forming the multi-layer through via conductor Conduction between internal wirings can be achieved.

The wiring board of the present invention obtained by the above manufacturing method is
A plate-shaped core body made of a polymer material is formed with a sub-core housing portion as a through-hole penetrating between the main surfaces or a recess opening in one of the main surfaces, and a plate-like shape made of ceramic inside And a wiring laminate formed by alternately laminating dielectric layers and conductor layers made of a polymer material on the main surface of the core substrate. A wiring board,
Between the layer between the ceramic sub-core and the wiring laminated portion formed on the main surface, a filling resin continuous layer that is continuous with the filling resin that fills the gap between the ceramic sub-core and the core body is interposed,
The conductor pad of the main surface of the ceramic sub-core may be configured by connecting a multi-layer through via conductor formed so as to penetrate the lowermost dielectric layer of the wiring laminated portion and the filling resin continuous layer. .

  According to the wiring board of the present invention, the ceramic sub-core and the wiring laminate are formed by forming the filling resin continuous layer continuous with the filling resin between the ceramic sub-core and the wiring laminate formed on the main surface. The linear expansion coefficient difference (that is, the linear expansion coefficient difference in the plate pressure direction) with respect to the portion (and thus the IC chip mounted thereon) can be absorbed by the elastic deformation of the filled resin continuous layer. Thereby, it is possible to prevent problems such as disconnection in the wiring around the ceramic sub-core. In addition, the filled resin continuous layer can have a structure covering the entire main surface of the core substrate, and this contributes to the flattening of the wiring substrate in addition to the above effects.

  Here, the filled resin continuous layer can be made of a material having a smaller linear expansion coefficient than the dielectric layer. In particular, the filled resin continuous layer can be made of a material having a linear expansion coefficient intermediate between the dielectric layer and the ceramic sub-core. Thereby, the effect which absorbs the linear expansion coefficient difference of the above plate pressure directions can be acquired favorably. Specifically, the filled resin continuous layer has an average linear expansion coefficient from room temperature (for example, 25 ° C.) to 200 ° C. (hereinafter simply referred to as a linear expansion coefficient) of 35 ppm / ° C. or less (preferably 33 ppm / ° C. or less: , 0 is not included). When this upper limit is exceeded, it becomes the same level as a wiring laminated portion mainly composed of a polymer material, and there is a possibility that the above effect cannot be obtained satisfactorily. In order to obtain such a linear expansion coefficient, the filled resin continuous layer can be made of a material having a filler content higher than that of the dielectric layer. Specifically, the filler content of the filled resin continuous layer can be 50 wt% or more and 80 wt% or less.

<Embodiment of wiring board>
An embodiment of a wiring board of the present invention will be described with reference to the drawings. FIG. 1 schematically shows a cross-sectional structure of the wiring board 1. In the present embodiment, the plate-like member has a surface appearing on the upper side in the drawing as the first main surface MP1 and a surface appearing on the lower side as the second main surface MP2. The wiring substrate 1 has a ceramic sub-core 3 in the lower region of the solder bump 7 in the core substrate CB, reduces the difference in coefficient of linear expansion from the semiconductor integrated circuit element (IC chip) C, and breaks due to thermal stress. Etc. are less likely to occur. Detailed description will be given below.

  FIG. 2 is a diagram showing the wiring board 1 arranged between the IC chip C and the main board (motherboard or the like) GB. The IC chip C has a signal terminal, a power supply terminal, and a ground terminal on the second main surface (not shown), and solder bumps 7 (Pb-Sn series, Sn) formed on the first main surface MP1 of the wiring board 1. -Ag-based, Sn-Sb-based, Sn-Zn-based solder, etc.). Also, an underfill material (not shown) made of a thermosetting resin is filled between the IC chip C and the first main surface MP1 of the wiring board 1 in order to improve the thermal fatigue life of the solder bumps 7. Is done. On the other hand, the main board (motherboard or the like) GB is mainly composed of a polymer material reinforced with ceramic particles and fibers as fillers, and is connected via solder balls BL formed on the second main surface MP2 of the wiring board 1. Are connected to the terminal pads 56.

  FIG. 3 is a diagram illustrating the first main surface MP1 of the wiring board 1. FIG. The solder bumps 7 are arranged in a grid pattern (or may be a staggered pattern). Among these, the power terminals 7a and the ground terminals 7b are alternately arranged in the center, and the signal terminals surround the signal terminals. 7s is arranged. These correspond to the terminals of the IC chip C.

  The core body 2 is configured in a plate shape with a heat resistant resin plate (for example, bismaleimide-triazine resin plate), a fiber reinforced resin plate (for example, glass fiber reinforced epoxy resin), or the like. A sub-core accommodating portion 25 (through hole) penetrating between the main surfaces MP1 and MP2 is formed at a position including the lower region of the solder bump 7, and a plate-shaped ceramic sub-core 3 is accommodated therein. The core substrate CB is used.

  The ceramic sub-core 3 has a through conductor 32 penetrating between the main surfaces MP1 and MP2 and a conductor pad 31 on the main surfaces MP1 and MP2 connected thereto, which are respectively connected to the power supply terminal 7a and the ground terminal 7b. Correspond. By forming the power supply and ground through conductors 32 in parallel in the ceramic sub-core 3, it is possible to reduce the inductance of the power supply and ground paths and thereby reduce the impedance.

  The ceramic sub-core 3 can be obtained by forming a via hole in a ceramic green sheet containing a ceramic material powder by punching or laser drilling, and laminating and filling a metal powder paste. As a ceramic material constituting the ceramic sub-core 3, inorganic ceramic filler such as alumina is added to 40 parts by weight or more and 60 parts by weight or less to alumina, silicon nitride, aluminum nitride or the like, borosilicate glass or lead borosilicate glass. Glass ceramic or the like can be used.

  A filling resin 4 made of a polymer material is filled in a space that forms a gap between the ceramic sub-core 3 and the core body 2 in the sub-core housing portion 25. The filling resin 4 is made of an epoxy-based resin containing an inorganic filler such as silica filler, and fixes the ceramic sub-core 3 to the core main body 2, and in-plane between the ceramic sub-core 3 and the core main body 2. It plays a role of absorbing the difference in linear expansion coefficient between the direction and the thickness direction by its own elastic deformation.

  On the first main surface MP1 side (the mounting surface side of the IC chip C) of the core substrate CB, a filling resin continuous layer 41 continuous with the filling resin 4 is formed so as to cover the entire surface of the first main surface MP1. The filling resin continuous layer 41 is integrally formed of the same resin material as that of the filling resin 4. The filling resin continuous layer 41 is interposed between the core substrate CB and the wiring laminated portion L1 formed on the first main surface MP1, thereby allowing the ceramic sub-core 3 and the wiring laminated portion L1 (and thus on the ceramic laminated core L1). A difference in linear expansion coefficient with respect to the mounted IC chip C) (that is, a difference in linear expansion coefficient in the plate pressure direction) can be absorbed by elastic deformation of the filled resin continuous layer 41. Thereby, it is possible to prevent problems such as disconnection in the wiring around the ceramic sub-core 3. In order to obtain such an effect, the filling resin continuous layer 41 may be provided only on the first main surface MP1 of the ceramic sub-core 3 as shown in FIG.

  In the wiring laminated portions L1 and L2 provided on both main surfaces MP1 and MP2 of the core substrate CB, dielectric layers B11 to B14 and B21 to B24 and conductor layers M12 to M14 and M21 to M24 are alternately laminated. It has a structure. The conductor layers M11 to M14, M21 to M24 are configured by wirings 51 and 53 made of Cu plating, pads 55 and 56, and the like. Between the conductor layers M11 to M14 and M21 to M24, interlayer connection is made by the via conductor 6, thereby forming a conduction path (for signal, power supply, and ground) from the pad 55 to the pad 56. . The pads 55 and 56 are for forming the solder bumps 7 and the solder balls BL, and the surface thereof is Ni-Au plated.

  The dielectric layers B11 to B14 and B21 to B24 are made of a polymer material such as an epoxy resin, and appropriately include an inorganic filler such as silica powder that adjusts the dielectric constant and dielectric strength. Among these, the dielectric layers B11 to B13 and B21 to B23 are called buildup resin insulation layers and via layers, and insulate the conductor layers M11 to M14 and M21 to M24, and the via conductors 6 for interlayer connection are provided. It is formed through. In particular, the dielectric layer B11 and the filling resin continuous layer 41 in the lowermost layer of the wiring laminated portion L1 are formed with a multi-layer through via conductor 65 extending through these two adjacent layers, and the ceramic sub-core 3 is the first main layer. It is connected to a conductor pad 31 on the surface MP1. On the other hand, the dielectric layers B14 and B24 are solder resist layers, and openings for exposing the pads 55 and 56 are formed.

  In addition, a through hole is formed in the core main body 2 and the dielectric layers B11 and B21 of the core substrate CB, and a through-hole conductor 21 is formed on the inner wall of the core substrate CB so as to establish conduction between the wiring laminated portions L1 and L2. . The through-hole conductor 21 corresponds to the signal terminal 7s. Inside the through-hole conductor 21, a resin hole filling material 23 made of an epoxy resin containing an inorganic filler such as a silica filler is filled and formed, and the end portion of the through-hole conductor 21 is a lid conductor made of Cu plating. 52 is formed. In addition, the area | region from the conductor layers M12 to M22 centering on a core board | substrate in which the through-hole conductor 21 and the cover conductor 52 were formed is called core area | region CR.

  The dielectric layers B11 to B14, B21 to B24 and the filling resin 4 and the filling resin continuous layer 41 are made of the same epoxy resin, but the linear expansion coefficient is adjusted by the difference in the content of the inorganic filler. Has been. That is, the filled resin 4 and the filled resin continuous layer 41 have a larger filler content than that of the dielectric layers B11 to B14 and B21 to B24, and thus have a small linear expansion coefficient. The filled resin continuous layer 41 has a linear expansion coefficient intermediate between the dielectric layers B11 to B14 and B21 to B24 and the ceramic sub-core 3. Specifically, the linear expansion coefficients of the dielectric layers B11 to B14, B21 to B24 are 40 ppm / ° C. or more and 50 ppm / ° C. or less, and the linear expansion coefficient of the ceramic sub-core 3 is 3 ppm / ° C. or more and 5 ppm / ° C. or less. On the other hand, the linear expansion coefficient of the filled resin continuous layer 41 is set to 32 ppm / ° C. or less (however, 0 is not included) (particularly when matching the linear expansion coefficient with the ceramic sub-core 3 is intended). 25 ppm / ° C. or less is preferred). Further, in order to obtain such a linear expansion coefficient, the filler content of the filled resin continuous layer 41 can be 53 wt% or more and 80 wt% or less (particularly, when matching the linear expansion coefficient with the ceramic sub-core 3 is intended). Is preferably 70 wt% or more). The filled resin continuous layer 41 can be a resin obtained by adding an acid anhydride to an epoxy resin, or a resin such as an amine.

<First Modification of Wiring Board>
A first modification (wiring board 1 ′) of the wiring board 1 will be described. In the following, portions different from the wiring board 1 are mainly described, and overlapping portions are denoted by the same reference numerals in the drawing and description thereof is omitted. A wiring board 1 ′ shown in FIG. 9 is formed by incorporating a thin film capacitor portion 3C (electronic component) on the first main surface MP1 side of the ceramic sub-core 3 ′. The thin film capacitor portion 3C is for reducing the switching noise of the IC chip C and stabilizing the operation power supply voltage. The thin film capacitor portion 3C is on the first main surface MP1 side (ceramic substrate 34) of the ceramic sub-core 3 'which is directly under the solder bump 7. The wiring length between the IC chip C and the thin film capacitor 3C is shortened and contributes to the reduction of the inductance component of the wiring. Further, the first principal surface MP1 side of the ceramic sub-core 3 ′ in which the thin film capacitor unit 3C is incorporated is covered (protected) by the filled resin continuous layer 41, thereby absorbing the difference in linear expansion coefficient in the plate pressure direction. And can prevent problems such as disconnection of surrounding wiring.

  The thin film capacitor portion 3C is formed by alternately laminating a plurality of dielectric thin films 38 and a plurality of electrode conductor thin films 36 and 37 forming a capacitor. There are two types of electrode conductor thin films 36 and 37 that are DC-separated from each other, a power-side electrode conductor thin film corresponding to the power terminal 7a and a ground-side electrode conductor thin film corresponding to the ground terminal 7b. They are arranged alternately in the stacking direction in a form separated by 38.

  Such a thin film capacitor portion 3C can be manufactured by repeating film formation by a well-known film formation technique and patterning by a well-known photolithography technique. The electrode conductor thin films 36 and 37 can be made of a metal such as Cu, Ag, Au, or Pt, for example, and are formed by a vapor phase film forming method such as sputtering or vacuum evaporation. On the other hand, the dielectric thin film 38 is made of an oxide or nitride, and is formed by a vapor deposition method such as high-frequency sputtering, reactive sputtering, or chemical vapor deposition (CVD). In the case of an oxide (a composite oxide having a perovskite crystal structure, for example, one or more of barium titanate, strontium titanate, and lead titanate) It can also form by the solution film-forming method (Chemical Solution Deposition: CSD).

  Specifically, the thin film capacitor unit 3C can be manufactured, for example, according to the steps as shown in FIGS. The thin film capacitor portion 3C is formed on a ceramic substrate 34. As described above, the ceramic substrate 34 is formed by a known ceramic green sheet containing a ceramic raw material powder and punching or laser drilling. It is obtained by laminating and firing a via hole filled with a metal powder paste.

  First, in step C <b> 1, a metal thin film 367 is formed on the main surface of the ceramic substrate 34. Then, the process proceeds to Step C2, and the periphery of the through conductor 32 corresponding to the power source or the ground in the metal thin film 367 is etched in a donut shape, so that the through conductor 32 and the electrode conductor thin film 36 are separated. FIG. 12 shows a top view of this. Subsequently, the process proceeds to Step C3, and a dielectric thin film 38 is formed by, for example, a sol-gel method so as to cover the entire surface of the electrode conductor thin film 36. In Step C4, the dielectric thin film 38 is opened at a position corresponding to the through conductor 32. Form. Next, in step C5, a metal thin film 367 is formed in the same manner as in step C1, and in step C6, the periphery of the through conductor 32 different from that in step C2 is etched into a donut shape, so that the through conductor 32 and the electrode conductor thin film 37 are etched. And are separated. FIG. 12 shows a top view of this. By repeating the above steps, a structure in which a plurality of dielectric thin films 38 and a plurality of electrode conductor thin films 36 and 37 are alternately laminated is obtained.

<Second Modification of Wiring Board>
A description will be given of a second modified example (wiring board 1 ″) of the wiring board 1. Hereinafter, portions different from the wiring board 1 will be mainly described, and overlapping portions will be denoted by the same reference numerals in the drawing and description thereof will be omitted. In the wiring substrate 1 ″ shown in FIG. 13, the entire ceramic sub-core 3 ″ is configured as a multilayer ceramic capacitor (electronic component). This multilayer ceramic capacitor is a thin film capacitor in the first modification (wiring substrate 1 ′). Two types of electrodes that have the same laminated structure as that of the portion 3C and that are DC-separated from each other between a power-side electrode conductor layer corresponding to the power terminal 7a and a ground-side electrode conductor layer corresponding to the ground terminal 7b The conductor layers 36 and 37 are alternately arranged in the stacking direction, separated by the ceramic layer 33. Also, the ceramic sub-core 3 "which is a multilayer ceramic capacitor as a whole. Since the first main surface MP1 side is covered (protected) by the filled resin continuous layer 41, the difference in linear expansion coefficient in the plate pressure direction can be absorbed, and problems such as disconnection of surrounding wiring can be prevented.

  Specifically, the ceramic sub-core 3 ″ made of such a multilayer ceramic capacitor is a multilayer ceramic capacitor in which electrode conductor layers 36 and 37 and ceramic layers 33 co-fired with them are alternately stacked. That is, the ceramic sub-core 3 ″ is obtained by forming the ceramic layer 33 from a ceramic green sheet, forming the electrode conductor layers 36 and 37 by printing and applying a metal paste, and co-firing these laminates. Can do. Further, the electrode conductor layers 36 or 37 are connected to each other in the stacking direction by through conductors 32 forming vias, and these are formed to be separated from each other at the time of printing patterning of the metal paste.

<Embodiment of Manufacturing Method of Wiring Board>
Next, an embodiment of a method for manufacturing a wiring board according to the present invention will be described with reference to the drawings. 4-7 is a figure showing the manufacturing process of the wiring board 1. FIG.

  In step 1, a conductor pattern 54 (conductor layer M11) is formed on both main surfaces MP1 and MP2 of the core body 2. This is a pattern etching of copper foil using a mask material for a heat-resistant resin plate (for example, bismaleimide-triazine resin plate) or fiber reinforced resin plate (for example, glass fiber reinforced epoxy resin) having copper foil on both main surfaces. Can be obtained.

  In step 2, a through-hole penetrating between the main surfaces MP1 and MP2 is formed by drilling to provide the sub-core housing portion 25. Moreover, the adhesiveness with the filling resin 4 with which it fills later can be improved by performing a roughening process with the potassium permanganate etc. with respect to the side wall of the subcore accommodating part 25 (through-hole). Furthermore, an organic compound (coupling agent) may be applied.

  In step 3 (blocking step), the opening on the second main surface MP2 side of the sub core housing part 25 (through hole) is made of the sheet material S having the adhesive ad on the surface, and the adhesive ad is in the sub core housing part 25. Close it so that it is exposed inside. The sheet material S preferably has an adhesive strength of the adhesive material ad of 8.0 N / 25 mm or more (measured by 180 ° peeling method (JIS Z 0237)). The unit [N / 25 mm] means a force measured using a sheet material having a width of 25 mm as a sample. As the material (base material) of the sheet material S, for example, a resin sheet such as polyester, polyimide, or PET can be used. As the adhesive ad applied to the surface of the sheet material S, for example, a silicon adhesive, an acrylic adhesive, a thermoplastic rubber adhesive, or the like can be used.

  In step 4 (sub-core accommodating step), the ceramic sub-core 3 is accommodated from the opening on the first main surface MP1 side of the sub-core accommodating portion 25 and is fixed to the adhesive ad. This can accommodate the ceramic sub-core 3 with high accuracy by using a known mounting device.

  In step 5 (press-fitting printing step), the resin paste 4P is press-fitted with a rubber squeegee SK from the first main surface MP1 side of the ceramic sub-core 3 and the core main body 2, and the resin paste is inserted into the gap between the ceramic sub-core 3 and the core main body 2. 4P is filled (formation of filled resin 4). By press-fitting printing with a rubber squeegee SK, the resin paste 4P is filled in the gap between the ceramic sub-core 3 and the core body 2 without generating voids. In addition, since the press-fitting printing directly press-prints the resin paste 4P on the ceramic sub-core 3 and the first main surface MP1 of the core main body 2 without using a mask material, a gap between the ceramic sub-core 3 and the core main body 2 is obtained. Simultaneously with the filling of the resin paste 4P, a continuous layer is formed on the entire surface of the ceramic main core 3 and the first main surface MP1 of the core body 2 (formation of the filled resin continuous layer 41). The resin paste 4P filled and coated as described above is cured (so-called curing) by heating and drying to become the filled resin 4 and the filled resin continuous layer 41. In addition, when obtaining the filling resin continuous layer 41 which covers only the 1st main surface MP1 of the ceramic subcore 3 as shown in FIG. 8, press-fitting printing in the state which covered the 1st main surface MP1 of the core main body 2 with the mask material. I do.

  Specifically, the method for manufacturing a wiring board according to the present embodiment includes a product part region PR in which a plurality of product parts to be the wiring board 1 are arranged, as shown in FIG. 5 is performed on the manufacturing substrate constituted by the disposal margin partial region DR surrounding the substrate, and in this step 5 (press-fit printing step), the resin paste 4P is deposited on the disposal margin partial region DR, which is shown in FIG. By moving the rubber squeegee SK as described above, the gap between the ceramic sub-core 3 and the core main body 2 is filled, and a layer covering the entire surface of the first main surface MP1 of the ceramic sub-core 3 and the core main body 2 is formed.

  Here, the viscosity of the resin paste 4P is, for example, about 6 Pa · s or more and 57 Pa · s or less at room temperature (for example, 25 ° C.) or more and 120 ° C. or less (in particular, preferably 30 Pa · s or more). In order to obtain such a viscosity, the filler content of the resin paste 4P can be set to 53 wt% or more and 80 wt% or less (particularly, 70 wt% or more is preferable). The resin paste 4P can be a resin obtained by adding an acid anhydride to an epoxy resin, or can be a resin such as an amine.

  After the resin paste 4P is heated and dried and cured (so-called curing) to obtain the filled resin 4 and the filled resin continuous layer 41, a roughening treatment is performed with potassium permanganate or the like to form a dielectric formed later. Adhesion with body layers B11 and B21 can be improved.

  In addition, in the formation of the filling resin by injection by a conventional dispenser or the like, the filling resin 4 may be formed so as to rise from the first main surface MP1 of the core body 2 and the ceramic sub-core 3, which is removed. However, in the process 5 (press-fit printing process) of the present invention, there is a concern that the manufacturing process becomes complicated due to the necessity of polishing for the above-mentioned reasons, and the ceramic secondary core or the like is damaged by such polishing. Since the first main surface MP1 of the core 3 is coated with a layer of the resin paste 4P to form the filled resin continuous layer 41, it is not necessary to perform such polishing and the ceramic sub-core 3 is not damaged. . This is particularly the case when manufacturing the wiring board 1 ′ and the wiring board 1 ″ having the ceramic sub-cores 3 ′ and 3 ″ in which the capacitors are incorporated, as shown in the first and second modifications of the wiring board 1. It is advantageous.

  After step 6, dielectric layers B11 to 14, B21 to 24 and conductor layer M12 are formed on main surface MP1 (specifically, on filled resin continuous layer 41) and MP2 of core substrate CB in which ceramic sub-core 3 is accommodated. To M14 and M22 to M24 are alternately stacked to form the wiring stacked portions L1 and L2. This can be realized by using a known build-up process (semi-additive method, full-additive method, subtractive method, formation of a dielectric layer by laminating a film-like resin material, photolithography technique, etc.).

  First, in step 6 (lowermost dielectric layer forming step), dielectric layers B11 and B21 are laminated on the main surfaces MP1 and MP2 of the core substrate CB in which the ceramic sub-core 3 is accommodated. In particular, the dielectric layer B11 which is the lowermost layer of the wiring laminated portion L1 is formed on the filled resin continuous layer 41. Next, in step 7 (multi-layer through via hole forming step), the first main surface MP1 side is penetrated across the dielectric layer B11 and the filled resin continuous layer 41 by a technique such as a laser via process or a photo via process. A plurality of through-hole via holes 65a are formed, and via holes 6a are formed in the dielectric layer B21 on the second main surface MP2 side. As a result, the conductor pad 31 is exposed at the bottom of the via hole 6a and the multi-layer through via hole 65a. Further, after the formation of the via hole 6a and the multi-layer through via hole 65a, a desmear process (resin residue removal process) is performed with potassium permanganate or the like to clean the surface of the conductor pad 31.

  Next, in step 8, a through hole TH is formed by a drill or the like so as to penetrate the core substrate CB and the dielectric layers B11 and B21 and the conductor layers M11 and M21 formed on the main surfaces MP1 and MP2 in the thickness direction. To do. In step 9 (multi-layer through via conductor forming step), Cu plating (electrolytic Cu plating after electroless Cu plating) is applied to the entire surface to fill the via hole 6a and the multi-layer through via hole 65a. The 6, multi-layer through via conductor 65 is formed, and the through hole conductor 21 is formed on the inner surface of the through hole TH. Thereafter, in step 10, the lid conductor 52 is formed by filling the inside of the through-hole conductor 21 with the resin filler 23 and further applying Cu plating to the entire surface.

  Next, in step 11, the wiring 51 and the like are patterned by pattern etching of Cu plating covering the dielectric layers B11 and B21. Thus, the core region CR is obtained. Similarly, the dielectric layers B12 to B14 and B22 to B24 and the conductor layers M13, 14, M23, and M24 are alternately formed, and the dielectric layers B14 and B24 are opened by a technique such as a laser via process or a photo via process. And the pads 55 and 56 are exposed. Further, Ni—Au plating is applied to the surfaces of the pads 55 and 56, and solder bumps 7 are formed on the pads 55. Thereafter, the wiring board 1 shown in FIG. 1 is completed through predetermined inspections such as electrical inspection and appearance inspection.

  As mentioned above, although embodiment of this invention was described, this invention is not limited to these, In the range which does not lose the identity with the invention embodied in these, it can change suitably.

The figure which represents roughly the cross-section of the wiring board of this invention The figure showing the wiring board arrange | positioned between a semiconductor integrated circuit element (IC chip) and main boards (motherboard etc.) The figure showing the 1st principal surface of a wiring board The figure showing the manufacturing process of the wiring board of this invention Figure following Figure 4 Figure following Figure 5 Figure following Figure 6 The figure showing the modification of a filling resin continuous layer The figure which represents roughly the cross-section of the 1st modification of a wiring board Diagram showing manufacturing process of thin film capacitor Figure following Figure 10 The top view of the thin film capacitor part in the manufacturing process The figure which represents roughly the cross-section of the 2nd modification of a wiring board Substrate top view after completion of step 4 (sub-core accommodation step)

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Wiring board 2 Core main body 25 Sub core accommodating part 3 Ceramic sub core 4 Filling resin 41 Filling resin continuous layer 6 Via conductor 7 Solder bump CB Core board L1, L2 Wiring laminated part SK Squeegee

Claims (2)

  1. A plate-like core body made of a polymer material is formed with a sub-core housing portion as a through hole penetrating between the principal surfaces or a recess opening in the first principal surface, and a plate-like shape made of ceramic inside And a wiring laminate formed by alternately laminating dielectric layers and conductor layers made of a polymer material on the main surface of the core substrate. A method for manufacturing a wiring board, comprising:
    A sub core housing step of housing the ceramic sub core from the opening side of the first main surface of the sub core housing portion;
    The press fit printed ceramic sub-core and the first main surface side of the core body of the resin paste by the squeegee, to fill the resin paste in a gap of the core body and the ceramic sub-core, wherein the ceramic sub-core A press-fitting printing process for forming a coating on the first main surface, and forming a filled resin continuous layer continuous with the resin paste ;
    A method of manufacturing a wiring board, comprising:
  2. After the press-fitting printing step, a lowermost dielectric layer forming step of forming a dielectric layer serving as a lowermost layer of the wiring laminated portion on the filled resin continuous layer;
    Forming a multi-layer through via hole penetrating across the dielectric layer and the filling resin continuous layer, and exposing a conductive pad that the ceramic sub-core has on the first main surface inside the multi-layer through via hole; and
    In the multi-layer through via hole, a multi-layer through via conductor forming step of filling and forming a multi-layer through via conductor;
    The manufacturing method of the wiring board of Claim 1 containing this.
JP2005163673A 2005-06-03 2005-06-03 Wiring board manufacturing method Active JP4726546B2 (en)

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Application Number Priority Date Filing Date Title
JP2005163673A JP4726546B2 (en) 2005-06-03 2005-06-03 Wiring board manufacturing method
TW095119500A TWI396481B (en) 2005-06-03 2006-06-02 Wiring board and manufacturing method of wiring board
EP06011529A EP1729552A3 (en) 2005-06-03 2006-06-02 Wiring board and manufacturing method of wiring board
US11/445,288 US7696442B2 (en) 2005-06-03 2006-06-02 Wiring board and manufacturing method of wiring board
CN 200610088773 CN1874648B (en) 2005-06-03 2006-06-05 Wiring board and manufacturing method of wiring board
US12/706,695 US8863378B2 (en) 2005-06-03 2010-02-16 Method for manufacturing a wiring board

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JP4726546B2 true JP4726546B2 (en) 2011-07-20

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CN102771200A (en) * 2010-02-22 2012-11-07 三洋电机株式会社 Multilayer printed circuit board and manufacturing method therefor
WO2012009831A1 (en) * 2010-07-23 2012-01-26 欣兴电子股份有限公司 Wiring board and manufacturing method thereof
JP5536682B2 (en) * 2011-01-18 2014-07-02 日本特殊陶業株式会社 Component built-in wiring board
JP2012216601A (en) * 2011-03-31 2012-11-08 Fujitsu Ltd Electronic device manufacturing method and electronic device
JP6166878B2 (en) 2012-08-30 2017-07-19 新光電気工業株式会社 Wiring board and wiring board manufacturing method
TWI563886B (en) * 2015-10-28 2016-12-21 Ind Tech Res Inst Insulating colloidal material and multilayer circuit structure

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CN1874648B (en) 2012-10-17

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