CN104658919A - Quad-flat no-lead packaging method - Google Patents

Quad-flat no-lead packaging method Download PDF

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Publication number
CN104658919A
CN104658919A CN201510049628.5A CN201510049628A CN104658919A CN 104658919 A CN104658919 A CN 104658919A CN 201510049628 A CN201510049628 A CN 201510049628A CN 104658919 A CN104658919 A CN 104658919A
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China
Prior art keywords
metal layer
patterned metal
layer
connection pads
flat non
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CN201510049628.5A
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卓恩民
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ADL Engineering Inc
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ADL Engineering Inc
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Priority to CN201510049628.5A priority Critical patent/CN104658919A/en
Publication of CN104658919A publication Critical patent/CN104658919A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/28105—Layer connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. layer connectors on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Packaging Frangible Articles (AREA)

Abstract

The invention discloses a quad-flat no-lead packaging method. The quad-flat no-lead packaging method comprises the following steps: providing a packaging carrier plate provided with a strippable metal layer arranged on at least one surface of the packaging carrier plate; forming a first patterned metal layer on the strippable metal layer; forming a first-time patterned metal layer and stacking the first-time patterned metal layer on the first patterned metal layer; forming an insulation layer on the strippable metal layer and dividing the stacked first patterned metal layer and first-time patterned metal layer into a plurality of electrically isolated external connecting pads; forming a second patterned metal layer on the insulation layer and electorally connecting the second patterned metal layer with the external connecting pads; performing chip packaging; removing the packaging carrier plate and exposing the external connecting pads. A metal bonding layer can be arranged between the second metal layer and the insulation layer to enhance bonding. The method can increase the process yield.

Description

Four limit flat non-connection pin method for packing
The application is application number: 201010624721.1, the applying date: 2010.12.29, denomination of invention: four limit flat non-connection pin method for packing and the divisional application of the application for a patent for invention of structure made thereof.
Technical field
The present invention about a kind of semiconductor packaging, particularly a kind of four limit flat non-connection pins (quad flatno-lead) method for packing.
Background technology
In semiconductor packaging process, because the trend that electronic product is compact adds that function is on the increase, packaging density is improved constantly thereupon, also constantly reduce package dimension and improvement encapsulation technology.How to develop the packaging technology of high density and thin space and reduce the important topic that manufacturing cost is technical field for this reason always.
Summary of the invention
In order to solve the problem, one of the object of the invention is to provide a kind of four limit flat non-connection pin method for packing, can obtain the packaging technology of high density and thin space and can improve operation yield.
One of the object of the invention is to provide a kind of four limit flat non-connection pin method for packing, can use prior art and double-side technology, and compares have lower cost and advantage with use substrate.
In order to achieve the above object, provide a kind of four limit flat non-connection pin method for packing according to an aspect of the present invention, comprise the following step: provide an encapsulating carrier plate, wherein at least one surface of encapsulating carrier plate arranges a peelable metal level; Form one first patterned metal layer on peelable metal level; Formed one first time patterned metal layer, be stackingly arranged on the first patterned metal layer; Formed an insulating barrier on peelable metal level with covering first patterned metal layer, and expose first time patterned metal layer, and the first patterned metal layer of each stacking setting and first time patterned metal layer are separated into the multiple external connection pad be electrically insulated from each other by insulating barrier; Form one second patterned metal layer on insulating barrier and external connection pad, wherein the second patterned metal layer comprises at least one die pad, multiple conductive connection pads and multi-line, and externally connection pad and the second metal level are electrically connected; Carry out a chip package step; And remove encapsulating carrier plate and expose external connection pad.
Another aspect of the present invention provides a kind of four limit flat non-connection pin method for packing, and comprise the following step: provide an encapsulating carrier plate, wherein at least one surface of encapsulating carrier plate arranges a peelable metal level; Form one first patterned metal layer on peelable metal level; Form an insulating barrier on encapsulating carrier plate, cover peelable metal level, wherein insulating barrier has multiple opening with exposed portion first patterned metal layer; Form a metallic bond layer and cover insulating barrier with on the first patterned metal layer exposed; Formation one first time patterned metal layer is in this metallic bond layer, wherein patterned metal layer is stacking is arranged on the first patterned metal layer first time, and insulating barrier this first patterned metal layer of each stacking setting and first time patterned metal layer are separated into the multiple external connection pad be electrically insulated from each other; Formed one second patterned metal layer in first time patterned metal layer and this metallic bond layer of part on, wherein the second patterned metal layer comprises at least one die pad, multiple conductive connection pads and multi-line, and externally connection pad and the second metal level are electrically connected; Carry out a chip package step; And remove encapsulating carrier plate and expose external connection pad.
Advantageous Effects of the present invention is: the present invention four limit flat non-connection pin method for packing has the encapsulating carrier plate of peelable metal level by using, and this peelable metal level can be utilized to carry out patterning as packaging body external connector thereafter, the diversity of overall package technique and encapsulating structure is provided.The process of upper and lower knitting layer then can utilize its material behavior to increase the structural strength between patterned metal layer and encapsulating material, strengthen its value of thrust, and avoid causing the short circuit because of circuit bridging in the process of SMT, guard metal layer is to avoid oxidation simultaneously.In addition, all technique all can use existing technology and equipment, does not increase cost and degree of difficulty.And the technique due to the peelable metal level of patterning uses image transfer technology or the micro-shadow technology of lithographic printing, therefore effectively can reach the structure of high density and thin space.The present invention, except can using prior art, also can be applicable to double-side technology.And the present invention is compared with generally using the method for packing of substrate, encapsulating carrier plate also can be selected recyclable or reuse material, therefore has lower cost and preferably advantage.In addition, this method can coordinate and utilizes electroplating technology to make special construction and the conductive connection pads structure of thin space.
Accompanying drawing explanation
Accompanying drawing is coordinated to illustrate in detail below by way of specific embodiment, when the effect that can be easier to understand object of the present invention, technology contents, feature and reach, wherein:
Figure 1A, Figure 1B, Fig. 1 C, Fig. 1 D, Fig. 1 E, Fig. 1 F, Fig. 1 G and Fig. 1 H is the schematic flow sheet of one embodiment of the invention.
Fig. 2 A, Fig. 2 B, Fig. 2 C and Fig. 2 D are the schematic diagram of different embodiments of the invention.
Fig. 3 A, Fig. 3 B, Fig. 3 C and Fig. 3 D are the close-up schematic view of different embodiments of the invention.
Fig. 4 A, Fig. 4 B, Fig. 4 C and Fig. 4 D are the close-up schematic view of different embodiments of the invention.
Fig. 5 is the schematic diagram of one embodiment of the invention.
Fig. 6 A, Fig. 6 B and Fig. 6 C are the part run schematic diagram of one embodiment of the invention.
Fig. 7 A and Fig. 7 B is the schematic diagram of one embodiment of the invention.
Fig. 8 A, Fig. 8 B and Fig. 8 C are the schematic diagram of different embodiments of the invention.
Fig. 9 A, Fig. 9 B, Fig. 9 C, Fig. 9 D, Fig. 9 E, Fig. 9 F, Fig. 9 G, Fig. 9 H and Fig. 9 I are the schematic diagram of different embodiments of the invention.
Figure 10 A, Figure 10 B, Figure 10 C, Figure 10 D, Figure 10 E, Figure 10 F, Figure 10 G and Figure 10 H are the schematic diagram of different embodiments of the invention.
Figure 11 A, Figure 11 B, Figure 11 C, Figure 11 D, Figure 11 E, Figure 11 F, Figure 11 G, Figure 11 H, Figure 11 I, Figure 11 J, Figure 11 K and Figure 11 L are the schematic diagram of different embodiments of the invention.
Figure 12 A, Figure 12 B, Figure 12 C, Figure 12 D, Figure 12 E, Figure 12 F, Figure 12 G, Figure 12 H and Figure 12 I are the schematic diagram of different embodiments of the invention.
Embodiment
Now be described in detail as follows to preferred embodiment of the present invention, described preferred embodiment is only not used to limit the present invention with explaining.Figure 1A, Fig. 1 D, Fig. 1 E, Fig. 1 F, Fig. 1 G and Fig. 1 H is the schematic flow sheet of the four limit flat non-connection pin method for packing of one embodiment of the invention.In the present embodiment, four limit flat non-connection pin method for packing comprise the following steps.
First, as shown in Figure 1A, an encapsulating carrier plate 10 is provided.Wherein, at least one surface of this encapsulating carrier plate 10 arranges a peelable metal level 20.Then, continue referring to Fig. 1 D, a patterned metal layer 40 is formed on peelable metal level 20.Wherein, patterned metal layer 40 comprises at least one die pad 42 and multiple conductive connection pads 44.
Then, a chip 50 is set in die pad 42, as referring to figure 1e.Chip 50 can utilize an adhesion material (figure does not mark) to be fixed in die pad 42.Afterwards, a plurality of leads 60 is utilized to be electrically connected chip 50 and conductive connection pads 44.
Continue referring to Fig. 1 F, an encapsulating material 70 is utilized to cover chip 50, lead-in wire 60, conductive connection pads 44 and peelable metal level 20.
Afterwards, as shown in Figure 1 G, remove encapsulating carrier plate 10 and expose the lower surface of peelable metal level 20.
As shown in fig. 1h, a patterning program is carried out in order to form multiple external connector 22 to peelable metal level 20 (as shown in Figure 1 G).Wherein, external connector 22 and conductive connection pads 44 are electrically connected.
Continue referring to Fig. 1 H, in the present embodiment, the size of each external connector 22 is greater than the size of each conductive connection pads 44, can provide subsequent conductive material, as soldered ball, and larger contact area.But the present invention is not limited to this, the size of external connector 22 and shape depend on the demand of user and designer.In an embodiment, as Fig. 2 B, each external connector 22, such as conductive pole (conductive pillar), its size is less than the size of each conductive connection pads 44, the electric conducting material (as soldered ball) so used thereafter, can increase the bond strength with conductive pole and conductive connection pads 44.
In the present invention, the external connector of overall package body carries out Patternized technique gained to peelable metal level after utilization removes encapsulating carrier plate.Therefore, as shown in Figure 2 A, multiple external connector 22 can be designed to the external contact with rewiring (re-layout) conductive connection pads 44, so can increase the changeability of packaging body in response to customer demand.
Continue above-mentioned explanation, and in different embodiment, the surface of encapsulating carrier plate 10 can arrange the stripping of the easy stripper surface of a metal 12 in order to auxiliary peelable metal level 20.The easy stripper surface 12 of this metal can be metal material or other smooth material forms surface.
In addition, patterned metal layer 40 can utilize made by different process, made by image transfer technique or lithographic printing lithography technique.
As in an embodiment, please refer to Figure 1B, Fig. 1 C and Fig. 1 D, patterned metal layer 40 can utilize made by image transfer technique.First, arranging an image transfer layer 30 on peelable metal level 20 exposes the upper surface of the peelable metal level 20 of part, as shown in Figure 1B.Carry out plating and form patterned metal layer 40 on the peelable metal level 20 be exposed to the outside, as shown in Figure 1 C.
Finally, the making of image transfer layer 30 finishing patterns metal level 40 is removed.(figure does not show) in another embodiment, the mode forming patterned metal layer also first can form a metal level on the surface of encapsulating carrier plate, carries out a lithography program afterwards to form this patterned metal layer.
Referring to Figure 1A, Fig. 1 D, Fig. 1 E, Fig. 1 F, Fig. 1 G and Fig. 2 C, in the present embodiment, four limit flat non-connection pin method for packing comprise the following steps.First, provide an encapsulating carrier plate 10, wherein at least one surface of this encapsulating carrier plate 10 arranges a peelable metal level 20, as shown in Figure 1A.Then, form a patterned metal layer 40 on peelable metal level 20, wherein this patterned metal layer 40 comprises at least one die pad 42 and multiple conductive connection pads 44, as shown in figure ip.
Afterwards, with reference to Fig. 1 E, arranging a chip 50 in die pad 42 utilizes a plurality of leads 60 to be electrically connected chip 50 and conductive connection pads 44.Thereafter, as shown in Fig. 1 F and Fig. 1 G, utilize an encapsulating material 70 to cover chip 50, lead-in wire 60, conductive connection pads 44 and peelable metal level 20; And utilize an etching program to remove peelable metal level 20.
In the present embodiment, encapsulating carrier plate used in the present invention has peelable metal level 20, and therefore alternative is carried out patterning operation to this peelable metal level 20 or removed this peelable metal level 20 on demand completely, as shown in Fig. 1 G and Fig. 2 C.In an embodiment, also can remove the patterned metal layer 40 of part thickness while removing this peelable metal level 20 further, as shown in Fig. 1 G, Fig. 2 D.
Please refer to Fig. 3 A, Fig. 3 B, Fig. 3 C and Fig. 3 D, the structure of conductive connection pads of the present invention and external connector has outside multiple change, also optionally forms a Treatment of Metal Surface layer 80 in external connector 22 or conductive connection pads 44.Wherein, the upper and lower surface of conductive connection pads 44 all optionally arranges Treatment of Metal Surface layer 80 thereon.
In the present invention, the patterned metal layer as die pad and conductive connection pads can select the mode of electroplating to make, as long as the exposure technique that therefore develops can coordinate the spacing accomplished, the method can produce the conductive connection pads of colory small size and thin space.Compared to etching mode, affect the restriction of rate of etch and thickness owing to being limited to liquid medicine replacing velocity, its control difficulty for thin space improves.Therefore, use plating mode can have higher reliability and compliance rate, therefore can make more complicated conductive connection pads structure, as shown in Figure 5, side is the structure of stair-stepping conductive connection pads 44 '.The method also can make conductive connection pads can have a trapezoid or inverted trapezoidal structure, as shown in Figure 4 A and 4 B shown in FIG..
Continue above-mentioned explanation, make the method for this structure as described later, with reference to Fig. 1 C, power on after being coated with work one first patterned metal layer 40 between image transfer layer 30 with peelable metal level 20, can arrange image transfer layer 30 ' on the first patterned metal layer 40 exposes the upper surface of part first patterned metal layer 40, as shown in Figure 6A.Then, formation one second patterned metal layer 43 is electroplated on the first patterned metal layer 40 be exposed to the outside, as shown in Figure 6B.Then, with reference to Fig. 6 C, remove the side that image transfer layer 30 and time image transfer layer 30 ' can obtain conductive connection pads 44 ' and there is a step structure, as shown in Figure 4 C.But four limit flat non-connection pin encapsulating structures of the present invention are not limited to this, utilize said method to make conductive connection pads 44 that side as shown in Figure 4 D has a step structure.
The inventive method, by controlling image transfer layer (30, Figure 1B) shape, as trapezoidal (figure does not show), can make conductive connection pads and can have a trapezoid or inverted trapezoidal structure, as shown in Figure 4 A and 4 B shown in FIG..
Please refer to Fig. 7 A and Fig. 7 B, in an embodiment, patterned metal layer 40, except comprising at least one die pad 42 with except multiple conductive connection pads 44, also comprises a circuit 46 in order to be electrically connected conductive connection pads 44 between two.Wherein, a pair of conductive connection pads 44 in order to utilize lead-in wire 60 to be electrically connected with chip 50 between two, and another of conductive connection pads 44 is to being then electrically connected with one of external connector 22 (as shown in Figure 8 A).Wherein, as previously mentioned, Treatment of Metal Surface layer 80 is also optionally set in the conductive connection pads 44 for routing.
Continue referring to Fig. 8 A, in the present invention, do not limit the size of the die pad 42 of patterned metal layer 40.The size of die pad 42 can be equivalent to the size (as shown in Figure 8 A) of chip 50 or be greater than, is less than the size of chip 50.In the present invention, conductive connection pads 44 configuration of this cabling design is different from the design of general four limit flat non-connection pin encapsulation, effectively can shorten the line length of the routing of lead-in wire 60, also effectively can save packaging cost except after can promoting encapsulation except yield.
Continue above-mentioned explanation, please refer to Fig. 8 B, when die pad 42 ' size is less than the size of chip 50, in an embodiment, the conductive connection pads 44 be positioned at below chip 50 also can assist carries chips 50, and chip 50 can utilize insulation adhesion layer (figure does not mark) to be fixedly installed thereon.In an embodiment; die pad 42 ' can higher than the height of other conductive connection pads 44 with the height for the conductive connection pads 44 of carries chips 50; so, larger space can be provided to allow encapsulating material fully fill up space, avoid bottom chip 50, exposing the effect reaching available protecting chip 50.
Continue referring to Fig. 8 C, in an embodiment, die pad can be made up of the conductive connection pads 44 ' be arranged at below chip 50, so can effectively utilize limited position to reach the most densification design of external connector 22 or soldered ball (figure does not show).In an embodiment, the height of the conductive connection pads 44 ' of carries chips 50 also can higher than the height of other conductive connection pads 44.
Please refer to Fig. 8 A, Fig. 8 B and Fig. 8 C, in the present invention, die pad 42 ' and conductive connection pads 44 ' all can utilize electroplates to reach required thickness.Different step image transfer program then can be utilized with the chip 42 ' of general conductive connection pads 44 different-thickness to reach with conductive connection pads 44 '.
Continue above-mentioned, the four limit flat non-connection pin method for packing of further embodiment of this invention, in order to manufacture the structure as shown in Fig. 7 A and Fig. 7 B, comprise the following steps: to provide an encapsulating carrier plate, wherein at least one surface of encapsulating carrier plate arranges a peelable metal level; Form a patterned metal layer on encapsulating carrier plate, and expose the peelable metal level of part, wherein patterned metal layer comprises at least one die pad, multiple conductive connection pads, many circuits and multiple external connection pad; Carry out a chip package step; And remove encapsulating carrier plate and expose external connection pad.Wherein Fig. 9 A to Fig. 9 I is the schematic flow sheet of the four limit flat non-connection pin method for packing of one embodiment of the invention, illustrates and arranges knitting layer in patterned metal layer and the steps flow chart on the peelable metal level exposed; Figure 10 A to Figure 10 G is the schematic flow sheet of the four limit flat non-connection pin method for packing of one embodiment of the invention, illustrates and arranges the steps flow chart of knitting layer under patterned metal layer; And Figure 10 H illustrates and forms upper knitting layer and lower knitting layer respectively in patterned metal layer up and down simultaneously.Embodiment is described in detail as follows.
First, please refer to Fig. 9 A, provide an encapsulating carrier plate 10, wherein at least one surface of encapsulating carrier plate 10 arranges a peelable metal level 20.Then, as shown in Figure 9 B, form a patterned metal layer 40 above peelable metal level 20, and expose the peelable metal level 20 of part, wherein patterned metal layer 40 is containing at least one die pad 42, multiple conductive connection pads 44, many circuits 46 and multiple external connection pad 48.As shown in Figure 9 C, wire pad 82 is optionally set in the conductive connection pads 44 for routing.In this embodiment, the step forming patterned metal layer 40 comprises: arrange an image transfer layer on peelable metal level 20; Plating forms patterned metal layer 40 on peelable metal level 20; And remove image transfer layer.
In an embodiment, as shown in Figure 9 C, utilize and comprise sputter, evaporation or electric plating method and to form on one knitting layer 90 in patterned metal layer 40 with on the peelable metal level 20 be exposed to the outside.And, as shown in fig. 9d, remove the upper knitting layer 90 of part to expose wire pad 82.Then, please refer to Fig. 9 E, remove the upper knitting layer 90 of part in a suitable manner to expose segment chip bearing 42.
Then, a chip package step is carried out.As shown in fig. 9f, a chip 50 is set in die pad 42, and utilizes a plurality of leads 60 be electrically connected chip 50 and conductive connection pads 44 or be electrically connected chip 50 and wire pad 82 if any arranging wire pad 82.Further, utilize an encapsulating material 70 to encapsulate lead-in wire 60, chip 50, upper knitting layer 90 and conductive connection pads 44 or wire pad 82, wherein encapsulating material 70 encapsulates lead-in wire 60, chip 42 and conductive connection pads 44 including but not limited to utilizing the mode of injecting glue, wire mark, rotary coating.Wherein circuit 46 is electrically connected conductive connection pads 44 between two, and is electrically connected with chip 50 between two a pair of conductive connection pads 44, and another of conductive connection pads 44 is between two electrically connected with external connection pad 48.Finally, as shown in Fig. 9 F and Fig. 9 G, remove encapsulating carrier plate 10 to expose patterned metal layer 40 and the upper knitting layer 90 of part.After wherein removing support plate 10, the mode also comprising comprising etching removes peelable metal level 20 to form the structure as Fig. 9 G.Please refer to Fig. 9 H, also comprise knitting layer 90 in the part that removes in a suitable manner and expose, as shown by arrows in FIG., with electrically isolated die pad 42 and conductive connection pads 44.Come again, please refer to Fig. 9 I, Treatment of Metal Surface layer 80 is optionally set on the external connection pad 48 exposed.In an embodiment, please continue to refer to Fig. 9 I, an insulating barrier 91 can be set on the patterned metal layer 40 exposed, wherein form the mode of this insulating barrier 91 including but not limited to palm fibre oxidation (Brown Oxide) and melanism (Black Oxide) process.Between metal level and encapsulating material, form a knitting layer can increase engagement function between encapsulating material and metal level.
Continue above-mentioned, Figure 10 A to Figure 10 H is the schematic flow sheet of the four limit flat non-connection pin method for packing of further embodiment of this invention, and in the present embodiment, four limit flat non-connection pin method for packing comprise the following steps.Be with above-described embodiment difference, formed knitting layer under patterned metal layer.
First, as shown in Figure 10 A, provide an encapsulating carrier plate 10, wherein at least one surface of encapsulating carrier plate 10 arranges a peelable metal level 20.Then, as shown in Figure 10 B, form knitting layer 92 and, on peelable metal level 20, wherein descend knitting layer 92 to be that a patterning knitting layer makes the peelable metal level 20 of part be exposed to the outside, and lower knitting layer 92 is including but not limited to the stacking formation of at least one knitting layer.Come again, as illustrated in figure 10 c, form a patterned metal layer 40 ' on peelable metal level 20 and the lower knitting layer 92 of part.Described in above-described embodiment, patterned metal layer 40 ' comprises at least one die pad 42 ', multiple conductive connection pads 44 ', many circuits 46 ' and external connection pad 48 ', wherein partially patterned metal level 40 ' is arranged on lower knitting layer 92 completely, as die pad 42 '; Part patterned metal layer 40 ' part covers lower knitting layer 92 part and covers peelable metal level 20, as conductive connection pads 44 ', circuit 46 ' and external connection pad 48 '.Then, as shown in Figure 10 D, remove the lower knitting layer 92 of die pad 42 ' around below, as shown by arrows in FIG., make die pad 42 ' and the conductive connection pads 44 ' that is arranged at around it electrically isolated.
Then, a chip package step is carried out.As shown in figure 10e, a chip 50 ' is set in die pad 42 ', and utilizes a plurality of leads 60 ' to be electrically connected chip 50 ' and conductive connection pads 44 '; And utilize an encapsulating material 70 ' to encapsulate lead-in wire 60 ', chip 50 ', lower knitting layer 92, peelable metal level 20 and conductive connection pads 44 '.And selectivity above forms wire pad 82 ' to facilitate routing operation in conductive connection pads 44 '.Finally, as shown in Figure 10 E and Figure 10 F, after removing encapsulating carrier plate 10 and etching away peelable metal level 20, expose external connection pad 48 ' and lower knitting layer 92, wherein descend knitting layer 92 to have the effect of welding resisting layer herein.In an embodiment, as shown in figure 10g, Treatment of Metal Surface layer 80 ' is also optionally set on the external connection pad 48 ' exposed.Please refer to Figure 10 H, shown in above-described embodiment, also to comprise in formation one knitting layer 90 ' between patterned metal layer 40 ' and encapsulating material 70, to increase the engaging force of patterned metal layer 40 ' and encapsulating material 70 '.
Continue above-mentioned, Figure 11 A to Figure 11 I is the schematic flow sheet of the four limit flat non-connection pin method for packing of further embodiment of this invention, in order to manufacture the structure as shown in Fig. 7 A and Fig. 7 B.In the present embodiment, four limit flat non-connection pin method for packing comprise the following steps.
First, please refer to Figure 11 A, provide an encapsulating carrier plate 10, wherein at least one surface of encapsulating carrier plate 10 arranges a peelable metal level 20.Then, as shown in Figure 11 D, one first patterned metal layer 41 is formed on peelable metal level 20.And formed one first time patterned metal layer 411, to be stackingly arranged on the first patterned metal layer 41.Come again, please refer to Figure 11 E, form an insulating barrier 93 on peelable metal level 20 with on the first patterned metal layer 41, and expose first time patterned metal layer 411, and the first patterned metal layer 41 of each stacking setting is separated into first time patterned metal layer 411 the multiple external connection pad 48 be electrically insulated from each other by insulating barrier 93; Wherein insulating barrier 93 can utilize the mode of coating (printing) to be arranged on encapsulating carrier plate 10.In an embodiment, a surface treatment step can be carried out form rough surface to strengthen engaging with follow-up setting material thereon on patterned insulation layer 93, the method for dry type or wet type plasma treatment (plasmatreatment) wherein can be utilized.And, can be as shown in fig. 11f, selective use method for sputtering forms a metallic bond layer 94 and covers insulating barrier 93 with the first time exposed in pattern metal 411, to strengthen the engagement function of follow-up circuit and patterned insulation layer 93, wherein the material of metallic bond layer 94 is including but not limited to titanium or copper.
Continue above-mentioned, in this embodiment, the step forming external connection pad 48, as shown in Figure 11 B and Figure 11 C, comprising: arrange one first image transfer layer 33 on peelable metal level 20, and exposes the peelable metal level 20 of part; Then, formation first patterned metal layer 41 is electroplated on the peelable metal level 20 be exposed to the outside.Come again, as shown in Figure 11 C, arrange one first time image transfer layer 34 on the first image transfer layer 33 and exposed portion first patterned metal layer 41.Plating forms patterned metal layer 411 for the first time and is stacked on the first patterned metal layer 41; And remove the first image transfer layer 33 and first time image transfer layer 34, to form the structure as Figure 11 D.
Then, as shown in fig. 11g, form one second patterned metal layer, as patterned metal layer 40, above insulating barrier 93 with the external connection pad 48 be exposed to the outside, wherein patterned metal layer 40 comprises at least one die pad 42, multiple conductive connection pads 44 and many circuits 46, and patterned metal layer 40 and external connection pad 48 are electrically connected.Treatment of Metal Surface layer 82 is wherein optionally set in the conductive connection pads 44 for routing.In this embodiment, form the step of patterned metal layer 40 as shown in fig. 11g, comprise: arranging one second image transfer layer 35 on insulating barrier 93 exposes partial insulative layer 93 and external connection pad 48, and plating formation second patterned metal layer, as patterned metal layer 40, in insulating barrier 93 with on the external connection pad 48 be exposed to the outside; And remove the second image transfer layer 35.After removing the second image transfer layer 35, also comprise the metallic bond layer 94 removing with etching mode and be positioned at below the second image transfer layer 35, as figure, shown in 11H, make metallic bond layer 94 and the second patterned metal layer have identical patterning and configure.
Then, a chip package step is carried out.As shown in figure 111, a chip 50 is set in die pad 42; A plurality of leads 60 is utilized to be electrically connected chip 50 and conductive junction point 44; And utilize an encapsulating material 70 to encapsulate lead-in wire 60, chip 50 and conductive junction point 44.Wherein circuit 46 is electrically connected conductive connection pads 44 between two, and one of conductive connection pads 44 is electrically connected with chip 50 between two, and another and external connection pad 48 of conductive connection pads 44 are electrically connected between two.Finally, as shown in figure 111, remove encapsulating carrier plate 10 and etch away peelable metal level 20 again to expose external connection pad 48.
Figure 11 J, Figure 11 K, Figure 11 L illustrate the different application after removing support plate respectively, as shown in Figure 11 J, a Treatment of Metal Surface layer 80 can be formed on the external connection pad 48 exposed, after this and form one deck encapsulating material 73 in the insulating barrier 93 exposed, wherein encapsulating material 73 can be identical or different with the material of the encapsulating material 70 of coating chip 50.As shown in fig. 11k, after removing support plate, also comprise after removing part first patterned metal layer 41, then Treatment of Metal Surface layer 80 is optionally set on the external connection pad 48 exposed.And as shown in figure hl, the structural design of insulating barrier 93 and conductive connection pads 48, can be multiple-level stack and is be electrically connected between each layer conductive connection pads 48.
Continue above-mentioned, Figure 12 A to Figure 12 I is the schematic flow sheet of the four limit flat non-connection pin method for packing of further embodiment of this invention, in order to manufacture the structure as shown in Fig. 7 A and Fig. 7 B.In the present embodiment, four limit flat non-connection pin method for packing comprise the following steps.Be with above-described embodiment difference, Treatment of Metal Surface layer can make in different phase and be formed.
First, as illustrated in fig. 12, provide an encapsulating carrier plate 10, wherein at least one surface of encapsulating carrier plate 10 arranges a peelable metal level 20.Then, as shown in Figure 12 B, one first patterned metal layer 41 ' is formed on peelable metal level 20.The step wherein forming the first patterned metal layer 41 ' comprises: arrange one first image transfer layer 33 ' on peelable metal level 20, and exposes the peelable metal level 20 of part; Then, formation first patterned metal layer 41 ' is electroplated on the peelable metal level 20 be exposed to the outside; And remove the first image transfer layer 33 '.
Then, please refer to Figure 12 C, Figure 12 D, first form an insulating barrier 93 ' on peelable metal level 20, wherein insulating barrier 93 ' has multiple opening with exposed portion first patterned metal layer 41 '.Then, as Figure 12 E, forming a metallic bond layer 94 ', to cover insulating barrier 93 ' upper with reinforced insulation layer 93 ' and the bond arranging thereafter circuit thereon with the first patterned metal layer 41 ' exposed.Then, as shown in figure 12e, formation one first time patterned metal layer 411 ' is in the opening of insulating barrier 93 ', and be positioned on the first patterned metal layer 41 ' of exposing, wherein patterned metal layer 411 ' is stacking is for the first time arranged on the first patterned metal layer 41 ', and the first patterned metal layer 41 ' of stacking setting is separated into each other in electrically isolated a plurality of external connection pad 48 ' with first time patterned metal layer 411 ' by insulating barrier 93 '.
Come again, as shown in Figure 12 F, form one second patterned metal layer, as patterned metal layer 40 ', in insulating barrier 93 ' with on the external connection pad 48 ' exposed, wherein the second patterned metal layer 40 ' is comprise at least one die pad 42 ', multiple conductive connection pads 44 ' and plural circuit 46 ', and externally connection pad 48 ' and the second metal level 40 ' are electrically connected.In an embodiment, the step forming the second patterned metal layer 40 ', as shown in Figure 12 F and Figure 12 G, comprising: arrange one second image transfer layer 35 ' on part metals knitting layer 94 ', and the first time patterned metal layer 411 ' exposed; Plating formation second patterned metal layer 40 ' is in metallic bond layer 94 ' with first time patterned metal layer 411 '; Remove the second image transfer layer 35 '; And remove the metallic bond layer 94 ' of the second image transfer layer 35 ' below with etching mode, to form the structure as Figure 12 G.
Then, a chip package step is carried out.As shown in Figure 12 H, a chip 50 ' is set in die pad 42 '; A plurality of lead-in wires 60 ' are utilized to be electrically connected chip 50 ' and conductive junction point 44 '; And utilize an encapsulating material 70 ' to encapsulate lead-in wire 60 ', chip 50 ' and conductive junction point 44 '.Finally, as shown in Figure 12 H and 12I, remove encapsulating carrier plate 10 and expose external connection pad 48 '.In another embodiment, as shown in figure 12i, Treatment of Metal Surface layer 80 ' is more optionally set on the external connection pad 48 ' exposed.Forming the external connection pad of stack can make successive process grasp degree higher, and then improves process yields.In addition, a metallic bond layer can be formed to increase the engagement function of insulating material and metal level between metal level and insulating barrier.
Comprehensively above-mentioned, the present invention four limit flat non-connection pin method for packing has the encapsulating carrier plate of peelable metal level by using, and this peelable metal level can be utilized to carry out patterning as packaging body external connector thereafter, the diversity of overall package technique and encapsulating structure is provided.The process of upper and lower knitting layer then can utilize its material behavior to increase the structural strength between patterned metal layer and encapsulating material, strengthen its value of thrust, and avoid causing the short circuit because of circuit bridging in the process of SMT, guard metal layer is to avoid oxidation simultaneously.In addition, all technique all can use existing technology and equipment, does not increase cost and degree of difficulty.And the technique due to the peelable metal level of patterning uses image transfer technology or the micro-shadow technology of lithographic printing, therefore effectively can reach the structure of high density and thin space.The present invention, except can using prior art, also can be applicable to double-side technology.And the present invention is compared with generally using the method for packing of substrate, encapsulating carrier plate also can be selected recyclable or reuse material, therefore has lower cost and preferably advantage.In addition, this method can coordinate and utilizes electroplating technology to make special construction and the conductive connection pads structure of thin space.
Above-described embodiment is only that technological thought of the present invention and feature are described, its object is to enable person skilled in the art understand content of the present invention and implement according to this, when not limiting the scope of the claims of the present invention with it, namely every equalization done according to disclosed spirit changes or modifies, and must be encompassed in the scope of the claims of the present invention.

Claims (20)

1. four limit flat non-connection pin method for packing, is characterized in that, comprise the following step:
There is provided an encapsulating carrier plate, wherein at least one surface of this encapsulating carrier plate arranges a peelable metal level;
Form one first patterned metal layer on this peelable metal level;
Formed one first time patterned metal layer, be stackingly arranged on this first patterned metal layer;
Formed an insulating barrier on this peelable metal level with covering this first patterned metal layer, and expose this patterned metal layer first time, and this insulating barrier by this first patterned metal layer of each stacking setting and this first time patterned metal layer be separated into the multiple external connection pad be electrically insulated from each other;
Form one second patterned metal layer on this insulating barrier and those external connection pads, wherein this second patterned metal layer comprises at least one die pad, multiple conductive connection pads and multi-line, and these external connection pads and this second metal level are electrically connected;
Carry out a chip package step; And
Remove this encapsulating carrier plate and expose these external connection pads.
2. four limit flat non-connection pin method for packing according to claim 1, is characterized in that, this surface of this encapsulating carrier plate can be metal material or easy stripping metal surface.
3. four limit flat non-connection pin method for packing according to claim 1, it is characterized in that, the step forming these external connection pads comprises:
One first image transfer layer is set on this peelable metal level, and exposes this peelable metal level of part;
Plating forms this first patterned metal layer on this peelable metal level be exposed to the outside;
Arrange one first time image transfer layer on this first image transfer layer and this first patterned metal layer of exposed portion;
Plating forms this patterned metal layer first time and is stacked on this first patterned metal layer; And
Remove this first image transfer layer and this first time image transfer layer.
4. four limit flat non-connection pin method for packing according to claim 1, it is characterized in that, the step forming this insulating barrier comprises:
One insulating material to be arranged on this peelable metal level in the mode of coating and to cover this first patterned metal layer; And
Grind this insulating material to expose this patterned metal layer first time.
5. four limit flat non-connection pin method for packing according to claim 1, is characterized in that, also comprise formation one metallic bond layer and cover this insulating barrier with this exposed on patterned metal layer first time; And form this second patterned metal layer in this metallic bond layer.
6. four limit flat non-connection pin method for packing according to claim 5, it is characterized in that, this metallic bond layer has identical patterning with this second patterned metal layer and configures.
7. four limit flat non-connection pin method for packing according to claim 1, it is characterized in that, this chip package step comprises:
One chip is set in this die pad;
Multilead is utilized to be electrically connected this chip and these conductive junction points; And
An encapsulating material is utilized to encapsulate these lead-in wire, this chip and these conductive junction points.
8. four limit flat non-connection pin method for packing according to claim 7, is characterized in that, this encapsulating material utilizes the mode of injecting glue, wire mark, rotary coating to encapsulate these lead-in wire, this chip and these conductive junction points.
9. four limit flat non-connection pin method for packing according to claim 7, it is characterized in that, this circuit is electrically connected these conductive connection pads between two, and one of these conductive connection pads are electrically connected with this chip between two, and another and these external connection pad of these conductive connection pads is electrically connected between two.
10. four limit flat non-connection pin method for packing according to claim 1, is characterized in that, also comprise and arrange a Treatment of Metal Surface layer in the conductive connection pads for routing and/or these the external connection pads exposed.
11. four limit flat non-connection pin method for packing according to claim 1, it is characterized in that, the step forming this second patterned metal layer comprises:
Arranging one second image transfer layer on this insulating barrier exposes part this insulating barrier and these external connection pads;
Plating forms this second patterned metal layer in this insulating barrier with on these the external connection pads be exposed to the outside; And
Remove this second image transfer layer.
12. a kind of four limit flat non-connection pin method for packing, is characterized in that, comprise the following step:
There is provided an encapsulating carrier plate, wherein at least one surface of this encapsulating carrier plate arranges a peelable metal level;
Form one first patterned metal layer on this peelable metal level;
Form an insulating barrier on this encapsulating carrier plate, cover this peelable metal level, wherein this insulating barrier has multiple opening with this first patterned metal layer of exposed portion;
Form a metallic bond layer and cover this insulating barrier with on this first patterned metal layer exposed;
Formed one first time patterned metal layer in this metallic bond layer wherein this first time patterned metal layer to be stackingly arranged on this first patterned metal layer, and this insulating barrier by this first patterned metal layer of each stacking setting and this first time patterned metal layer be separated into the multiple external connection pad be electrically insulated from each other;
Formed one second patterned metal layer in this first time patterned metal layer and this metallic bond layer of part on, wherein this second patterned metal layer comprises at least one die pad, multiple conductive connection pads and multi-line, and these external connection pads and this second metal level are electrically connected;
Carry out a chip package step; And
Remove this encapsulating carrier plate and expose these external connection pads.
13., according to four limit flat non-connection pin method for packing described in claim 12, is characterized in that, this surface of this encapsulating carrier plate can be metal material or easily stripping metal is surperficial.
14. according to four limit flat non-connection pin method for packing described in claim 12, and it is characterized in that, the step forming this insulating barrier comprises:
One insulating material to be arranged on this peelable metal level in the mode of coating and to cover this first patterned metal layer; And
Bore mode is utilized on this insulating material, to form multiple opening to expose this first patterned metal layer of part.
15. four limit flat non-connection pin method for packing according to claim 12, it is characterized in that, this metallic bond layer utilizes method for sputtering to be formed.
16. four limit flat non-connection pin method for packing according to claim 12, it is characterized in that, this chip package step comprises:
One chip is set in this die pad;
Multilead is utilized to be electrically connected this chip and these conductive junction points; And
An encapsulating material is utilized to encapsulate these lead-in wire, this chip and these conductive junction points.
17., according to four limit flat non-connection pin method for packing described in claim 16, is characterized in that, this encapsulating material utilizes the mode of injecting glue, wire mark, rotary coating to encapsulate these lead-in wire, this chip and these conductive junction points.
18. according to four limit flat non-connection pin method for packing described in claim 16, it is characterized in that, this circuit is electrically connected these conductive connection pads between two, and one of these conductive connection pads are electrically connected with this chip between two, and another and these external connection pad of these conductive connection pads is electrically connected between two.
19. four limit flat non-connection pin method for packing according to claim 12, also comprise and arrange a Treatment of Metal Surface layer in the conductive connection pads for routing and/or these the external connection pads exposed.
20. four limit flat non-connection pin method for packing according to claim 12, it is characterized in that, the step forming this second patterned metal layer comprises:
One second image transfer layer is set in this metallic bond layer of part, and this patterned metal layer exposed first time;
Plating forms this second patterned metal layer in this metallic bond layer with on this for the first time patterned metal layer;
Remove this second image transfer layer; And
This metallic bond layer below this second image transfer layer is removed with etching mode.
CN201510049628.5A 2010-09-01 2010-12-29 Quad-flat no-lead packaging method Pending CN104658919A (en)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107507781A (en) * 2017-08-30 2017-12-22 深圳中科四合科技有限公司 A kind of preparation method of chip-packaging structure
CN107564876A (en) * 2017-08-30 2018-01-09 深圳中科四合科技有限公司 A kind of chip-packaging structure
CN108735764A (en) * 2017-04-18 2018-11-02 金佶科技股份有限公司 Taken module and its manufacturing method
CN110581075A (en) * 2018-06-08 2019-12-17 欣兴电子股份有限公司 Circuit carrier plate structure and manufacturing method thereof
US10888001B2 (en) 2018-06-08 2021-01-05 Unimicron Technology Corp. Circuit carrier board structure and manufacturing method thereof

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI492358B (en) * 2012-09-26 2015-07-11 矽品精密工業股份有限公司 Semiconductor package and method of forming the same
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TWI622151B (en) * 2016-12-07 2018-04-21 矽品精密工業股份有限公司 Carrier substrate for semiconductor packaging and package structure thereof, and method for fabricating semiconductor package
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1617332A (en) * 2003-11-07 2005-05-18 株式会社巴川制纸所 Adhesive thin sheet for producing semiconductor device, semiconductor device and its producing method
CN1659698A (en) * 2002-06-06 2005-08-24 皇家飞利浦电子股份有限公司 Quad flat non-leaded package comprising a semiconductor device
US20080135990A1 (en) * 2006-12-07 2008-06-12 Texas Instruments Incorporated Stress-improved flip-chip semiconductor device having half-etched leadframe
US20090001603A1 (en) * 2007-06-30 2009-01-01 Chien-Wei Chang High-Density Fine Line Structure And Method Of Manufacturing The Same

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4251807B2 (en) * 2001-12-17 2009-04-08 株式会社巴川製紙所 Adhesive sheet for semiconductor device manufacturing
JP2005531137A (en) * 2002-04-29 2005-10-13 アドヴァンスト インターコネクト テクノロジーズ リミテッド Partially patterned leadframe and method for its manufacture and use in semiconductor packaging
JPWO2004075293A1 (en) * 2003-02-19 2006-06-01 日立化成工業株式会社 Adhesive film for semiconductor, metal plate with adhesive film using the same, wiring circuit with adhesive film, semiconductor device, and method for manufacturing semiconductor device
US20100044850A1 (en) * 2008-08-21 2010-02-25 Advanced Semiconductor Engineering, Inc. Advanced quad flat non-leaded package structure and manufacturing method thereof
TWI372454B (en) * 2008-12-09 2012-09-11 Advanced Semiconductor Eng Quad flat non-leaded package and manufacturing method thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1659698A (en) * 2002-06-06 2005-08-24 皇家飞利浦电子股份有限公司 Quad flat non-leaded package comprising a semiconductor device
CN1617332A (en) * 2003-11-07 2005-05-18 株式会社巴川制纸所 Adhesive thin sheet for producing semiconductor device, semiconductor device and its producing method
US20080135990A1 (en) * 2006-12-07 2008-06-12 Texas Instruments Incorporated Stress-improved flip-chip semiconductor device having half-etched leadframe
US20090001603A1 (en) * 2007-06-30 2009-01-01 Chien-Wei Chang High-Density Fine Line Structure And Method Of Manufacturing The Same

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108735764A (en) * 2017-04-18 2018-11-02 金佶科技股份有限公司 Taken module and its manufacturing method
CN107507781A (en) * 2017-08-30 2017-12-22 深圳中科四合科技有限公司 A kind of preparation method of chip-packaging structure
CN107564876A (en) * 2017-08-30 2018-01-09 深圳中科四合科技有限公司 A kind of chip-packaging structure
CN107564876B (en) * 2017-08-30 2019-09-27 深圳中科四合科技有限公司 A kind of chip-packaging structure
CN107507781B (en) * 2017-08-30 2019-09-27 深圳中科四合科技有限公司 A kind of preparation method of chip-packaging structure
CN110581075A (en) * 2018-06-08 2019-12-17 欣兴电子股份有限公司 Circuit carrier plate structure and manufacturing method thereof
US10888001B2 (en) 2018-06-08 2021-01-05 Unimicron Technology Corp. Circuit carrier board structure and manufacturing method thereof

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