CN103474358A - Multi-circle QFN package lead frame manufacturing method - Google Patents
Multi-circle QFN package lead frame manufacturing method Download PDFInfo
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- CN103474358A CN103474358A CN2013104551827A CN201310455182A CN103474358A CN 103474358 A CN103474358 A CN 103474358A CN 2013104551827 A CN2013104551827 A CN 2013104551827A CN 201310455182 A CN201310455182 A CN 201310455182A CN 103474358 A CN103474358 A CN 103474358A
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- packaged chip
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
The invention relates to a multi-circle QFN package lead frame manufacturing method, and belongs to the technical field of semi-conductor packaging. According to the technical scheme, the multi-circle QFN package lead frame manufacturing method comprises the following steps that 1 a substrate is provided and needed lead foot graphs are formed on the front face of the substrate; 2 multiple circles of needed outer lead feet are formed on the substrate by the utilization of the lead foot graphs on the substrate; 3 a needed packaging chip is arranged on the substrate and the packaging chip is electrically connected with the outer lead feet on the substrate through connecting lines; 4 plastic packaging is conducted on the packaging chip on the substrate to obtain a plastic packaging body, and the plastic packaging body enables the packaging chip, the connecting lines and the outer lead feet to be pressed on the substrate in a covering mode; 5 etching is conducted on the back face of the substrate so as to separate the packaging chip from the outer lead feet. According to the multi-circle QFN package lead frame manufacturing method, the structure is compact, the technology is simple and convenient to implement, the compatibility is good, the cost is low, and the machining precision and the machining efficiency are high.
Description
Technical field
The present invention relates to a kind of preparation method, especially a kind of multi-turn QFN encapsulating lead preparation method, belong to the technical field of semiconductor packages.
Background technology
Multi-turn QFN(Quad Flat No-lead Package) be a kind of new packing forms that immediate development is got up, its basic structure is similar to the QFN encapsulation, different is that it has how exclusive pin, between how exclusive pin, can be staggered, to increase the density of outer pin.Existing multi-turn QFN all adopts pressing to prepare lead frame, needs expensive mould and equipment, complicated process of preparation, and very flexible, cost is high, and machining accuracy is low, is difficult to meet user demand.
Summary of the invention
The objective of the invention is to overcome the deficiencies in the prior art, a kind of multi-turn QFN encapsulating lead preparation method is provided, its compact conformation, technique is simple and convenient, and compatible good, cost is low, and machining accuracy and working (machining) efficiency are high.
According to technical scheme provided by the invention, described multi-turn QFN encapsulating lead preparation method, described encapsulating lead preparation method comprises the steps:
A kind of multi-turn QFN encapsulating lead preparation method is characterized in that described encapsulating lead preparation method comprises the steps:
A, provide substrate, and arrange on the front of described substrate and form required pin figure;
B, utilize pin figure on substrate, generate pin outside required multi-turn on substrate;
C, required packaged chip is set on aforesaid substrate, and described packaged chip is electrically connected to the outer pin on substrate by connecting line;
D, the packaged chip of aforesaid substrate top is carried out to plastic packaging, obtains plastic-sealed body, described plastic-sealed body by packaged chip, connecting line and outer pin gland on substrate;
E, etching is carried out in the back side of aforesaid substrate, separate with the outer pin by packaged chip.
In described step a, comprise the steps:
A1, provide substrate, and on the front of described substrate, required dry film is set;
A2, the dry film on substrate is exposed and developed, to obtain the pin isolation pattern on substrate; The front of substrate forms required pin figure by the pin isolation pattern.
The material of described substrate comprises copper.
In described step b, the outer pin of described multi-turn obtains by electroplating the electroplated metal layer of desired thickness in the pin figure on substrate and on described electroplated metal layer, surface-treated layer being set.
In described step e, after the back-etching to substrate, outer pin processing layer is set on the surface of pin outside.
The material of described electroplated metal layer comprises copper, and the material of surface-treated layer comprises tin, Ni or Au.
Advantage of the present invention: the preparation technology of lead frame and substrate preparation technology are merged, with substrate process, carry out the needed lead frame of production multi-turn QFN; Adopt semi-additive process to prepare the inside and outside pin of chip, improved the preparation precision of outer pin, can prepare the outer pin array of thin space, guarantee the precision of outer pin size simultaneously, technological flexibility is high, can change at any time according to demand the arrangement mode of outer pin, and avoiding needs to change grinding tool in traditional punch forming, cycle is long, the problem that cost is high.A plurality of lead frames of moulding simultaneously once, efficiency is high, adapts to automated production and goods good uniformity.By to substrate, etching realizes the separation of outer pin not needing grinding to realize the separation of outer pin, reduced the destruction to encapsulating structure, guaranteed the planarization of outer pin face.Very thin (100 μ m are thick or less) and the thickness that lead frame can be done are adjustable, meet compact development trend.
The accompanying drawing explanation
The cutaway view that Fig. 1 ~ Fig. 8 is the concrete implementing process of the present invention, wherein
The cutaway view that Fig. 1 is substrate of the present invention.
Fig. 2 is the cutaway view arranged on substrate of the present invention after dry film.
Fig. 3 is the cutaway view after the present invention is exposed to dry film.
Fig. 4 is the cutaway view after the present invention is developed.
Fig. 5 is that the present invention electroplates the cutaway view obtained after outer pin.
Fig. 6 is the cutaway view after the present invention carries out paster and routing.
Fig. 7 is the cutaway view after the present invention carries out plastic packaging.
Fig. 8 is that the present invention carries out etching to substrate, makes the cutaway view after outer pin separates.
The upward view that Fig. 9 is Fig. 8.
Description of reference numerals: 1-substrate, 2-dry film, 3-pin isolation pattern, 4-mask plate, 5-window, 6-electroplated metal layer, 7-surface-treated layer, 8-packaged chip, 9-connecting line, 10-plastic-sealed body, the outer pin processing layer of 11-, 12-pin figure, the outer pin of 13-and 14-chip are installed figure.
Embodiment
Below in conjunction with concrete drawings and Examples, the invention will be further described.
As shown in Fig. 1 ~ Fig. 9: in order to prepare easily multi-turn QFN encapsulating lead, cut down finished cost, improve production precision and efficiency, encapsulating lead preparation method of the present invention comprises the steps:
A, provide substrate 1, and arrange on the front of described substrate 1 and form required pin figure 12;
As shown in Fig. 1 ~ Fig. 4: in the embodiment of the present invention, the material of substrate 1 comprises copper, in order to obtain pin figure 12 on substrate 1, in described step a, comprises the steps:
A1, provide substrate 1, and required dry film 2 is set on the front of described substrate 1;
Arrange on substrate 1 that the type of dry film 2 can decide according to the thickness of desired outer pin-pitch, outer pin size and required substrate 1, as depicted in figs. 1 and 2.
A2, the dry film 2 on substrate 1 is exposed and developed, to obtain pin isolation pattern 3 on substrate 1; The front of substrate 1 forms required pin figure 12 by pin isolation pattern 3.
As shown in Figure 3 and Figure 4: when dry film 2 is exposed, utilize 5 pairs of dry films 2 of mask plate 4 and the window on mask plate 4 to be exposed, perhaps adopt the LDI technology directly to be exposed on dry film 2, after dry film 2 is developed, obtain pin isolation pattern 3 on the front of substrate 1.In the embodiment of the present invention, by pin isolation pattern 3, can access pinouts shape 12 and chip installation figure 14, chip is installed the center that figure 14 is positioned at substrate 1, and pin figure 12 is positioned at the periphery that chip is installed figure 14.In the specific implementation, can be as required, the periphery that figure 14 is installed at chip arranges multi-circle pin figure 12.In order to improve the intensity of substrate 1, reduce the buckling deformation of substrate, in the embodiment of the present invention, PI film (polyimide film) can be set on the surface of substrate 1.
B, utilize pin figure 12 on substrate 1, generate pin 13 outside required multi-turn on substrate 1;
As shown in Figure 5: the outer pin 13 of described multi-turn obtains by electroplated metal layer 6 being set on substrate 1 and on described electroplated metal layer 6, surface-treated layer 7 being set.In the embodiment of the present invention, the material of electroplated metal layer 6 is also copper, and the material of surface-treated layer 7 is tin, Ni, Au etc.; Utilize pin isolation pattern 3 to obtain electroplated metal layer 6 and surface-treated layer 7 at pin figure 12 and 14 plating of chip installation figure.In the embodiment of the present invention, the electroplated metal layer 6 in pin figure 12 and corresponding surface-treated layer 7 can form outer pin 13, and the thickness of electroplated metal layer 6 can be arranged as required.
C, required packaged chip 8 is set on aforesaid substrate 1, and described packaged chip 8 is electrically connected to the outer pin 13 on substrate 1 by connecting line 9;
As shown in Figure 6: remove the pin isolation pattern 3 on aforesaid substrate 1, then electroplated metal layer 6 and the surface-treated layer 7 in chip is installed figure 14 arranges packaged chip 8, so that packaged chip 8 is positioned at the central area that chip is installed figure 14; The type of packaged chip 8 can be selected as required, and packaged chip 8 is electrically connected to the outer pin 13 of the multi-turn on substrate 1 by connecting line 9.
D, the packaged chip 8 of aforesaid substrate 1 top is carried out to plastic packaging, obtains plastic-sealed body 10, on described plastic-sealed body 10 by packaged chip 8, connecting line 9 and outer pin 13 glands on substrate 1;
As shown in Figure 7: utilize resin carry out plastic packaging and be cured the packaged chip 8 and the connecting line 8 that fix, obtain plastic-sealed body 10; Plastic-sealed body 10 glands packaged chip 8, outer pin 13 and outside in gap between pin 13, so that packaged chip 8 and connecting line 9 are protected.
E, etching is carried out in the back side of aforesaid substrate 1, separate from substrate 1 with the outer pin 13 by packaged chip 8 peripheries.
As shown in Figure 8: after above-mentioned plastic packaging, substrate 1 is carried out to whole etchings, so that outer pin 13 is separated.After substrate 1 is carried out to etching, outer pin 13 links together by plastic-sealed body 10 and packaged chip 8.Further, the surface of pin 13 arranges outer pin processing layer 11 outside, by the protection of outer pin processing layer 11 convenient outer pins 13 and the requirement that meets the next stage interconnection.The material of outer pin processing layer 11 is generally tin or Ni, Au etc., according to concrete technology, requires to determine.When the back side of aforesaid substrate 1 is provided with the PI support membrane, when carrying out etching, should first removes the PI film at substrate 1 back side, and then carry out etching.As shown in Figure 9: for forming the bottom view of multi-turn QFN encapsulating lead, there is shown the schematic diagram that packaged chip 8 outer rings arrange the outer pin 13 of three circles.
The preparation technology of lead frame and substrate preparation technology are merged in the present invention, with substrate process, carry out the needed lead frame of production multi-turn QFN; Adopt semi-additive process to prepare the inside and outside pin of chip, improved the preparation precision of outer pin, can prepare the outer pin array of thin space, guarantee the precision of outer pin size simultaneously, technological flexibility is high, can change at any time according to demand the arrangement mode of outer pin, and avoiding needs to change grinding tool in traditional punch forming, cycle is long, the problem that cost is high.A plurality of lead frames of moulding simultaneously once, efficiency is high.By to substrate, 1 etching realizes the separation of outer pin 13, do not need grinding to realize the separation of outer pin 13, the less destruction to encapsulating structure, guaranteed the planarization of machined surface.Very thin (100 μ m are thick or less) and the thickness that lead frame can be done are adjustable, meet compact development trend.
Claims (6)
1. a multi-turn QFN encapsulating lead preparation method, is characterized in that, described encapsulating lead preparation method comprises the steps:
(a), substrate (1) is provided, and arrange on the front of described substrate (1) and form required pin figure (12);
(b), utilize pin figure (12) on substrate (1), pin (13) outside substrate (1) is gone up the required multi-turn of generation;
(c), required packaged chip (8) is set on aforesaid substrate (1), and described packaged chip (8) is electrically connected to the outer pin (13) on substrate (1) by connecting line (9);
(d), the packaged chip (8) of aforesaid substrate (1) top is carried out to plastic packaging, obtain plastic-sealed body (10), described plastic-sealed body (10) by packaged chip (8), connecting line (9) and outer pin (13) gland on substrate (1);
(e), etching is carried out in the back side of aforesaid substrate (1), with the outer pin (13) by packaged chip (8), separate.
2. multi-turn QFN encapsulating lead preparation method according to claim 1, is characterized in that, in described step (a), comprises the steps:
(a1), substrate (1) is provided, and required dry film (2) is set on the front of described substrate (1);
(a2), the dry film (2) on substrate (1) is exposed and developed, to obtain pin isolation pattern (3) on substrate (1); The front of substrate (1) forms required pin figure (12) by pin isolation pattern (3).
3. multi-turn QFN encapsulating lead preparation method according to claim 1 and 2, it is characterized in that: the material of described substrate (1) comprises copper.
4. multi-turn QFN encapsulating lead preparation method according to claim 1, it is characterized in that, in described step (b), the outer pin (13) of described multi-turn obtains by electroplating the electroplated metal layer (6) of desired thickness in the pin figure (12) on substrate (1) and surface-treated layer (7) being set on described electroplated metal layer (6).
5. multi-turn QFN encapsulating lead preparation method according to claim 1, is characterized in that, in described step (e), after the back-etching to substrate (1), on the surface of pin (13), outer pin processing layer (11) is set outside.
6. multi-turn QFN encapsulating lead preparation method according to claim 4, it is characterized in that: the material of described electroplated metal layer (6) comprises copper, the material of surface-treated layer (7) comprises tin, Ni or Au.
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| CN2013104551827A CN103474358A (en) | 2013-09-29 | 2013-09-29 | Multi-circle QFN package lead frame manufacturing method |
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| CN2013104551827A CN103474358A (en) | 2013-09-29 | 2013-09-29 | Multi-circle QFN package lead frame manufacturing method |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104465585A (en) * | 2014-12-26 | 2015-03-25 | 江苏长电科技股份有限公司 | Wafer level package structure and technological method thereof |
| CN105530761A (en) * | 2014-09-29 | 2016-04-27 | 深南电路有限公司 | Circuit board manufacturing method |
| CN110444516A (en) * | 2019-08-07 | 2019-11-12 | 华羿微电子股份有限公司 | A kind of semiconductor package and preparation method thereof of no lead frame |
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Application publication date: 20131225 |