CN103489794B - Improve the method for lead frame hardness in QFN package lead frame preparation technology - Google Patents
Improve the method for lead frame hardness in QFN package lead frame preparation technology Download PDFInfo
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- CN103489794B CN103489794B CN201310456986.9A CN201310456986A CN103489794B CN 103489794 B CN103489794 B CN 103489794B CN 201310456986 A CN201310456986 A CN 201310456986A CN 103489794 B CN103489794 B CN 103489794B
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- 238000000034 method Methods 0.000 title claims abstract description 32
- 238000002360 preparation method Methods 0.000 title claims abstract description 22
- 238000005516 engineering process Methods 0.000 title claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 115
- 239000002184 metal Substances 0.000 claims abstract description 73
- 229910052751 metal Inorganic materials 0.000 claims abstract description 73
- 239000004033 plastic Substances 0.000 claims abstract description 10
- 238000004806 packaging method and process Methods 0.000 claims abstract description 8
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 5
- 238000002955 isolation Methods 0.000 claims description 22
- 239000000463 material Substances 0.000 claims description 9
- 210000004907 gland Anatomy 0.000 claims description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 238000003825 pressing Methods 0.000 claims description 3
- 238000007747 plating Methods 0.000 claims 1
- 238000003754 machining Methods 0.000 abstract description 5
- 238000000227 grinding Methods 0.000 description 11
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000004743 Polypropylene Substances 0.000 description 3
- 230000006378 damage Effects 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000000654 additive Substances 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- -1 polypropylene Polymers 0.000 description 1
- 229920001155 polypropylene Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4842—Mechanical treatment, e.g. punching, cutting, deforming, cold welding
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
The present invention relates to a kind of method improving lead frame hardness in QFN package lead frame preparation technology, it comprises the steps: a, provides substrate and metal connecting layer, is provided with isolated interstice in metal connecting layer; B, supporting medium layer is set on the front of aforesaid substrate; C, mask layer is set at the back side of substrate, and obtains the etched hole of through described mask layer; D, above-mentioned etched hole is utilized to etch substrate, the sorting hole needed for formation; E, the mask layer removed on substrate, and first surface processing layer is set at the back side of substrate; F, arrange packaged chip in the center of substrate back, packaged chip is electrically connected by the pin of connecting line with packaged chip outer ring; G, plastic packaging is carried out to packaged chip, obtain plastic-sealed body; H, carry out thinning to the supporting medium layer of substrate front side, until the surface exposure of metal connecting layer.The present invention can improve the hardness of lead frame, and technique is simple and convenient, and cost is low, machining accuracy and working (machining) efficiency high.
Description
Technical field
The present invention relates to a kind of preparation method, especially a kind of method improving lead frame hardness in QFN package lead frame preparation technology, belongs to the technical field of semiconductor packages.
Background technology
Multi-turn QFN(QuadFlatNo-leadPackage) be a kind of new packing forms that immediate development is got up, its basic structure encapsulates similar to QFN, arranges pin unlike it more, can be staggered, to increase the density of pin between many row's pins.Existing multi-turn QFN complicated process of preparation, cost is high, and machining accuracy is low; In addition, the hardness angle of QFN package lead frame, easily causes the bending of lead frame, causes the unreliability that QFN encapsulates.
Summary of the invention
The object of the invention is to overcome the deficiencies in the prior art, a kind of method improving negative line framework hardness in QFN package lead frame preparation technology is provided, it can improve the hardness of lead frame, reduce the buckling deformation of lead frame substrate, be convenient to the automation of chip package, technique is simple and convenient, compatible good, cost is low, machining accuracy and working (machining) efficiency high.
According to technical scheme provided by the invention, the method for lead frame hardness in described raising QFN package lead frame preparation technology, the method for described raising lead frame hardness comprises the steps:
A, provide substrate, and the metal connecting layer be electrically connected with described substrate is set on the front of substrate, in described metal connecting layer, be provided with the isolated interstice of through metal connecting layer;
B, on the front of aforesaid substrate pressing supporting medium layer, described supporting medium layer to cover in metal connecting layer and is filled in isolated interstice;
C, mask layer is set at the back side of substrate, optionally shelters and etch described mask layer, obtain the etched hole of through described mask layer;
D, above-mentioned etched hole is utilized to etch substrate, to make etched hole through substrate, the sorting hole needed for formation;
E, the mask layer removed on substrate, and first surface processing layer is set at the back side of substrate; First surface processing layer and corresponding substrate, metal connecting layer form multi-circle pin by sorting hole;
F, arrange packaged chip in the center at the aforesaid substrate back side, described packaged chip is electrically connected by the pin of connecting line with described packaged chip outer ring;
G, plastic packaging is carried out to above-mentioned packaged chip, obtain plastic-sealed body; Described plastic-sealed body gland on packaged chip, first surface processing layer, and is filled in sorting hole;
H, carry out thinning to the supporting medium layer in aforesaid substrate front, until the surface exposure of metal connecting layer.
In described step a, comprise the steps:
A1, provide substrate, and required dry film is set on the front of described substrate;
A2, the dry film on substrate exposed and develops, to obtain pin isolation pattern on substrate;
A3, utilize described pin isolation pattern on substrate, electroplate required metal connecting layer; Remove described pin isolation pattern, to obtain the isolated interstice of through described metal connecting layer.
The material of described substrate and the material of metal connecting layer include copper.The material of described supporting medium layer comprises PP.
A similar technical scheme, improve the method for lead frame hardness in QFN package lead frame preparation technology, the method for described raising lead frame hardness comprises the steps:
S1, provide substrate, and the metal connecting layer be electrically connected with described substrate is set on the front of substrate, in described metal connecting layer, be provided with the isolated interstice of some through metal connecting layer;
S2, on the front of aforesaid substrate, arrange supporting medium layer, described supporting medium layer to cover in metal connecting layer and is filled in isolated interstice;
S3, grinding is carried out to the supporting medium layer in above-mentioned metal connecting layer, to make the surface exposure of metal connecting layer; And second surface processing layer is set on the surface that metal connecting layer is exposed, the metal connecting layer below second surface processing layer and described second surface processing layer forms the pin of multi-turn by the supporting medium layer in isolated interstice;
S4, above aforesaid substrate, arrange packaged chip, described packaged chip is positioned at the central area of substrate, and packaged chip is electrically connected by the pin of connecting line with described packaged chip outer ring;
S5, carry out plastic packaging to above-mentioned packaged chip, obtain plastic-sealed body in surface, described plastic-sealed body gland is in second surface processing layer, packaged chip and supporting medium layer;
S6, the back side of substrate to be etched, with the surface exposure making metal connecting layer be connected with substrate, pin is separated from each other;
S7, arrange the 3rd surface-treated layer on the surface that metal connecting layer is exposed, described 3rd processing layer is electrically connected with metal connecting layer.
In described step s1, comprise the steps:
S11, provide substrate, and required dry film is set on the front of described substrate;
S12, the dry film on substrate exposed and develops, to obtain pin isolation pattern on substrate;
S13, utilize described pin isolation pattern on substrate, electroplate required metal connecting layer; Remove described pin isolation pattern, to obtain the isolated interstice of through described metal connecting layer.
In described step s3, the method for supporting medium layer being carried out to grinding comprises plasma etching.
Advantage of the present invention: the preparation technology of lead frame and substrate preparation technology are merged, use substrate process carrys out the lead frame required for production multi-turn QFN; Subtractive process is adopted to prepare the inside and outside pin of chip, improve the preparation precision of pin, the pin array of more thin space can be prepared, ensure the precision of pin size simultaneously, technological flexibility is high, can change the arrangement mode of pin according to demand at any time, and avoiding needs in traditional punch forming to change grinding tool, cycle is long, the problem that cost is high.Once plastic multiple lead frame, efficiency is high.In the process preparing lead frame, improved the hardness of lead frame by supporting medium layer, not easily bend, the destruction to encapsulating structure can be reduced by corresponding processing step, ensure that the planarization of machined surface, easily be automated production.Very thin (100 μm thick or less) that lead frame can be done and pin thickness is adjustable, meets compact development trend.
Accompanying drawing explanation
Fig. 1 ~ Fig. 9 is the concrete implementing process cutaway view of the embodiment of the present invention 1, wherein
Fig. 1 is the cutaway view of substrate of the present invention.
Fig. 2 is the cutaway view after substrate of the present invention being arranged dry film.
Fig. 3 is the cutaway view after the present invention exposes dry film.
Fig. 4 is the cutaway view after the present invention develops.
Fig. 5 is the cutaway view after the present invention obtains metal connecting layer on substrate.
Fig. 6 is that the present invention is supported the cutaway view after dielectric layer.
Fig. 7 is that the present invention obtains the cutaway view after etched hole by mask layer.
Fig. 8 is the cutaway view after the present invention obtains first surface processing layer.
Fig. 9 be plastic packaging of the present invention and thinning to supporting medium layer after cutaway view.
Figure 10 ~ Figure 13 is the concrete implementing process cutaway view of the embodiment of the present invention 2, wherein
Figure 10 is that the present invention is supported the cutaway view after dielectric layer.
Figure 11 is the cutaway view after the present invention obtains second surface processing layer.
Figure 12 is the cutaway view after plastic packaging of the present invention.
Figure 13 is the cutaway view after the present invention obtains the 3rd surface-treated layer.
Figure 14 is the bottom view that the present invention forms lead frame.
Description of reference numerals: 1-substrate, 2-dry film, 3-pin isolation pattern, 4-mask plate, 5-window, 6-metal connecting layer, 7-isolated interstice, 8-supporting medium layer, 9-mask layer, 10-etched hole, 11-first surface processing layer, 12-packaged chip, 13-connecting line, 14-plastic-sealed body, 15-second surface processing layer, 16-the 3rd surface-treated layer, 17-pin and 18-sorting hole.
Embodiment
Below in conjunction with concrete drawings and Examples, the invention will be further described.
In order to improve the hardness of lead frame in multi-circle QFN package lead frame preparation technology, the present invention is described by embodiment 1 and implementation column 2, particularly:
Embodiment 1
As shown in Fig. 1 ~ Fig. 9: a kind of method improving lead frame hardness in QFN package lead frame preparation technology, the method for described raising lead frame hardness comprises the steps:
A, provide substrate 1, and the metal connecting layer 6 be electrically connected with described substrate 1 is set on the front of substrate 1, in described metal connecting layer 6, be provided with the isolated interstice 7 of some through metal connecting layer 6;
As shown in Fig. 1 ~ Fig. 4: in the embodiment of the present invention, the material of substrate 1 and the material of metal connecting layer 6 comprise copper, and in order to obtain metal connecting layer 6 and isolated interstice 7 in the front of substrate 1, described step a comprises the steps:
A1, provide substrate 1, and required dry film 2 is set on the front of described substrate 1;
Type substrate 1 being arranged dry film 2 can decide according to the thickness of required pin-pitch, pin size and required substrate 1, as depicted in figs. 1 and 2.
A2, the dry film 2 on substrate 1 is exposed and developed, to obtain pin isolation pattern 3 on substrate 1;
As shown in Figure 3 and Figure 4: when exposing dry film 2, utilize mask plate 4 and the 5 pairs of dry films 2 of the window on mask plate 4 to expose, after dry film 2 is developed, the front of substrate 1 obtains pin isolation pattern 3.In the embodiment of the present invention, pin isolation pattern 3 comprises spacing block and by the region outside spacing block;
A3, described pin isolation pattern 3 is utilized to electroplate required metal connecting layer 6 on substrate 1; Remove described pin isolation pattern 3, to obtain the isolated interstice 7 of through described metal connecting layer 6.Remove described pin isolation pattern 3 and refer to the spacing block removing pin isolation pattern 3, electroplated metal layer 6 is positioned on the region outside spacing block, can obtain isolated interstice 7, the through metal connecting layer 6 of isolated interstice 7 after removing spacing block.
As shown in Figure 5: utilize pin isolation pattern 3 plated metal articulamentum 6, when after removal figure spacing block 3, the isolated interstice 7 of through metal connecting layer 6 can just be obtained.
B, on the front of aforesaid substrate 1 pressing supporting medium layer 8, described supporting medium layer 8 to cover in metal connecting layer 6 and is filled in isolated interstice 7;
As shown in Figure 6: the material of described supporting medium layer 8 comprises PP(polypropylene), the hardness forming lead frame can be improved by supporting medium layer 8.
C, mask layer 9 is set at the back side of substrate 1, optionally shelters and etch described mask layer 9, obtain the etched hole 10 of through described mask layer 9;
As shown in Figure 7: arrange mask layer 9 as required, obtain etched hole 10 after etching to mask layer 9, described etched hole 10 extends to the back side of substrate 1 from the upper surface of mask layer 9.
D, above-mentioned etched hole 10 pairs of substrates 1 are utilized to etch, to make etched hole 10 through substrate 1, the sorting hole 18 needed for formation;
Substrate 1 corresponding immediately below described etched hole 10 can be etched by etched hole 10, form sorting hole 18, described sorting hole 18 is connected with aforementioned isolated interstice 7 of having filled supporting medium layer 8, and the axis of the axis of isolated interstice 7 and sorting hole 18 is located along the same line, by sorting hole 18 and isolated interstice 7, metal connecting layer 6 and substrate 1 can be divided into some independently parts.
E, the mask layer 9 removed on substrate 1, and first surface processing layer 11 is set at the back side of substrate 1; First surface processing layer 11 and corresponding substrate 1, metal connecting layer 6 form multi-circle pin 17 by sorting hole 18;
As shown in Figure 8: first surface processing layer 11 is set by substrate 1 back side substrate 1 can be made conveniently to be electrically connected, first surface processing layer 11 be separated rear corresponding substrate 1 above by sorting hole 18, metal connecting layer 6 can form pin 17, and the structure of described pin 17 in multi-turn.The pin 17 of multi-turn is split by sorting hole 18
F, arrange packaged chip 12 in the center at aforesaid substrate 1 back side, described packaged chip 12 is electrically connected by the pin 17 of connecting line 13 with described packaged chip 12 outer ring;
In the embodiment of the present invention, packaged chip 12 is positioned at the center at substrate 1 back side, and namely packaged chip 12 is positioned at the center of multi-circle pin 17, and packaged chip 12 is electrically connected with pin 17 by connecting line 13.
G, plastic packaging is carried out to above-mentioned packaged chip 12, obtain plastic-sealed body 14; Described plastic-sealed body 14 gland on packaged chip 12, first surface processing layer 11, and is filled in sorting hole 18;
Can be protected packaged chip 12 and connecting line 13 by plastic-sealed body 14, make packaged chip 12, connecting line 13 and leg 17 be interconnected integral simultaneously, guarantee the reliability encapsulated.Plastic-sealed body 14 adopts resin, and plastic-sealed body 14 is filled in after in sorting hole 18, and the pin 17 of multi-turn links into an integrated entity by plastic-sealed body 14.
H, carry out thinning, until the surface exposure of metal connecting layer 6 to the supporting medium layer 8 in aforesaid substrate 1 front.
As shown in Figure 9: in order to pin 17 and outside connection can be facilitated, in the embodiment of the present invention, the supporting medium layer 8 in substrate 1 front is needed to carry out grinding thinning, during concrete enforcement, can using plasma etching or grinding process carry out grinding, after skiving, the surface exposure of metal connecting layer 6 in pin 17.Further, surface-treated layer can also be set on the surface of exposed metal connecting layer 6.After the surface exposure of metal connecting layer 6, the outer surface of whole pin 17 is exposed.
Embodiment 2
As shown in Figure 10 ~ Figure 14: a kind of method improving lead frame hardness in QFN package lead frame preparation technology, the method for described raising lead frame hardness comprises the steps:
S1, provide substrate 1, and the metal connecting layer 6 be electrically connected with described substrate 1 is set on the front of substrate 1, in described metal connecting layer 6, be provided with the isolated interstice 7 of some through metal connecting layer 6;
S11, provide substrate 1, and required dry film 2 is set on the front of described substrate 1;
S12, the dry film 2 on substrate 1 is exposed and developed, to obtain pin isolation pattern 3 on substrate 1;
S13, described pin isolation pattern 3 is utilized to electroplate required metal connecting layer 6 on substrate 1; Remove described pin isolation pattern 3, to obtain the isolated interstice 7 of through described metal connecting layer 6.
The processing step of above-mentioned formation metal connecting layer 6 and isolated interstice 7 is on substrate 1 identical with embodiment 1, no longer describes in detail herein.
S2, on the front of aforesaid substrate 1, arrange supporting medium layer 8, described supporting medium layer 8 to cover in metal connecting layer 6 and is filled in isolated interstice 7; As shown in Figure 10.
S3, grinding is carried out, to make the surface exposure of metal connecting layer 6 to the supporting medium layer 8 in above-mentioned metal connecting layer 6; And second surface processing layer 15 is set on the surface that metal connecting layer 6 is exposed, second surface processing layer 15 forms the pin 17 of multi-turn with the metal connecting layer 6 below described second surface processing layer 15 by the supporting medium layer 8 in isolated interstice 7;
As shown in figure 11: in the present embodiment, plasma etching can be adopted to carry out grinding to supporting medium layer 8, first grinding is carried out to supporting medium layer 8, the damage to lead frame in follow-up grinding process can be reduced.The effect of second surface processing layer 15 is identical with the effect of above-mentioned first surface processing layer 11.Second surface processing layer 15 and corresponding metal connecting layer 6 form pin 17, and pin 17 carries out insulation isolation by the supporting medium layer 8 in isolated interstice 7, forms the structure of multi-turn simultaneously.
S4, above aforesaid substrate 1, arrange packaged chip 12, described packaged chip 12 is positioned at the central area of substrate 1, and packaged chip 12 is electrically connected by the pin 17 of connecting line 13 with described packaged chip 12 outer ring;
S5, carry out plastic packaging to above-mentioned packaged chip 12, side obtains plastic-sealed body 14 on substrate 1, and described plastic-sealed body 14 gland is in second surface processing layer 15, packaged chip 12 and supporting medium layer 8;
As shown in figure 12: central area packaged chip 12 being installed on whole lead frame, the pin 17 of multi-turn is positioned at the outer ring of packaged chip 12, can carry out available protecting by plastic-sealed body 14 to packaged chip 12.
S6, the back side of substrate 1 to be etched, with the surface exposure making metal connecting layer 6 be connected with substrate 1, pin 17 is separated from each other;
In the present embodiment, the back side of substrate 1 is etched, until all substrates 1 are all etched away, after substrate 1 etches away, the surface exposure of metal connecting layer 6, the pin 17 of multi-turn is no longer electrically connected by substrate 1, but the pin 17 of multi-turn can be linked into an integrated entity by plastic-sealed body 14.
S7, arrange the 3rd surface-treated layer 16 on the surface that metal connecting layer 6 is exposed, described 3rd processing layer 16 is electrically connected with metal connecting layer 6.
As shown in figure 13: in order to pin 17 can be facilitated by metal connecting layer 6 and outside electrical connection, the 3rd surface-treated layer 16 is set on the surface of metal connecting layer 6.As shown in figure 14: for forming the bottom view of multi-circle QFN package lead frame, there is shown the schematic diagram that packaged chip 12 outer ring arranges three circle pins 17.
The preparation technology of lead frame and substrate preparation technology merge by the present invention, and use substrate process carrys out the lead frame required for production multi-turn QFN; Semi-additive process is adopted to prepare the inside and outside pin of chip, improve the preparation precision of pin, the pin array of more thin space can be prepared, ensure the precision of pin size simultaneously, technological flexibility is high, can change the arrangement mode of pin according to demand at any time, and avoiding needs in traditional punch forming to change grinding tool, cycle is long, the problem that cost is high.Once plastic multiple lead frame, efficiency is high.In the process preparing lead frame, improved the hardness of lead frame by supporting medium layer 8, not easily bend, the destruction to encapsulating structure can be reduced by corresponding processing step, ensure that the planarization of machined surface, easily be automated production.Very thin (100 μm thick or less) that lead frame can be done and pin thickness is adjustable, meets compact development trend.
Claims (4)
1. improve a method for lead frame hardness in QFN package lead frame preparation technology, it is characterized in that, the method for described raising lead frame hardness comprises the steps:
(a), substrate (1) is provided, and the metal connecting layer (6) that is electrically connected with described substrate (1) is set on the front of substrate (1), in described metal connecting layer (6), is provided with the isolated interstice (7) of through metal connecting layer (6);
(b), on the front of aforesaid substrate (1) pressing supporting medium layer (8), described supporting medium layer (8) covers metal connecting layer (6) and goes up and be filled in isolated interstice (7);
(c), at the back side of substrate (1), mask layer (9) is set, optionally shelter and etch described mask layer (9), obtain the etched hole (10) of through described mask layer (9);
(d), utilize above-mentioned etched hole (10) to etch substrate (1), to make etched hole (10) through substrate (1), the sorting hole (18) needed for formation; Sorting hole (18) is connected with the isolated interstice (7) of filling supporting medium layer (8);
(e), the mask layer (9) removed on substrate (1), and first surface processing layer (11) is set at the back side of substrate (1); First surface processing layer (11) and corresponding substrate (1), metal connecting layer (6) form multi-circle pin (17) after being separated by sorting hole (18);
(f), in the center at aforesaid substrate (1) back side, packaged chip (12) is set, described packaged chip (12) is electrically connected with the pin (17) of described packaged chip (12) outer ring by connecting line (13);
(g), plastic packaging is carried out to above-mentioned packaged chip (12), obtain plastic-sealed body (14); Described plastic-sealed body (14) gland on packaged chip (12), first surface processing layer (11), and is filled in sorting hole (18);
(h), carry out thinning to the supporting medium layer (8) in aforesaid substrate (1) front, until the surface exposure of metal connecting layer (6).
2. the method for lead frame hardness in raising QFN package lead frame preparation technology according to claim 1, is characterized in that, in described step (a), comprise the steps:
(a1), provide substrate (1), and required dry film (2) is set on the front of described substrate (1);
(a2), to the dry film (2) on substrate (1) expose and develop, to obtain pin isolation pattern (3) on substrate (1);
(a3) metal connecting layer (6) of described pin isolation pattern (3) needed for the upper plating of substrate (1), is utilized; Remove described pin isolation pattern (3), to obtain the isolated interstice (7) of through described metal connecting layer (6).
3. the method for lead frame hardness in raising QFN package lead frame preparation technology according to claim 1, is characterized in that: the material of described substrate (1) and the material of metal connecting layer (6) include copper.
4. the method for lead frame hardness in raising QFN package lead frame preparation technology according to claim 1, is characterized in that: the material of described supporting medium layer (8) comprises PP.
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| US10147673B2 (en) | 2016-09-30 | 2018-12-04 | Stmicroelectronics, Inc. | Tapeless leadframe package with underside resin and solder contact |
| CN110323141B (en) * | 2019-04-15 | 2021-10-12 | 矽力杰半导体技术(杭州)有限公司 | Lead frame structure, chip packaging structure and manufacturing method thereof |
| CN111211097B (en) * | 2020-02-17 | 2021-11-16 | 珠海格力电器股份有限公司 | Packaging module and packaging method of power semiconductor device |
| CN112908862A (en) * | 2021-01-22 | 2021-06-04 | 山东盛品电子技术有限公司 | Chip back surface exposed packaging method without upper piece glue fixation and chip |
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| CN102486427A (en) * | 2010-12-06 | 2012-06-06 | 飞思卡尔半导体公司 | Pressure sensor and packaging method thereof |
| EP2636712A1 (en) * | 2012-03-07 | 2013-09-11 | Nitto Denko Corporation | Pressure-sensitive adhesive tape for resin encapsulation and method for producing resin encapsulation type semiconductor device |
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| JP2013135077A (en) * | 2011-12-26 | 2013-07-08 | Hitachi Cable Ltd | Substrate for semiconductor package, semiconductor package, and method of manufacturing substrate for semiconductor package and semiconductor package |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102486427A (en) * | 2010-12-06 | 2012-06-06 | 飞思卡尔半导体公司 | Pressure sensor and packaging method thereof |
| EP2636712A1 (en) * | 2012-03-07 | 2013-09-11 | Nitto Denko Corporation | Pressure-sensitive adhesive tape for resin encapsulation and method for producing resin encapsulation type semiconductor device |
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