CN103441108A - Chip front-mounting BGA encapsulating structure - Google Patents
Chip front-mounting BGA encapsulating structure Download PDFInfo
- Publication number
- CN103441108A CN103441108A CN2013103808097A CN201310380809A CN103441108A CN 103441108 A CN103441108 A CN 103441108A CN 2013103808097 A CN2013103808097 A CN 2013103808097A CN 201310380809 A CN201310380809 A CN 201310380809A CN 103441108 A CN103441108 A CN 103441108A
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- CN
- China
- Prior art keywords
- metal
- chip
- substrate
- plastic packaging
- metal coupling
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
The invention relates to a chip front-mounting BGA encapsulating structure which comprises a substrate (1). A chip (2) is mounted on the front face of the substrate (1) in a front-mounting mode, the front face of the chip (2) and the front face of the substrate (1) are connected through metal wires (9), a plurality of second metal lugs (5) are arranged on the front face of the chip (2), a plurality of first metal lugs (4) are arranged on the front face of the substrate (1) on the periphery of the chip (2), plastic packaging materials (6) encapsulate the peripheral area of the chip (2), the first metal lugs (4) and the second metal lugs (5), the plastic packaging materials (6), the first metal lugs (4) and the second metal lugs (5) are flush at the top, a metal layer (7) is electroplated on the front face of the plastic packaging materials (6), and a plurality of metal balls (8) are arranged on the back face of the substrate (1). The chip front-mounting BGA encapsulating structure has the advantages that under the condition that BGA encapsulating thickness is not increased, an integral metal cooling device is formed through an encapsulation technology, and overall cooling effects are improved.
Description
Technical field
The present invention relates to a kind of chip formal dress bga structure, belong to the semiconductor packaging field.
Background technology
Now, the semiconductor packages industry is in order to meet the requirement of various high power consumption chip, it places fin (as shown in Figure 1) on the BGA surface mostly, although fin has increased the radiating effect of encapsulation TOP face, but also therefore increased the whole height of BGA product, being difficult to be applied to the encapsulation to BGA requires thinner product as mobile phone, the handheld devices such as notebook, and the chips such as AP are owing to considering multinuclear computing etc., its power requirement is also more and more higher, requirement to heat radiation is also more and more higher, finless form is difficult to competent requirement, but increase fin and be difficult to again meet the requirement of product applied environment to thickness.And flange-cooled BGA production method, normally after the BGA production and processing is complete, then use sizing material pressing fin, so fin directly not contacting with the thermal source of substrate or chip surface, its radiating effect is bad.
Summary of the invention
The object of the invention is to overcome above-mentioned deficiency, a kind of chip formal dress bga structure is provided, it is not in the situation that increase the BGA package thickness, by packaging technology, metal coupling is integrated on the BGA plastic-sealed body, the projection bottom surface contacts with substrate surface or chip surface, the projection end face makes itself and plastic packaging material electroplating surface metal layer form the heat abstractor of an integral body by electroplating technology, because metal coupling directly is connected with substrate surface or chip surface, heat can be directly conducted to the electroplated metal layer surface, and by the convection current radiation effects of electroplated metal layer surface and air, improved the integral heat sink effect.
The object of the present invention is achieved like this: a kind of chip formal dress bga structure, it comprises substrate, described substrate front side just is being equipped with chip by conduction or non-conductive bonding material, between described chip front side and substrate front side, by metal wire, be connected, described chip front side is provided with a plurality of the second metal couplings, substrate front side around described chip arranges a plurality of the first metal couplings, described chip, the zone of the first metal coupling and the second metal coupling periphery is encapsulated with plastic packaging material, described plastic packaging material flushes with the first metal coupling and the second metal coupling top, described plastic packaging material front is electroplate with metal level, described metal level is connected with the second metal coupling top with the first metal coupling, described substrate back is provided with a plurality of Metal Ball.
Further, a plurality of the first metal couplings are exposed in described plastic packaging material side.
Further, the shape of cross section of described the first metal coupling and the second metal coupling is square, circular, hexagon or octangle.
Compared with prior art, the present invention has following beneficial effect:
A kind of chip formal dress of the present invention bga structure, it is not in the situation that increase the BGA package thickness, by packaging technology, metal coupling is integrated on the BGA plastic-sealed body, the projection bottom surface contacts with substrate surface or chip surface, the projection end face makes itself and plastic packaging material electroplating surface metal layer form an integral heat dissipation means by electroplating technology, because metal coupling directly is connected with substrate surface or chip surface, heat can be directly conducted to the electroplated metal layer surface, and, by the convection current radiation effects of electroplated metal layer surface and air, improved the integral heat sink effect; Metal coupling can adopt some fixed dimension specifications, convenient batch production, and can carry out flexible arrangement according to the needs of inner structure, inner hotspot location and the moulding of mould stream with link position, the contact area of substrate, chip surface, be conducive to produce in enormous quantities, also overcome and adopted monoblock heat radiating metal piece to need special phenomenon because die size is different, package dimension varies in size.
The accompanying drawing explanation
The structural representation that Fig. 1 is in the past common radiation type BGA.
Each operation schematic diagram that Fig. 2 ~ Fig. 9 is a kind of chip formal dress of the present invention bga structure manufacture method.
The schematic diagram that Figure 10 is a kind of chip formal dress of the present invention bga structure.
The schematic diagram that Figure 11 is another embodiment of a kind of chip formal dress of the present invention bga structure.
Wherein:
Substrate 1
Chip 2
Conduction or non-conductive bonding material 3
The first metal coupling 4
The second metal coupling 5
Metal Ball 8
Metal wire 9.
Embodiment
Referring to Figure 10, a kind of chip formal dress of the present invention bga structure, it comprises substrate 1, chip 2 just is being equipped with by conduction or non-conductive bonding material 3 in described substrate 1 front, described chip 2 positive with substrate 1 front between by metal wire 9, be connected, described chip 2 fronts are provided with a plurality of the second metal couplings 5 by heat-conducting glue, substrate 1 front around described chip 2 arranges a plurality of the first metal couplings 4 by heat-conducting glue, described the first metal coupling 4 flushes with the second metal coupling 5 tops, described chip 2, the zone of the first metal coupling 4 and the second metal coupling 5 peripheries is encapsulated with plastic packaging material 6, described plastic packaging material 6 flushes with the first metal coupling 4 and the second metal coupling 5 tops, described plastic packaging material 6 fronts are electroplate with metal level 7, described metal level 7 is connected with the second metal coupling 5 tops with the first metal coupling 4, described substrate 1 back side is provided with a plurality of Metal Ball 8.
The shape of cross section of described the first metal coupling 4 and the second metal coupling 5 can be square, circular, hexagon, octangle etc., and metal coupling can be installed in SMT operation or load operation.
Its manufacture method is as follows:
Step 1, get a plate base
Referring to Fig. 2, get a plate base, contain printed circuit on substrate, the selection of substrate thickness can be selected according to product performance;
Step 2, load
Referring to Fig. 3, in the front of substrate, by conduction or non-conductive bonding material, just loading onto chip;
Step 3, metal wire bonding
Referring to Fig. 4, carry out the operation of bonding metal wire between chip front side and substrate front side;
Step 4, installation metal coupling
Referring to Fig. 5, the substrate front side around the chip that completes the load routing is installed a plurality of the first metal derbies by heat-conducting glue, in chip front side, by heat-conducting glue, installs a plurality of the second metal derbies;
Step 5, plastic packaging
Participate in Fig. 6, the substrate front side that completes the metal coupling installation in step 4 is carried out the protection of epoxy resin plastic packaging, and epoxide resin material can be selected filler be arranged or do not have Packed kind according to product performance;
Referring to Fig. 7, after completing the epoxy resin plastic packaging, step 5 carries out surface grinding, and make the first metal coupling and the second metal coupling top expose the plastic packaging material surface;
Referring to Fig. 8, the plastic packaging material electroplating surface last layer metal level after step 6 completes grinding;
Referring to Fig. 9, the substrate back after step 7 completes electroplated metal layer is implanted a plurality of Metal Ball.
Another of a kind of chip formal dress of the present invention bga structure implemented as shown in figure 11, it is by the unnecessary plastic packaging material in corner is cut after the electroplated metal layer operation, make the plastic packaging material side expose a plurality of the first metal couplings, thereby increase the contact area of itself and air, promote the radiating efficiency with the cross-ventilation radiation.
Claims (3)
1. a chip formal dress bga structure, it is characterized in that: it comprises substrate (1), described substrate (1) is positive just is being equipped with chip (2) by conduction or non-conductive bonding material (3), described chip (2) positive with substrate (1) front between by metal wire (9), be connected, described chip (2) front is provided with a plurality of the second metal couplings (5), described chip (2) substrate (1) front on every side arranges a plurality of the first metal couplings (4), described chip (2), the peripheral zone of the first metal coupling (4) and the second metal coupling (5) is encapsulated with plastic packaging material (6), described plastic packaging material (6) flushes with the first metal coupling (4) and the second metal coupling (5) top, described plastic packaging material (6) front is electroplate with metal level (7), described metal level (7) is connected to form an integral heat dissipation means with the first metal coupling (4) and the second metal coupling (5) top by plating, described substrate (1) back side is provided with a plurality of Metal Ball (8).
2. a kind of chip formal dress bga structure according to claim 1, it is characterized in that: a plurality of the first metal couplings (4) are exposed in described plastic packaging material (6) side.
3. a kind of chip formal dress bga structure according to claim 1 and 2 is characterized in that: the shape of cross section of described the first metal coupling (4) and the second metal coupling (5) is square, circular, hexagon or octangle.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013103808097A CN103441108A (en) | 2013-08-28 | 2013-08-28 | Chip front-mounting BGA encapsulating structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013103808097A CN103441108A (en) | 2013-08-28 | 2013-08-28 | Chip front-mounting BGA encapsulating structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103441108A true CN103441108A (en) | 2013-12-11 |
Family
ID=49694796
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2013103808097A Pending CN103441108A (en) | 2013-08-28 | 2013-08-28 | Chip front-mounting BGA encapsulating structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103441108A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107785329A (en) * | 2016-08-30 | 2018-03-09 | 矽品精密工业股份有限公司 | Electronic package structure and method for fabricating the same |
| CN117393517A (en) * | 2023-12-08 | 2024-01-12 | 成都智多晶科技有限公司 | Wire bonding type packaging structure and substrate capable of effectively enhancing heat dissipation efficiency |
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| JP2005327771A (en) * | 2004-05-12 | 2005-11-24 | Nec Electronics Corp | Ball grid type semiconductor device |
| CN1909216A (en) * | 2005-08-01 | 2007-02-07 | 恩益禧电子股份有限公司 | Semiconductor package featuring metal lid member |
| CN101127334A (en) * | 2006-06-20 | 2008-02-20 | 美国博通公司 | Integrated circuit packages and its manufacture method |
| CN102549739A (en) * | 2009-10-13 | 2012-07-04 | 阿尔特拉公司 | Ic package with non-uniform dielectric layer thickness |
| CN103021972A (en) * | 2011-09-22 | 2013-04-03 | 国碁电子(中山)有限公司 | Chip encapsulation structure and method |
-
2013
- 2013-08-28 CN CN2013103808097A patent/CN103441108A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005327771A (en) * | 2004-05-12 | 2005-11-24 | Nec Electronics Corp | Ball grid type semiconductor device |
| CN1909216A (en) * | 2005-08-01 | 2007-02-07 | 恩益禧电子股份有限公司 | Semiconductor package featuring metal lid member |
| US20070045798A1 (en) * | 2005-08-01 | 2007-03-01 | Nec Electronics Corporation | Semiconductor package featuring metal lid member |
| CN101127334A (en) * | 2006-06-20 | 2008-02-20 | 美国博通公司 | Integrated circuit packages and its manufacture method |
| CN102549739A (en) * | 2009-10-13 | 2012-07-04 | 阿尔特拉公司 | Ic package with non-uniform dielectric layer thickness |
| CN103021972A (en) * | 2011-09-22 | 2013-04-03 | 国碁电子(中山)有限公司 | Chip encapsulation structure and method |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107785329A (en) * | 2016-08-30 | 2018-03-09 | 矽品精密工业股份有限公司 | Electronic package structure and method for fabricating the same |
| CN117393517A (en) * | 2023-12-08 | 2024-01-12 | 成都智多晶科技有限公司 | Wire bonding type packaging structure and substrate capable of effectively enhancing heat dissipation efficiency |
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| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C12 | Rejection of a patent application after its publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20131211 |