CN107731764B - Semiconductor packaging structure - Google Patents
Semiconductor packaging structure Download PDFInfo
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- CN107731764B CN107731764B CN201710917659.7A CN201710917659A CN107731764B CN 107731764 B CN107731764 B CN 107731764B CN 201710917659 A CN201710917659 A CN 201710917659A CN 107731764 B CN107731764 B CN 107731764B
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- heat dissipation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3672—Foil-like cooling fins or heat sinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3675—Cooling facilitated by shape of device characterised by the shape of the housing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The invention relates to a semiconductor packaging structure which comprises a lead frame (1), wherein the lead frame (1) comprises a plurality of pins (1.1), a chip (3) is arranged on the pins (1.1) in an inverted mode, a heat dissipation frame (4) is arranged on the chip (3), the heat dissipation frame (4) comprises a heat dissipation plate (4.1) and elastic pins (4.2), the upper surface of the chip (3) is in contact with the lower surface of the heat dissipation plate (4.1), the lead frame (1), the chip (2) and the heat dissipation frame (4) are packaged in a plastic packaging material (5), and the lower surface of the pin (1.1) and the lower surface of the elastic pins (4.2) are located on the same plane and exposed outside the plastic packaging material (5). The invention relates to a semiconductor packaging structure, which can ensure that the height from the lower surface of an elastic pin to the upper surface of a heat dissipation frame is the same as the height of a mold cavity, thereby ensuring that the lower surface of the elastic pin is exposed outside a plastic packaging material, and ensuring that the heat dissipation frame of the packaging structure can reliably realize the grounding function.
Description
Technical Field
The invention relates to a semiconductor packaging structure, and belongs to the technical field of semiconductor packaging.
Background
Electronic components such as microprocessors and integrated circuits must operate within a certain specified temperature range to operate efficiently. Excessive heat reduces the performance, reliability and life expectancy of the electronic components and can even cause failure. Therefore, heat sinks are widely used to control excessive heat. In the conventional chip packaging structure with the heat sink, a plastic package material is separated between the heat sink and the chip surface, however, because the heat dissipation performance of the plastic package material is poor, the heat dissipated by the chip during operation cannot be dissipated effectively through the plastic package material, and further the electric heating performance and reliability of the electronic product are affected.
In addition to generating heat, electronic components also generate electromagnetic radiation. Electromagnetic radiation emitted by electronic components can cause electromagnetic interference (EMI) or noise in adjacent electronic components and systems. The heat sink acts as an antenna to further radiate electromagnetic radiation generated by the electronic component, so the heat sink is typically grounded for EMI suppression.
Referring to fig. 1, in order to provide a conventional package structure capable of improving heat dissipation performance, a heat dissipation frame is disposed on a chip, jaws are disposed on four sides of the heat dissipation frame downward, and the chip and a heat sink are attached together, so that a better heat dissipation effect can be achieved. In addition, the grounding electrical function of the radiating fins can be realized through clamping claws on four sides of the radiating frame.
However, the packaging structure has many defects during packaging:
1. because the height of the clamping jaw has tolerance, if the height is too high, the upper die can press the heat dissipation frame downwards during the re-die assembly, the outer edge of the clamping jaw can be stressed to tilt upwards, so that flash on the lower surface of the clamping jaw is caused, and in addition, the heat dissipation frame is not attached to the chip, so that the heat dissipation effect is influenced. If the height is too low, the bottom of the clamping jaw has a certain distance from the lower die, the lower surface of the clamping jaw is completely covered in the plastic packaging material during packaging, and the lower surface of the clamping jaw has flash or is completely covered in the plastic packaging material, so that the grounding function of the packaging structure is failed;
2. the height from the lower surface of the pin to the upper surface of the chip has tolerance, if the height is too high, the height from the lower surface of the pin to the upper surface of the heat dissipation frame exceeds the height of a mold cavity of the mold, and the heat dissipation frame can crush the chip during mold closing; if the height is too low, a certain gap is formed between the heat dissipation frame and the upper surface of the chip, and after encapsulation, molding compound or air bubbles exist between the heat dissipation frame and the upper surface of the chip, so that heat conduction between the chip and the heat dissipation frame is affected, and the heat dissipation capability of the whole package is affected.
Disclosure of Invention
The invention aims to solve the technical problem of providing a semiconductor packaging structure aiming at the prior art, which can ensure that the height from the lower surface of an elastic pin to the upper surface of a heat dissipation frame is the same as the height of a mold cavity, thereby ensuring that the lower surface of the elastic pin is exposed outside a plastic packaging material, and ensuring that the heat dissipation frame of the packaging structure can reliably realize the grounding function;
on the other hand, the height from the lower surface of the pin to the upper surface of the heat dissipation frame is the same as that of the mold cavity, so that the chip can be ensured to be directly and completely contacted with the heat dissipation frame, the packaging structure has a better heat dissipation effect, and the chip can be prevented from being crushed by the packaging mold.
The technical scheme adopted by the invention for solving the problems is as follows: the utility model provides a semiconductor package structure, it includes the lead frame, the lead frame includes a plurality of pins, the chip is equipped with through the tin ball on the pin, be provided with heat dissipation frame on the chip, heat dissipation frame includes heating panel and elasticity pin, the elasticity pin is connected and is set up around the heating panel, the chip upper surface contacts with the heating panel lower surface, lead frame, chip and heat dissipation frame package are in the plastic envelope material, pin lower surface and elasticity pin lower surface are located the coplanar and expose outside the plastic envelope material, heating panel upper surface exposes outside the plastic envelope material.
The utility model provides a semiconductor packaging structure, it includes the lead frame, the lead frame includes a plurality of pins, the chip is equipped with through the tin ball upside down on the pin, be provided with heat dissipation frame on the chip, heat dissipation frame includes heating panel, elasticity pin heat-conducting member, elasticity pin is connected and is set up around the heating panel, heat-conducting member sets up in the chip upper surface, be connected through heat-conducting member between chip and the heating panel, lead frame, chip and heat dissipation frame seal are in the plastic envelope material, pin lower surface and elasticity pin lower surface are located the coplanar and expose outside the plastic envelope material, the heating panel upper surface exposes outside the plastic envelope material.
The utility model provides a semiconductor packaging structure, it includes the lead frame, the lead frame includes pin and base island, the pin encircles with single group or multiunit mode and arranges around the base island, be provided with the chip through bonding material or solder on the base island, the chip passes through metal bonding wire and pin electric connection, be provided with heat dissipation frame on the chip, heat dissipation frame includes heating panel, elasticity pin and heat-conducting piece, the connection of elasticity pin sets up around the heating panel, heat-conducting piece sets up on the chip, be connected through heat-conducting piece between chip and the heating panel, lead frame, chip and heat dissipation frame cladding are in the plastic envelope material, pin lower surface and elasticity pin lower surface are located the coplanar and expose outside the plastic envelope material, the heating panel upper surface exposes outside the plastic envelope material.
The heat conducting member is an elastic heat conducting member.
The elastic heat conducting piece and the heat dissipation plate are of an integrated structure or a split structure.
Compared with the prior art, the invention has the advantages that:
1. the invention can ensure that the height from the lower surface of the elastic pin to the upper surface of the heat dissipation frame is the same as the height of the mold cavity, thereby ensuring that the lower surface of the elastic pin is exposed outside the plastic package material, and ensuring that the heat dissipation frame of the packaging structure can reliably realize the grounding function;
2. the height from the lower surface of the elastic heat conducting piece to the upper surface of the heat dissipation plate can be changed along with the height from the lower surface of the pin to the upper surface of the chip, so that the height from the lower surface of the pin to the upper surface of the heat dissipation frame is the same as the height of the die cavity, the chip is ensured to be directly and completely contacted with the heat dissipation frame, and the packaging structure has better heat dissipation effect and electrical property;
3. the heat dissipation frame of the invention realizes the direct combination of the heat dissipation frame and the chip by the occlusion of the elastic pins and the plastic package material, simplifies the process, saves the adhesive and can reduce the production and material costs.
Drawings
Fig. 1 is a schematic view of a conventional package structure capable of improving heat dissipation performance.
Fig. 2 is a schematic view of a semiconductor package structure according to embodiment 1 of the invention.
Fig. 3 is a schematic view of a semiconductor package structure according to embodiment 2 of the present invention.
Fig. 4 to 10 are schematic views of another embodiment of an elastic heat conductor in embodiment 2 of a semiconductor package structure according to the present invention.
Fig. 11 is a schematic view of a semiconductor package structure according to embodiment 3 of the present invention.
Fig. 12 is a schematic view of a semiconductor package structure according to embodiment 4 of the present invention.
Fig. 13-19 are schematic views of another embodiment of a heat conducting member in embodiment 4 of a semiconductor package structure according to the present invention.
Wherein:
Pin 1.1
Island 1.2
Heat sink plate 4.1
Elastic pin 4.2
Heat conducting member 4.3
Adhesive substance or solder 7.
Detailed Description
The invention is described in further detail below with reference to the accompanying examples.
Example 1:
as shown in fig. 2, the semiconductor package structure in this embodiment includes a lead frame 1, the lead frame 1 includes a plurality of leads 1.1, a chip 3 is flip-mounted on the leads 1.1 through solder balls 2, a heat dissipation frame 4 is disposed on the chip 3, the heat dissipation frame 4 includes a heat dissipation plate 4.1 and elastic pins 4.2, the elastic pins 4.2 are connected and disposed around the heat dissipation plate 4.1, an upper surface of the chip 3 contacts with a lower surface of the heat dissipation plate 4.1, the lead frame 1, the chip 2 and the heat dissipation frame 4 are covered in a molding compound 5, the lower surface of the leads 1.1 and the lower surface of the elastic pins 4.2 are located on the same plane and exposed outside the molding compound 5, and the upper surface of the heat dissipation plate 4.1 is exposed outside the molding compound 5;
example 2:
as shown in fig. 3, the semiconductor package structure in this embodiment includes a lead frame 1, the lead frame 1 includes a plurality of leads 1.1, a chip 3 is flip-mounted on the leads 1.1 through solder balls 2, a heat dissipation frame 4 is disposed on the chip 3, the heat dissipation frame 4 includes a heat dissipation plate 4.1, an elastic pin 4.2 and a heat conduction member 4.3, the elastic pin 4.2 is disposed around the heat dissipation plate 4.1, the heat conduction member 4.3 is disposed on an upper surface of the chip 2, the chip 2 is connected to the heat dissipation plate 4.1 through the heat conduction member 4.3, the lead frame 1, the chip 2 and the heat dissipation frame 4 are covered in a molding compound 5, a lower surface of the lead 1.1 and a lower surface of the elastic pin 4.2 are located on the same plane and exposed outside the molding compound 5, and an upper surface of the heat dissipation plate 4.1 is exposed outside the molding compound 5;
the heat conducting member 4.3 is an elastic heat conducting member;
as shown in fig. 4 to 10, the shape and structure of the heat conducting member 4.3 are not limited as long as it has a certain elasticity
The heat conducting piece 4.3 and the heat dissipation plate 4.1 are of an integral structure or a split structure;
and can play the role of heat conduction and meet the requirements.
Example 3:
as shown in fig. 11, the semiconductor package structure in this embodiment includes a lead frame 1, the lead frame 1 includes pins 1.1 and a base island 1.2, the pins 1.1 are arranged around the base island 1.2 in a single-group or multi-group manner, a chip 3 is disposed on the base island 1.2 through an adhesive or solder 7, the chip 3 is electrically connected to the pins 1.1 through metal bonding wires 6, a heat dissipation frame 4 is disposed on the chip 3, the heat dissipation frame 4 includes a heat dissipation plate 4.1, elastic pins 4.2 and heat conduction members 4.3, the elastic pins 4.2 are disposed around the heat dissipation plate 4.1, the heat conduction members 4.3 are disposed on the chip 2, the chip 2 is connected to the heat dissipation plate 4.1 through the heat conduction members 4.3, the lead frame 1, the chip 2 and the heat dissipation frame 4 are covered in a plastic package material 5, lower surfaces of the pins 1.1 and the elastic pins 4.2 are located on the same plane and exposed outside the plastic package material 5, the upper surface of the heat dissipation plate 4.1 is exposed outside the plastic package material 5;
example 4:
as shown in fig. 12, example 4 differs from example 3 in that: the heat conducting member 4.3 is an elastic heat conducting member;
the heat conducting piece 4.3 and the heat dissipation plate 4.1 are of an integral structure or a split structure;
as shown in fig. 13 and 19, the shape and structure of the heat conducting member 4.3 are not limited, and it is sufficient if it has certain elasticity and can conduct heat.
In addition to the above embodiments, the present invention also includes other embodiments, and any technical solutions formed by equivalent transformation or equivalent replacement should fall within the scope of the claims of the present invention.
Claims (4)
1. A semiconductor package structure, characterized in that: it includes lead frame (1), lead frame (1) includes a plurality of pins (1.1), chip (3) are equipped with through tin ball (2) on pin (1.1) fall, be provided with heat dissipation frame (4) on chip (3), heat dissipation frame (4) include heating panel (4.1) and elasticity pin (4.2), elasticity pin (4.2) are connected and are set up around heating panel (4.1), chip (3) upper surface contacts with heating panel (4.1) lower surface, lead frame (1), chip (2) and heat dissipation frame (4) encapsulate in plastic envelope material (5), pin (1.1) lower surface and elasticity pin (4.2) lower surface are located the coplanar and expose outside plastic envelope material (5), heating panel (4.1) upper surface exposes outside plastic envelope material (5).
2. A semiconductor package structure, characterized in that: the lead frame comprises a lead frame (1), wherein the lead frame (1) comprises a plurality of pins (1.1), a chip (3) is inversely arranged on the pins (1.1) through solder balls (2), a heat dissipation frame (4) is arranged on the chip (3), the heat dissipation frame (4) comprises a heat dissipation plate (4.1) and an elastic pin (4.2) and a heat conduction piece (4.3), the elastic pin (4.2) is connected and arranged around the heat dissipation plate (4.1), the heat conduction piece (4.3) is arranged on the upper surface of the chip (2), the chip (2) and the heat dissipation plate (4.1) are connected through the heat conduction piece (4.3), the heat conduction piece (4.3) is an elastic heat conduction piece, the lead frame (1), the chip (2) and the heat dissipation frame (4) are encapsulated in a plastic packaging material (5), the lower surfaces of the pins (1.1) and the elastic pin (4.2) are positioned on the same plane and exposed outside the plastic packaging material (5), the upper surface of the heat dissipation plate (4.1) is exposed out of the plastic packaging material (5).
3. A semiconductor package structure, characterized in that: it includes lead frame (1), lead frame (1) includes pin (1.1) and base island (1.2), pin (1.1) encircle to arrange around base island (1.2) with single group or multiunit mode, be provided with chip (3) through bonding material or solder (7) on base island (1.2), chip (3) are through metal bonding wire (6) and pin (1.1) electric connection, be provided with heat dissipation frame (4) on chip (3), heat dissipation frame (4) include heating panel (4.1), elasticity pin (4.2) and heat-conducting piece (4.3), elasticity pin (4.2) are connected and are set up around heating panel (4.1), heat-conducting piece (4.3) set up on chip (2), be connected through heat-conducting piece (4.3) between chip (2) and the heating panel (4.1), heat-conducting piece (4.3) are the elasticity heat-conducting piece, lead frame (1), Chip (2) and heat dissipation frame (4) cladding are in plastic packaging material (5), pin (1.1) lower surface and elasticity pin (4.2) lower surface are located the coplanar and expose outside plastic packaging material (5), heat dissipation plate (4.1) upper surface exposes outside plastic packaging material (5).
4. A semiconductor package according to any one of claims 2 or 3, wherein: the elastic heat conducting piece (4.3) and the heat dissipation plate (4.1) are of an integral structure or a split structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201710917659.7A CN107731764B (en) | 2017-09-30 | 2017-09-30 | Semiconductor packaging structure |
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| CN201710917659.7A CN107731764B (en) | 2017-09-30 | 2017-09-30 | Semiconductor packaging structure |
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| CN107731764A CN107731764A (en) | 2018-02-23 |
| CN107731764B true CN107731764B (en) | 2020-04-21 |
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| CN111146163B (en) * | 2019-12-25 | 2022-02-01 | 苏州通富超威半导体有限公司 | Chip module and preparation method |
| CN111933595A (en) * | 2020-07-16 | 2020-11-13 | 杰群电子科技（东莞）有限公司 | Semiconductor packaging structure and manufacturing method thereof |
| CN117855178A (en) * | 2023-09-25 | 2024-04-09 | 日月新半导体(威海)有限公司 | Semiconductor package design method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1622319A (en) * | 2003-11-27 | 2005-06-01 | 矽统科技股份有限公司 | Wafer radiating element |
| CN101261983A (en) * | 2007-03-07 | 2008-09-10 | 奥林巴斯映像株式会社 | Semiconductor device with image pick-up element |
| CN103687432A (en) * | 2012-09-07 | 2014-03-26 | 仁宝电脑工业股份有限公司 | Heat radiation module |
| CN104465551A (en) * | 2014-12-26 | 2015-03-25 | 江苏长电科技股份有限公司 | Packaging structure capable of achieving electricity property and heat dissipation through mechanical press mode and process method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009252956A (en) * | 2008-04-04 | 2009-10-29 | Panasonic Corp | Mounting frame, semiconductor device, and method of manufacturing the same |
| CN106328612A (en) * | 2015-06-25 | 2017-01-11 | 浙江盾安人工环境股份有限公司 | Chip heat radiation apparatus and electronic assembly thereof |
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2017
- 2017-09-30 CN CN201710917659.7A patent/CN107731764B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1622319A (en) * | 2003-11-27 | 2005-06-01 | 矽统科技股份有限公司 | Wafer radiating element |
| CN101261983A (en) * | 2007-03-07 | 2008-09-10 | 奥林巴斯映像株式会社 | Semiconductor device with image pick-up element |
| CN103687432A (en) * | 2012-09-07 | 2014-03-26 | 仁宝电脑工业股份有限公司 | Heat radiation module |
| CN104465551A (en) * | 2014-12-26 | 2015-03-25 | 江苏长电科技股份有限公司 | Packaging structure capable of achieving electricity property and heat dissipation through mechanical press mode and process method |
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