CN111933595A - Semiconductor packaging structure and manufacturing method thereof - Google Patents
Semiconductor packaging structure and manufacturing method thereof Download PDFInfo
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- CN111933595A CN111933595A CN202010686205.5A CN202010686205A CN111933595A CN 111933595 A CN111933595 A CN 111933595A CN 202010686205 A CN202010686205 A CN 202010686205A CN 111933595 A CN111933595 A CN 111933595A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 103
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 55
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 230000017525 heat dissipation Effects 0.000 claims abstract description 162
- 239000002184 metal Substances 0.000 claims abstract description 69
- 229910052751 metal Inorganic materials 0.000 claims abstract description 69
- 238000001746 injection moulding Methods 0.000 claims abstract description 16
- 239000000084 colloidal system Substances 0.000 claims abstract description 15
- 239000000463 material Substances 0.000 claims description 17
- 239000003292 glue Substances 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 10
- 239000000853 adhesive Substances 0.000 claims description 9
- 230000001070 adhesive effect Effects 0.000 claims description 9
- 239000008393 encapsulating agent Substances 0.000 claims description 7
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical group [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 5
- 229910021389 graphene Inorganic materials 0.000 claims description 5
- 239000012778 molding material Substances 0.000 claims description 3
- 238000009434 installation Methods 0.000 claims 1
- 239000007788 liquid Substances 0.000 description 38
- 239000000110 cooling liquid Substances 0.000 description 12
- 239000002826 coolant Substances 0.000 description 10
- 238000001816 cooling Methods 0.000 description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000012858 packaging process Methods 0.000 description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 239000005022 packaging material Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000012809 cooling fluid Substances 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000010248 power generation Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/46—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids
- H01L23/473—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids by flowing liquids
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4871—Bases, plates or heatsinks
- H01L21/4882—Assembly of heatsink parts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3736—Metallic materials
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- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Materials Engineering (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The invention discloses a semiconductor packaging structure and a manufacturing method thereof, wherein the semiconductor packaging structure comprises: a chip carrier; a chip fixed to a chip carrier; a packaging colloid which coats the chip and the chip carrier; the upper heat dissipation channels are transversely arranged in the semiconductor packaging structure and are positioned above the chip; a plurality of lower heat dissipation channels transversely disposed within the chip carrier; the vertical heat dissipation channel is vertically arranged in the semiconductor packaging structure; the upper heat dissipation channel is communicated with the outside through the upper opening; the lower heat dissipation channel is communicated with the outside through the lower opening; the manufacturing method comprises a chip carrier providing step, a chip combining step, a metal side frame combining step, a vertical metal tube installing step and an injection molding step; the semiconductor packaging structure has good heat dissipation performance, and the manufacturing method can produce the semiconductor packaging structure with good heat dissipation performance.
Description
Technical Field
The present invention relates to the field of semiconductor packaging technologies, and in particular, to a semiconductor package structure and a method for manufacturing the semiconductor package structure.
Background
Semiconductors have applications in the fields of integrated circuits, consumer electronics, communication systems, photovoltaic power generation, lighting, high-power conversion, and the like; the semiconductor package structure is formed by fixing a chip (or wafer) on a corresponding chip carrier, and coating a layer of packaging colloid for protection on the chip and the chip carrier after the chip and the chip carrier are electrically connected as necessary to avoid the pollution of liquid, dust and gas in the environment to the internal circuit; however, for the high-power semiconductor package structure, the internal power device is easy to generate heat during operation, and if the heat cannot be effectively transferred to the outside of the semiconductor package structure in time, the accumulated heat will greatly affect the performance of the chip, thereby affecting the reliability of the semiconductor package structure.
In the prior art, the heat generated by the chip is generally conducted to the external atmosphere through the encapsulant, but the thermal conductivity of the encapsulant is poor, which results in poor heat dissipation performance of the conventional semiconductor package structure. There are some semiconductor package structures in the market, which implement heat dissipation of the semiconductor package structure by adding a metal heat sink (such as a tooth-shaped heat sink) on the semiconductor package structure, but the heat dissipation performance of the existing semiconductor package structure is limited because the heat exchange efficiency between the heat sink and the chip and the heat exchange efficiency between the heat sink and the atmosphere are both relatively limited.
Disclosure of Invention
One object of an embodiment of the present invention is to: the semiconductor packaging structure has good heat dissipation performance and high reliability.
Another object of an embodiment of the present invention is to: a method for manufacturing a semiconductor package is provided, which can manufacture a semiconductor package having excellent heat dissipation performance.
In order to achieve the purpose, the invention adopts the following technical scheme:
a semiconductor package structure, comprising:
a chip carrier;
a chip secured to the top of the chip carrier;
a packaging colloid which coats the chip and the chip carrier;
a plurality of upper heat dissipation channels transversely arranged in the semiconductor packaging structure, wherein the upper heat dissipation channels are positioned above the chip;
a plurality of lower heat dissipation channels transversely disposed within the chip carrier;
the vertical heat dissipation channel is vertically arranged in the semiconductor packaging structure, at least one part of the vertical heat dissipation channel is positioned in the packaging colloid, and openings at two ends of the vertical heat dissipation channel are communicated with the outside;
the upper opening is arranged on the side wall of the semiconductor packaging structure, and the upper heat dissipation channel is communicated with the outside through the upper opening;
and the lower opening is arranged on the side wall of the semiconductor packaging structure, and the lower heat dissipation channel is communicated with the outside through the lower opening.
Preferably, the packaging structure further comprises a metal frame, the metal frame is fixed to the top of the packaging colloid, and the upper heat dissipation channels are arranged in the metal frame.
Preferably, the number of the vertical heat dissipation channels is at least two.
Preferably, the chip is located between the plurality of vertical heat dissipation channels.
Preferably, in the height direction of the semiconductor package structure, the lower heat dissipation channel is arranged right below the chip, and the upper heat dissipation channel is arranged right above the chip.
Preferably, the wall surfaces of the upper heat dissipation channel and/or the lower heat dissipation channel and/or the vertical heat dissipation channel are provided with heat dissipation layers, and the heat dissipation layers are graphene heat dissipation layers or carbide heat dissipation layers.
Preferably, the device also comprises a vertical metal tube; the vertical metal tube penetrates through the chip carrier, the packaging colloid and the metal frame, and an internal channel of the vertical metal tube is the vertical heat dissipation channel.
Preferably, the inner wall of the vertical metal pipe is provided with a turbulent flow structure.
Preferably, the plurality of upper openings and the plurality of lower openings are located on the same sidewall of the semiconductor package structure.
A manufacturing method of a semiconductor packaging structure comprises the following steps:
a chip carrier providing step: providing a chip carrier, wherein a transversely arranged lower heat dissipation channel is arranged in the chip carrier, and two ends of the lower heat dissipation channel are communicated with the outside; the chip carrier is also provided with a first vertical through hole;
chip combination step: providing a chip carrier and a chip, and fixing the chip in a carrier core area of the chip carrier by adopting a bonding material;
combining the metal side frames: providing a metal side frame, wherein the metal side frame comprises a vertical frame and a transverse frame which are connected with each other, and the transverse frame is provided with a second vertical through hole and a plurality of upper heat dissipation channels which are transversely arranged; connecting the vertical frame to the circumferential side wall of the chip carrier in a surrounding manner by adopting a bonding material so as to form an injection molding groove capable of containing injection molding materials among the vertical frame, the top of the chip carrier and the transverse frame, wherein the injection molding groove is a glue filling space;
a vertical metal pipe mounting step: inserting one end of a vertical metal pipe into the first vertical through hole, and inserting the other end of the vertical metal pipe into the second vertical through hole;
injection molding: and injecting a packaging adhesive material into the injection molding groove, wherein the maximum height of the injected packaging adhesive material is lower than or level to the top end of the vertical metal pipe, and a packaging body is formed after the packaging adhesive is cured and molded.
The invention has the beneficial effects that: the semiconductor packaging structure has good heat dissipation performance and high reliability; the method for manufacturing the semiconductor packaging structure can manufacture the semiconductor packaging structure with good heat dissipation performance.
Drawings
The invention is explained in more detail below with reference to the figures and examples.
Fig. 1 is a schematic structural diagram of a semiconductor package structure according to an embodiment of the invention;
fig. 2 is a schematic structural diagram of a semiconductor package structure according to another embodiment of the invention;
fig. 3 is a schematic structural diagram of a semiconductor package structure according to another embodiment of the invention;
FIG. 4 is a cross-sectional view taken along line A-A or line B-B of FIG. 2;
FIG. 5 is a sectional view taken along line A-A or a sectional view taken along line B-B of FIG. 2;
in the figure: 100. a chip carrier; 110. a lower heat dissipation channel; 120. a lower opening; 121. a liquid inlet and outlet; 122. a lower liquid outlet; 130. a pin; 200. a chip; 300. packaging the colloid; 410. an upper heat dissipation channel; 420. an upper opening; 421. an upper liquid inlet; 422. an upper liquid outlet; 500. a vertical heat dissipation channel; 510. a vertical liquid inlet; 520. a vertical liquid outlet; 600. a metal frame; 700. a metal wire; 800. a vertical metal tube; 900. a turbulent flow structure.
Detailed Description
In order to make the technical problems solved, technical solutions adopted and technical effects achieved by the present invention clearer, the technical solutions of the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, unless otherwise explicitly specified or limited, the terms "connected" and "fixed" are to be understood broadly, e.g., as being fixedly connected, detachably connected, or integrated; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
The invention provides a semiconductor packaging structure which has good heat dissipation performance, can better exert the performance of a chip 200 and has high reliability.
As shown in fig. 1-5, in an embodiment of the semiconductor package structure of the present invention, the semiconductor package structure includes:
a chip carrier 100 having a die area on top for carrying a chip 200;
a chip 200 fixed to a chip area on top of the chip carrier 100;
a molding compound 300 encapsulating the chip 200 and the chip carrier 100 to electrically and physically protect the chip 200 and the chip carrier 100;
a plurality of upper heat dissipation channels 410 laterally disposed within the semiconductor package structure, wherein the upper heat dissipation channels 410 are located above the chip 200;
a plurality of lower heat dissipation channels 110 laterally disposed within the chip carrier 100, the lower heat dissipation channels 110 being located below the chip 200;
a vertical heat dissipation channel 500 vertically disposed in the semiconductor package structure, wherein at least a portion of the vertical heat dissipation channel 500 is located in the package encapsulant 300, and openings at two ends of the vertical heat dissipation channel 500 are communicated with the outside; an opening at one end of the vertical heat dissipation channel 500 is a vertical liquid inlet 510, an opening at the other end of the vertical heat dissipation channel 500 is a vertical liquid outlet 520, the vertical liquid inlet 510 is used for guiding a cooling medium into the vertical heat dissipation channel 500, and the vertical liquid outlet 520 is used for guiding the cooling medium in the vertical heat dissipation channel 500 out of the vertical heat dissipation channel 500;
an upper opening 420 disposed on a sidewall of the semiconductor package structure, wherein the upper heat dissipation channel 410 is communicated with the outside through the upper opening 420, the upper opening 420 includes an upper liquid inlet 421 and an upper liquid outlet 422, the upper liquid inlet 421 is configured to introduce a cooling medium into the upper heat dissipation channel 410, and the upper liquid outlet 422 is configured to guide the cooling medium in the upper heat dissipation channel 410 out of the upper heat dissipation channel 410;
a lower opening 120 formed in a sidewall of the semiconductor package structure, wherein the lower heat dissipation channel 110 is communicated with the outside through the lower opening 120, and the lower opening 120 includes a lower liquid inlet 121 and a lower liquid outlet 122; the lower liquid inlet 121 is used for guiding a cooling medium into the lower heat dissipation channel 110, and the lower liquid outlet 122 is used for guiding the cooling medium in the lower heat dissipation channel 110 out of the lower heat dissipation channel 110.
Further, the vertical heat dissipation channel 500 penetrates the semiconductor package structure.
Further, in some embodiments, the upper inlet channel and the lower inlet channel are communicated through a connecting channel or through a connecting pipe; in other embodiments, the upper inlet channel and the lower inlet channel are independent of each other.
In the semiconductor packaging structure, when the semiconductor packaging structure works, a cooling liquid lead-in pipe of a cooling device is butted with the vertical liquid inlet 510, the cooling liquid lead-in pipe of the cooling device is butted with the upper liquid inlet 421 and/or the lower liquid inlet 121, cooling liquid is pumped into the upper heat dissipation channel 410, the lower heat dissipation channel 110 and the vertical heat dissipation channel 500 through a cooling pump of the cooling device, and the cooling liquid can be water or other special cooling liquid; when the semiconductor package structure works, the upper heat dissipation channel 410, the lower heat dissipation channel 110 and the vertical heat dissipation channel 500 are all through-flowed with cooling liquid, the flowing cooling liquid exchanges heat with channel walls of the channels, the cooling liquid absorbing heat flows towards the upper liquid outlet 422, the lower liquid outlet 122 and the vertical liquid outlet 520 under the hydraulic action to flow out of the channels, so that the heat of the semiconductor package structure is taken away, the heat dissipation of the semiconductor package structure is realized, and the working performance of the chip 200 is ensured.
In the semiconductor package structure of the present invention, the heat dissipation channels are respectively disposed at the sides of the two larger heat emitting surfaces of the chip 200, that is, the upper heat dissipation channel 410 is disposed at the upper side of the top surface of the chip 200, and the lower heat dissipation channel 110 is disposed at the lower side of the bottom surface of the chip 200, so that heat dissipation can be performed in two directions, and the heat dissipation performance of the semiconductor package structure is improved; moreover, the lower heat dissipation channel 110 is disposed in the chip carrier 100, and since the chip carrier 100 is used for carrying the chip 200, the distance between the lower heat dissipation channel 110 and the chip 200 disposed in the chip carrier 100 is relatively small, so that the heat generated by the chip 200 can be efficiently transferred to the inner wall of the heat dissipation channel, thereby having efficient heat dissipation performance.
In the semiconductor package structure of the present invention, a vertical heat dissipation channel 500 is further provided, and at least a portion of the vertical heat dissipation channel 500 is located in the package colloid 300, so that the heat generated by the chip 200 can be conducted to the package colloid 300, and then the package colloid 300 can be cooled after the vertical heat dissipation channel 500 located in the package colloid 300 is through-flowed with a cooling liquid; through vertical heat dissipation channel 500 has not only increased the total volume of the inside heat dissipation channel of semiconductor package structure, still through vertical heat dissipation channel 500 go up heat dissipation channel 410 with heat dissipation channel 110's cooperation down provides vertical liquid stream water route and horizontal liquid stream water route, and the coolant liquid that flows along different directions can be uniformly right semiconductor package structure cools down to promote semiconductor package structure's heat dispersion.
Further, in another embodiment of the semiconductor package structure of the present invention, in order to facilitate the arrangement of the upper heat dissipation channel 410 in the semiconductor package structure, the semiconductor package structure further includes a metal frame 600, the metal frame 600 is fixed on the top of the encapsulant 300, the plurality of upper heat dissipation channels 410 are arranged in the metal frame 600, and the upper liquid inlet 421 and the upper liquid outlet 422 are located on the side wall of the metal frame 600.
Further, the metal frame 600 includes a vertical frame and a horizontal frame, and the upper heat dissipation channel 410 is formed in the horizontal frame; the vertical frame is fixed on the side wall of the chip carrier 100 through a bonding material, so that a glue filling space is defined among the vertical frame, the top of the chip carrier 100 and the transverse frame, and the glue filling opening is used for filling external packaging materials (such as epoxy resin packaging materials) into the glue filling space; the encapsulating material fills the glue filling space, and forms the encapsulating glue 300 after baking and curing, and the encapsulating glue 300 is combined with the transverse frame.
Further, the metal frame 600 is a copper frame, and the copper frame has good heat conductivity.
In the semiconductor package structure of this embodiment, the metal frame 600 with the upper heat dissipation channel 410 processed therein is adopted, and the metal frame 600 is in close contact with the package colloid 300, so that on the premise of ensuring the heat dissipation performance of the semiconductor package structure, the structure of the upper heat dissipation channel 410 and the lower heat dissipation channel 110 can be pre-processed in the package process, and the processing procedure of the upper heat dissipation channel 410 is not required in the package process, thereby improving the package efficiency.
Further, in another embodiment of the semiconductor package structure of the present invention, in order to improve the heat dissipation effect, the number of the vertical heat dissipation channels 500 is at least two, and a plurality of the vertical heat dissipation channels 500 are arranged around the side of the chip 200 in the horizontal direction.
Further, the chip 200 is located between the vertical heat dissipation channels 500, so that the vertical heat dissipation channels 500 are all disposed close to the chip 200, and thus the heat generated by the chip 200 is efficiently carried out of the semiconductor package structure by the cooling liquid.
Further, in another embodiment of the semiconductor package structure of the present invention, in the height direction of the semiconductor package structure, the lower heat dissipation channel 110 is disposed right below the chip 200, and the upper heat dissipation channel 410 is disposed right above the chip 200; with this arrangement, the upper heat dissipation channel 410 and the lower heat dissipation channel 110 can be closer to the chip 200, and the heat generated by the chip 200 can be more quickly taken out of the semiconductor package structure by the cooling fluid in the upper heat dissipation channel 410 and the lower heat dissipation channel 110.
Further, in another embodiment of the semiconductor package structure of the present invention, a heat dissipation layer is disposed on a channel wall surface of the upper heat dissipation channel 410 and/or the lower heat dissipation channel 110 and/or the vertical heat dissipation channel 500, and the heat dissipation layer is a graphene heat dissipation layer or a carbide heat dissipation layer.
Further, the channel wall surfaces of the upper heat dissipation channel 410, the lower heat dissipation channel 110 and the vertical heat dissipation channel 500 are all plated with graphene heat dissipation layers. With such an arrangement, the heat conduction efficiency of the upper heat dissipation channel 410, the lower heat dissipation channel 110 and the vertical heat dissipation channel 500 can be improved by utilizing the high heat conduction performance of graphene, so that the heat dissipation performance of the semiconductor packaging structure is improved.
Further, in another embodiment of the semiconductor package structure of the present invention, in order to facilitate the fabrication of the vertical heat dissipation channel 500 in the semiconductor package structure, the semiconductor package structure further includes a vertical metal tube 800; the vertical metal tube 800 penetrates the chip carrier 100, the encapsulant 300, and the metal frame 600, and an internal passage of the vertical metal tube 800 is the vertical heat dissipation passage 500.
Specifically, when the semiconductor package structure is manufactured, only through holes need to be processed on the chip carrier 100 and the metal frame 600, then two ends of the vertical metal tube 800 are respectively inserted into the through holes on two sides, and finally the epoxy resin package material is poured into the glue filling space, and the package material is wrapped on the outer wall of the vertical metal tube 800. By adopting the semiconductor packaging structure provided with the vertical metal tube 800, the packaging colloid 300 does not need to be perforated, and the vertical heat dissipation channel 500 can be formed in the semiconductor packaging structure, so that the semiconductor packaging structure is convenient to process and manufacture.
Further, the inner wall of the vertical metal tube 800 is provided with a turbulent flow structure 900.
Further, as shown in fig. 5, the turbulent flow structure 900 is a long bent turbulent flow structure 900, and the turbulent flow structure 900 forms a plurality of bends in the radial direction of the vertical heat dissipation channel 500; when flowing through the vertical heat dissipation channel 500 provided with the turbulent flow structure 900, the cooling liquid can be disturbed to homogenize the temperature in the vertical heat dissipation channel 500, so that the cooling and heat dissipation can be uniformly performed, and the heat dissipation performance of the semiconductor packaging structure is improved.
Further, after the turbulent flow structure 900 is inserted into the vertical metal tube 800, the end of the turbulent flow structure 900 is welded and fixed to the vertical metal tube 800; due to the adoption of the vertical metal tube 800, the turbulent flow structure 900 can be formed in the vertical heat dissipation channel 500 only by welding the end part of the turbulent flow structure 900 to the vertical metal tube 800; the vertical metal tube 800 with the turbulence structure 900 inside can be preprocessed, the vertical metal tube 800 with the turbulence structure 900 can be directly adopted in the packaging process, and the processing step of the turbulence structure 900 is not required to be added in the packaging process, so that the packaging process is simplified, and the UPH is improved.
Further, the vertical metal tube 800 is a copper tube, and the copper tube has good heat conductivity.
Further, in another embodiment of the semiconductor package structure of the present invention, the upper openings 420 and the lower openings 120 are located on the same sidewall of the semiconductor package structure.
Further, the upper liquid inlet 421, the upper liquid outlet 422, the lower liquid inlet 121 and the lower liquid outlet 122 are all located on the same side wall of the semiconductor package structure; with such an arrangement, when the semiconductor package structure is applied, it is convenient to interface a coolant inlet pipe of an external cooling device with the upper liquid inlet 421 and/or the lower liquid inlet 121 so as to introduce coolant into the upper heat dissipation channel 410 and/or the lower heat dissipation channel 110, and interface a coolant outlet pipe of the external cooling device with the upper liquid outlet 422 and/or the lower liquid outlet 122.
The invention also provides a manufacturing method of the semiconductor packaging structure, which can manufacture the semiconductor packaging structure with good heat dissipation performance.
In an embodiment of the method for manufacturing the semiconductor package structure of the present invention, the method includes the following steps:
combining the metal side frames: providing a metal side frame, wherein the metal side frame comprises a vertical frame and a transverse frame which are connected with each other, and the transverse frame is provided with a second vertical through hole and a plurality of upper heat dissipation channels 410 which are transversely arranged; connecting the vertical frame to the circumferential side wall of the chip carrier 100 in a surrounding manner by adopting a bonding material so as to form an injection molding groove capable of containing injection molding materials among the vertical frame, the top of the chip carrier 100 and the transverse frame, wherein the injection molding groove is a glue filling space;
the vertical metal pipe 800 is installed: inserting one end of a vertical metal pipe 800 into the first vertical through hole and inserting the other end into the second vertical through hole;
injection molding: and injecting a packaging adhesive material into the injection molding groove, wherein the maximum height of the injected packaging adhesive material is lower than or level to the top end of the vertical metal pipe 800, and the packaging adhesive is cured and molded to form a packaging body.
Further, after the chip 200 bonding step, a wire bonding step is also included: providing a metal wire 700, wherein one end of the metal wire 700 is soldered to the chip 200, and the other end of the metal wire 700 is soldered to the pin 130 of the chip carrier 100, so as to electrically connect the chip 200 and the pin 130.
Further, in the chip carrier 100 providing step, the chip carrier 100 is a lead frame.
The manufacturing method of the semiconductor packaging structure is used for manufacturing the semiconductor packaging structure with the heat dissipation channels distributed around the chip 200 for the circulation of the cooling liquid, and the manufactured semiconductor packaging structure has good heat dissipation performance.
In the description herein, it is to be understood that the terms "upper", "lower", "left", "right", and the like are used in an orientation or positional relationship based on that shown in the drawings, and are used for convenience of description and simplicity of operation only, and do not indicate or imply that the referenced device or element must have a particular orientation, be constructed in a particular orientation, and be operated, and thus should not be construed as limiting the present invention. Furthermore, the terms "first" and "second" are used merely for descriptive purposes and are not intended to have any special meaning.
In the description herein, references to the description of "an embodiment," "an example" or the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be appropriately combined to form other embodiments as will be appreciated by those skilled in the art.
The technical principle of the present invention is described above in connection with specific embodiments. The description is made for the purpose of illustrating the principles of the invention and should not be construed in any way as limiting the scope of the invention. Based on the explanations herein, those skilled in the art will be able to conceive of other embodiments of the present invention without inventive effort, which would fall within the scope of the present invention.
Claims (10)
1. A semiconductor package structure, comprising:
a chip-carrier (100);
a chip (200) fixed on top of the chip carrier (100);
an encapsulant (300) encapsulating the chip (200) and the chip carrier (100);
a plurality of upper heat dissipation channels (410) laterally disposed within the semiconductor package structure, the upper heat dissipation channels (410) being located above the chip (200);
a number of lower heat dissipation channels (110) laterally disposed within the chip carrier (100);
the vertical heat dissipation channel (500) is vertically arranged in the semiconductor packaging structure, at least one part of the vertical heat dissipation channel (500) is positioned in the packaging colloid (300), and openings at two ends of the vertical heat dissipation channel (500) are communicated with the outside;
an upper opening (420) provided at a sidewall of the semiconductor package structure, the upper heat dissipation channel (410) communicating with the outside through the upper opening (420);
and a lower opening (120) provided at a sidewall of the semiconductor package structure, wherein the lower heat dissipation channel (110) communicates with the outside through the lower opening (120).
2. The semiconductor package structure of claim 1, further comprising a metal frame (600), wherein the metal frame (600) is fixed on the top of the encapsulant (300), and the plurality of upper heat dissipation channels (410) are disposed in the metal frame (600).
3. The semiconductor package structure of claim 1, wherein the number of vertical heat dissipation channels (500) is at least two.
4. The semiconductor package structure of claim 3, wherein the chip (200) is located between a number of the vertical heat dissipation channels (500).
5. The semiconductor package structure of claim 1, wherein the lower heat dissipation channel (110) is disposed directly below the chip (200) and the upper heat dissipation channel (410) is disposed directly above the chip (200) in a height direction of the semiconductor package structure.
6. The semiconductor package structure according to claim 1, wherein a heat dissipation layer is disposed on a channel wall surface of the upper heat dissipation channel (410) and/or the lower heat dissipation channel (110) and/or the vertical heat dissipation channel (500), and the heat dissipation layer is a graphene heat dissipation layer or a carbide heat dissipation layer.
7. The semiconductor package structure of claim 2, further comprising a vertical metal tube (800); the vertical metal tube (800) penetrates through the chip carrier (100), the packaging colloid (300) and the metal frame (600), and an internal channel of the vertical metal tube (800) is the vertical heat dissipation channel (500).
8. The semiconductor package structure of claim 7, wherein an inner wall of the vertical metal tube (800) is provided with a flow disturbing structure (900).
9. The semiconductor package structure of any one of claims 1-6, wherein a number of the upper openings (420) and a number of the lower openings (120) are located on a same sidewall of the semiconductor package structure.
10. A method for manufacturing a semiconductor packaging structure is characterized by comprising the following steps:
chip carrier (100) providing step: providing a chip carrier (100), wherein the chip carrier (100) is internally provided with a transversely arranged lower heat dissipation channel (110), and two ends of the lower heat dissipation channel (110) are communicated with the outside; the chip carrier (100) is also provided with a first vertical through hole;
chip (200) bonding step: providing a chip carrier (100) and a chip (200), and fixing the chip (200) in a carrier core area of the chip carrier (100) by adopting a bonding material;
combining the metal side frames: providing a metal side frame, wherein the metal side frame comprises a vertical frame and a transverse frame which are connected with each other, and the transverse frame is provided with a second vertical through hole and a plurality of upper heat dissipation channels (410) which are transversely arranged; connecting the vertical frame to the circumferential side wall of the chip carrier (100) in a surrounding manner by adopting a bonding material so as to form an injection molding groove capable of containing an injection molding material among the vertical frame, the top of the chip carrier (100) and the transverse frame, wherein the injection molding groove is a glue filling space;
a vertical metal pipe (800) installation step: inserting one end of a vertical metal pipe (800) into the first vertical through hole, and inserting the other end of the vertical metal pipe into the second vertical through hole;
injection molding: and injecting a packaging adhesive material into the injection molding groove, wherein the maximum height of the injected packaging adhesive material is lower than or level to the top end of the vertical metal pipe (800), and the packaging adhesive is cured and molded to form a packaging body.
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Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020192854A1 (en) * | 2001-06-18 | 2002-12-19 | Tzu Johnson C. H. | Method for packing semiconductor die |
| US20140183712A1 (en) * | 2005-02-18 | 2014-07-03 | Utac Hong Kong Limited | Ball grid array package with improved thermal characteristics |
| CN104576573A (en) * | 2014-12-21 | 2015-04-29 | 北京工业大学 | Micro-channel heat exchanger for drop-shaped pin fins |
| CN104681515A (en) * | 2015-03-12 | 2015-06-03 | 中国计量学院 | Novel pressure tube type IGBT water cooling plate |
| CN205897906U (en) * | 2016-07-08 | 2017-01-18 | 广州市耀华电器有限公司 | Heat exchanger of high heat dissipating ability |
| CN106373929A (en) * | 2016-10-18 | 2017-02-01 | 池州脉纬散热器有限责任公司 | Copper pipe embedded water-cooled heat sink |
| CN106449559A (en) * | 2016-10-18 | 2017-02-22 | 池州脉纬散热器有限责任公司 | Turbulent flow water cooling radiator |
| CN107636827A (en) * | 2015-04-13 | 2018-01-26 | Abb瑞士股份有限公司 | Power electronics devices module |
| CN107731764A (en) * | 2017-09-30 | 2018-02-23 | 长电科技（宿迁）有限公司 | A kind of semiconductor package |
| CN108695170A (en) * | 2018-07-13 | 2018-10-23 | 江苏长电科技股份有限公司 | Monomer bimetallic plates encapsulating structure and its packaging method |
| CN109075145A (en) * | 2016-04-15 | 2018-12-21 | 京瓷株式会社 | Semiconductor device |
| CN110663109A (en) * | 2017-05-26 | 2020-01-07 | 三菱电机株式会社 | Semiconductor device with a plurality of semiconductor chips |
-
2020
- 2020-07-16 CN CN202010686205.5A patent/CN111933595A/en active Pending
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020192854A1 (en) * | 2001-06-18 | 2002-12-19 | Tzu Johnson C. H. | Method for packing semiconductor die |
| US20140183712A1 (en) * | 2005-02-18 | 2014-07-03 | Utac Hong Kong Limited | Ball grid array package with improved thermal characteristics |
| CN104576573A (en) * | 2014-12-21 | 2015-04-29 | 北京工业大学 | Micro-channel heat exchanger for drop-shaped pin fins |
| CN104681515A (en) * | 2015-03-12 | 2015-06-03 | 中国计量学院 | Novel pressure tube type IGBT water cooling plate |
| CN107636827A (en) * | 2015-04-13 | 2018-01-26 | Abb瑞士股份有限公司 | Power electronics devices module |
| CN109075145A (en) * | 2016-04-15 | 2018-12-21 | 京瓷株式会社 | Semiconductor device |
| CN205897906U (en) * | 2016-07-08 | 2017-01-18 | 广州市耀华电器有限公司 | Heat exchanger of high heat dissipating ability |
| CN106373929A (en) * | 2016-10-18 | 2017-02-01 | 池州脉纬散热器有限责任公司 | Copper pipe embedded water-cooled heat sink |
| CN106449559A (en) * | 2016-10-18 | 2017-02-22 | 池州脉纬散热器有限责任公司 | Turbulent flow water cooling radiator |
| CN110663109A (en) * | 2017-05-26 | 2020-01-07 | 三菱电机株式会社 | Semiconductor device with a plurality of semiconductor chips |
| CN107731764A (en) * | 2017-09-30 | 2018-02-23 | 长电科技（宿迁）有限公司 | A kind of semiconductor package |
| CN108695170A (en) * | 2018-07-13 | 2018-10-23 | 江苏长电科技股份有限公司 | Monomer bimetallic plates encapsulating structure and its packaging method |
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Application publication date: 20201113 |