CN101950726B - First-coating last-etching single package method for positively packaging double-sided graphic chip - Google Patents
First-coating last-etching single package method for positively packaging double-sided graphic chip Download PDFInfo
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- CN101950726B CN101950726B CN2010102730015A CN201010273001A CN101950726B CN 101950726 B CN101950726 B CN 101950726B CN 2010102730015 A CN2010102730015 A CN 2010102730015A CN 201010273001 A CN201010273001 A CN 201010273001A CN 101950726 B CN101950726 B CN 101950726B
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- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/32257—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the layer connector connecting to a bonding area disposed in a recess of the surface of the item
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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Abstract
The invention relates to a first-coating last-etching single package method for positively packaging a double-sided graphic chip. The method comprises the following technical steps: taking a metal substrate; plating a metal layer to coat the metal substrate; carrying out backside etching on the metal substrate; enveloping plastic pacing material (epoxy resin) without filler on the backside of the metal substrate; carrying out positive etching on the metal substrate; etching the positive sides of a basic island and a pin, wherein the backside sizes of the basic island and the pin are smaller than the positive sizes of the basic island and the pin to form a basic inland and pin structure with big top and small bottom; loading pieces; routing metal wires; enveloping local units by using plastic pacing material (epoxy resin) with filler on the positive side of the semi-finished product to ensure local unit areas on the positive side of the pin to expose the plastic pacing material (epoxy resin) with filler; plating metal layers on the backsides of the island and the pin and the positive side of the pin for coating; and cutting. The package structure of the chip prepared by the method of the invention does not have the problem of falling feet, and the length of the metal wires is shortened.
Description
(1) technical field
The present invention relates to first plating of a kind of two-sided graphic chips formal dress and afterwards carve single method for packing.Belong to the semiconductor packaging field.
(2) background technology
The production method of traditional chip-packaging structure is: after chemical etching and surface electrical coating are carried out in the front of employing metal substrate, promptly accomplish the making (shown in figure 43) of lead frame.Etching is then carried out at the back side of lead frame again in encapsulation process.Not enough below this method exists:
Because only carried out the work that etches partially before the plastic packaging in the metal substrate front; And plastic packaging material only wraps the height of half pin of pin in the plastic packaging process; So the constraint ability of plastic-sealed body and pin has just diminished; When if the plastic-sealed body paster is not fine to pcb board, does over again again and heavily paste, with regard to the problem (shown in figure 44) that is easy to generate pin.Especially the kind of plastic packaging material is to adopt when filler is arranged; Because material is at the environment and the follow-up surface-pasted stress changing relation of production process; Can cause metal and plastic packaging material to produce the crack of vertical-type, its characteristic is the high more then crisp more firmly more crack that is easy to generate more of proportion of filler.
In addition, because the distance between chip and the pin is far away, the length of metal wire is longer, shown in Figure 45～46, and metal wire cost higher (the especially metal wire of expensive proof gold matter); Same because the length of metal wire is longer, make that the signal output speed of chip is slow (especially the product of storage class and the calculating that needs mass data are more outstanding); Too because the length of metal wire is longer, so also higher to the interference of signal in existing dead resistance/parasitic capacitance of metal wire and parasitic electric pole; Because the distance between chip and the pin is far away, make that the volume and the area of encapsulation are bigger again, material cost is higher, and discarded object is more.
(3) summary of the invention
The objective of the invention is to overcome above-mentioned deficiency, provide a kind of and do not have again first plating of two-sided graphic chips formal dress of problem that produces pin and the contraction in length that can make metal wire afterwards to carve single method for packing.
The objective of the invention is to realize like this: a kind of two-sided graphic chips formal dress plates earlier afterwards carves single method for packing, and said method comprises following processing step:
Get the suitable metal substrate of a slice thickness,
Utilization by coating equipment in the front of metal substrate and the back side be covered respectively and can carry out the photoresistance glued membrane of exposure imaging, protecting follow-up electroplated metal layer process operation,
The positive photoresistance glued membrane of step 3, metal substrate needs the exposure of plated metal layer region/develop and windows
The metal substrate front that utilizes exposure imaging equipment that step 2 is accomplished photoresistance glued membrane lining operation is carried out exposure imaging and is removed part photoresistance glued membrane, carries out the zone of electroplated metal layer to expose the positive follow-up needs of metal substrate,
The zone of having windowed in step 4, metal substrate front is carried out metal level and is electroplated lining
The first metal layer plating lining is carried out in zone to having windowed in metal substrate front in the step 3, and this first metal layer places the front of said Ji Dao and pin,
Photoresistance glued membrane striping is carried out at step 5, metal substrate front and the back side
The positive remaining photoresistance glued membrane of metal substrate and the photoresistance glued membrane at the metal substrate back side are all removed,
Utilization by coating equipment in the front of metal substrate and the back side be covered respectively and can carry out the photoresistance glued membrane of exposure imaging, protecting follow-up etch process operation,
The photoresistance glued membrane at step 7, the metal substrate back side needs the exposure of etching area/develop and windows
Exposure imaging removal part photoresistance glued membrane is carried out at the metal substrate back side that utilizes exposure imaging equipment that step 6 is accomplished photoresistance glued membrane lining operation, prepares against the metal substrate back etched operation that follow-up needs carry out to expose the localized metallic substrate,
After the exposure/development and windowing task of completing steps seven, promptly carry out the etching operation of each figure, etch the back side of Ji Dao and pin, simultaneously the pin front is extended to next door, basic island as much as possible at the back side of metal substrate,
Photoresistance glued membrane striping is carried out at step 9, metal substrate front and the back side
The photoresistance glued membrane that the metal substrate front and back is remaining all removes,
Packless plastic packaging material (epoxy resin) operation is sealed at the metal substrate back side of completing steps nine said striping operations; And carry out the curing operation after plastic packaging material is sealed; Make the peripheral zone of Ji Dao and pin; Packless plastic packaging material (epoxy resin) is all set in zone and the zone between pin and the pin between pin and the basic island; This packless plastic packaging material (epoxy resin) is peripheral with Ji Dao and pin bottom; Pin bottom and Ji Dao bottom and pin bottom and pin bottom link into an integrated entity
Utilization by coating equipment in the front that will accomplish the metal substrate of sealing the operation of no filler plastic packaging material and the back side be covered respectively and can carry out the photoresistance glued membrane of exposure imaging, protecting follow-up etch process operation,
Exposure imaging removal part photoresistance glued membrane is carried out in the metal substrate front of sealing the operation of no filler plastic packaging material of accomplishing that utilizes exposure imaging equipment that step 11 is accomplished photoresistance glued membrane lining operation, carries out the operation of metal substrate front-side etch in order to follow-up needs,
After the exposure/development and windowing task of completing steps 12; Promptly carry out the etching operation of each figure in the metal substrate front that the operation of no filler plastic packaging material is sealed in completion; Etch the front of Ji Dao and pin; And make the positive size of the back side size of said Ji Dao and pin, form up big and down small Ji Dao and pin configuration less than Ji Dao and pin
Photoresistance glued membrane striping is carried out at step 14, metal substrate front and the back side
The positive remaining photoresistance glued membrane of the metal substrate of completing steps 13 etching operations and the photoresistance glued membrane at the metal substrate back side are all removed, process lead frame,
Step 15, load
On the first metal layer of front, basic island, carry out the implantation of chip through conduction or non-conductive bonding material,
The semi-finished product of accomplishing chip implantation operation are carried out playing the metal wire operation between chip front side and the pin front the first metal layer,
The semi-finished product front that routing is accomplished is carried out local unit and is encapsulated with filler plastic packaging material (epoxy resin) operation; The positive local unit of pin zone is exposed filler plastic packaging material (epoxy resin) is arranged; And carry out the curing operation after plastic packaging material is sealed; Make top and chip and the metal wire of Ji Dao and pin all had filler plastic packaging material (epoxy resin) to seal outward
The back side of step 10 eight, Ji Dao and pin and the front of pin are carried out metal level and are electroplated lining
Completing steps 17 being encapsulated with the said positive local unit of the pin zones that filler plastic packaging material (epoxy resin) is arranged of exposing of the back side and the step 10 seven of said Ji Dao and pin of filler plastic packaging material (epoxy resin) operation carries out second metal level and the first metal layer respectively and electroplates the operation that is covered
The semi-finished product of ten eight the second metal levels of completing steps being electroplated lining carry out cutting operation, make originally more than of chips that connect together with array formula aggregate mode independent, make single encapsulating structure finished product of two-sided graphic chips formal dress.
The invention has the beneficial effects as follows:
1, guarantees not have again the problem that produces pin
Because lead frame has adopted two-sided etched technology; So planning and designing easily with produce up big and down small pin configuration; The levels plastic packaging material is wrapped up big and down small pin configuration closely together; So the constraint ability of plastic-sealed body and pin just becomes big, do not have the problem that produces pin again.
2, guarantee the contraction in length of metal wire
1) separates etched technology owing to used the lead frame back side with the front; So can extend to the follow-up next door, zone that needs cartridge chip as much as possible by the pin that lead frame is positive; Impel chip and pin distance significantly to shorten; Like Fig. 2～Fig. 3, so the length of metal wire has also shortened, and the cost of metal wire also can significantly reduce (the especially metal wire of expensive proof gold matter);
2) also because the contraction in length of metal wire makes also significantly speedup (the especially product of storage class and the calculating that needs mass data of signal output speed of chip; More outstanding); Because the length of metal wire has shortened, so existing dead resistance/parasitic capacitance of metal wire and parasitic electric pole are to the also significantly reduction of interference of signal.
3, the volume of encapsulation and area can significantly be dwindled
Because of having used the elongation technology of pin,, make the volume and the area of encapsulation significantly to dwindle so can be easy to produce the distance between high pin number and highdensity pin and the pin.
4, material cost and material usage reduce
Because volume after being encapsulated is significantly dwindled, more directly embody material cost significantly descend with because the minimizing of material usage also significantly reduces the puzzlement of discarded object environmental protection.
5, adopt the advantage of single encapsulation of local unit to have:
1) in different application, can the pin at plastic-sealed body edge be stretched out plastic-sealed body.
2) pin at plastic-sealed body edge stretches out outside the plastic-sealed body and can clearly check out situation about being welded on the pcb board.
3) area of modular type than the easy because multiple material different shrinkage that structure produces of conference different should stand distortion, and single encapsulation of local unit just can disperse fully multiple material different shrinkage that structure produces different should stand distortion.
4) single is encapsulated in when carrying out the plastic-sealed body cutting and separating; Because the thickness that cuts has only the thickness of pin; So the speed of cutting can be come much soon than the encapsulating structure of modular type, so and incisory blade because the thickness of cutting just approached life-span of cutting blade relative also just become longer.
(4) description of drawings
Fig. 1 (A)～Fig. 1 (R) afterwards carves single method for packing embodiment 1 each operation sketch map for the two-sided graphic chips formal dress of the present invention plates earlier.
Fig. 2 is single encapsulating structure embodiment 1 structural representation of the two-sided graphic chips formal dress of the present invention.
Fig. 3 is the vertical view of Fig. 2.
Fig. 4 (A)～Fig. 4 (R) afterwards carves single method for packing embodiment 2 each operation sketch map for the two-sided graphic chips formal dress of the present invention plates earlier.
Fig. 5 is single encapsulating structure embodiment 2 structural representations of the two-sided graphic chips formal dress of the present invention.
Fig. 6 is the vertical view of Fig. 5.
Fig. 7 (A)～Fig. 7 (R) afterwards carves single method for packing embodiment 3 each operation sketch map for the two-sided graphic chips formal dress of the present invention plates earlier.
Fig. 8 is single encapsulating structure embodiment 3 structural representations of the two-sided graphic chips formal dress of the present invention.
Fig. 9 is the vertical view of Fig. 8.
Figure 10 (A)～Figure 10 (R) afterwards carves single method for packing embodiment 4 each operation sketch map for the two-sided graphic chips formal dress of the present invention plates earlier.
Figure 11 is single encapsulating structure embodiment 4 structural representations of the two-sided graphic chips formal dress of the present invention.
Figure 12 is the vertical view of Figure 11.
Figure 13 (A)～Figure 13 (R) afterwards carves single method for packing embodiment 5 each operation sketch map for the two-sided graphic chips formal dress of the present invention plates earlier.
Figure 14 is single encapsulating structure embodiment 5 structural representations of the two-sided graphic chips formal dress of the present invention.
Figure 15 is the vertical view of Figure 14.
Figure 16 (A)～Figure 16 (R) afterwards carves single method for packing embodiment 6 each operation sketch map for the two-sided graphic chips formal dress of the present invention plates earlier.
Figure 17 is single encapsulating structure embodiment 6 structural representations of the two-sided graphic chips formal dress of the present invention.
Figure 18 is the vertical view of Figure 17.
Figure 19 (A)～Figure 19 (R) afterwards carves single method for packing embodiment 7 each operation sketch map for the two-sided graphic chips formal dress of the present invention plates earlier.
Figure 20 is single encapsulating structure embodiment 7 structural representations of the two-sided graphic chips formal dress of the present invention.
Figure 21 is the vertical view of Figure 20.
Figure 22 (A)～Figure 22 (R) afterwards carves single method for packing embodiment 8 each operation sketch map for the two-sided graphic chips formal dress of the present invention plates earlier.
Figure 23 is single encapsulating structure embodiment 8 structural representations of the two-sided graphic chips formal dress of the present invention.
Figure 24 is the vertical view of Figure 23.
Figure 25 (A)～Figure 25 (R) afterwards carves single method for packing embodiment 5 each operation sketch map for the two-sided graphic chips formal dress of the present invention plates earlier.
Figure 26 is single encapsulating structure embodiment 5 structural representations of the two-sided graphic chips formal dress of the present invention.
Figure 27 is the vertical view of Figure 26.
Figure 28 (A)～Figure 28 (R) afterwards carves single method for packing embodiment 6 each operation sketch map for the two-sided graphic chips formal dress of the present invention plates earlier.
Figure 29 is single encapsulating structure embodiment 6 structural representations of the two-sided graphic chips formal dress of the present invention.
Figure 30 is the vertical view of Figure 29.
Figure 31 (A)～Figure 31 (R) afterwards carves single method for packing embodiment 11 each operation sketch map for the two-sided graphic chips formal dress of the present invention plates earlier.
Figure 32 is single encapsulating structure embodiment 11 structural representations of the two-sided graphic chips formal dress of the present invention.
Figure 33 is the vertical view of Figure 32.
Figure 34 (A)～Figure 34 (R) afterwards carves single method for packing embodiment 12 each operation sketch map for the two-sided graphic chips formal dress of the present invention plates earlier.
Figure 35 is single encapsulating structure embodiment 12 structural representations of the two-sided graphic chips formal dress of the present invention.
Figure 36 is the vertical view of Figure 35.
Figure 37 (A)～Figure 37 (R) afterwards carves single method for packing embodiment 13 each operation sketch map for the two-sided graphic chips formal dress of the present invention plates earlier.
Figure 38 is single encapsulating structure embodiment 13 structural representations of the two-sided graphic chips formal dress of the present invention.
Figure 39 is the vertical view of Figure 38.
Figure 40 (A)～Figure 40 (R) afterwards carves single method for packing embodiment 14 each operation sketch map for the two-sided graphic chips formal dress of the present invention plates earlier.
Figure 41 is single encapsulating structure embodiment 14 structural representations of the two-sided graphic chips formal dress of the present invention.
Figure 42 is the vertical view of Figure 41.
Figure 43 was for to adopt the front of metal substrate to carry out chemical etching and surface electrical coating flow diagram in the past.
Figure 44 pin figure for what formed in the past.
Figure 45 is an encapsulating structure sketch map in the past.
Figure 46 is 45 vertical view.
Reference numeral among the figure:
The 1.3, the 4th basic island 1.4, the 1.2, the 3rd basic island, the 1.1, the 3rd basic island, the 3rd basic island.
(5) embodiment
The two-sided graphic chips formal dress of the present invention plates earlier that afterwards to carve single method for packing following:
Embodiment 1: single basic island individual pen pin
Referring to Fig. 2 and Fig. 3, Fig. 2 is single encapsulating structure embodiment 1 structural representation of the two-sided graphic chips formal dress of the present invention.Fig. 3 is the vertical view of Fig. 2.Can find out by Fig. 2 and Fig. 3; Single encapsulating structure of the two-sided graphic chips formal dress of the present invention; Comprise basic island 1, pin 2, packless plastic packaging material (epoxy resin) 3, conduction or non-conductive bonding material 6, chip 7, metal wire 8 and filler plastic packaging material (epoxy resin) 9 is arranged; Said pin 2 fronts extend to 1 next door, basic island as much as possible; Front at said basic island 1 and pin 2 is provided with the first metal layer 4; The back side at said basic island 1 and pin 2 is provided with second metal level 5; On the 1 front the first metal layer 4 of said basic island, be provided with chip 7 through conduction or non-conductive bonding material 6; Chip 7 positive with pin 2 front the first metal layers 4 between be connected with metal wire 8, outside the top of said basic island 1 and pin 2 and chip 7 and metal wire 8, be encapsulated with filler plastic packaging material (epoxy resin) 9, this has filler plastic packaging material (epoxy resin) 9 that pin 2 positive local unit are coated; Zone between zone, pin 2 and the basic island 1 of said basic island 1 and pin 2 peripheries and the zone between pin 2 and the pin 2 are equipped with packless plastic packaging material (epoxy resin) 3; Said packless plastic packaging material (epoxy resin) 3 is peripheral with basic island 1 and pin bottom, pin 2 bottoms and 1 bottom, basic island and pin 2 bottoms and pin 2 bottoms link into an integrated entity, and makes said Ji Dao and pin back side size less than Ji Dao and pin front size, forms up big and down small Ji Dao and pin configuration.
Its method for packing is following:
Referring to Fig. 1 (A), get the suitable metal substrate of a slice thickness 10.The material of metal substrate can be carried out conversion according to the function and the characteristic of chip, for example: copper, aluminium, iron, copper alloy or dilval etc.
Referring to Fig. 1 (B), utilize by coating equipment in the front of metal substrate and the back side be covered respectively and can carry out the photoresistance glued membrane 11 and 12 of exposure imaging, to protect follow-up electroplated metal layer process operation.And this photoresistance glued membrane can be a dry type photoresistance pellicle also can be wet type photoresistance glued membrane.
The positive photoresistance glued membrane of step 3, metal substrate needs the exposure of plated metal layer region/develop and windows
Referring to Fig. 1 (C), the metal substrate front that utilizes exposure imaging equipment that step 2 is accomplished photoresistance glued membrane lining operation is carried out exposure imaging and is removed part photoresistance glued membrane, carries out the zone of electroplated metal layer to expose the positive follow-up needs of metal substrate.
The zone of having windowed in step 4, metal substrate front is carried out metal level and is electroplated lining
Referring to Fig. 1 (D), the first metal layer 4 plating linings are carried out in the zone of having windowed in metal substrate front in the step 3, this first metal layer 4 places the front of said basic island 1 and pin 2.
Photoresistance glued membrane striping is carried out at step 5, metal substrate front and the back side
Referring to Fig. 1 (E), the positive remaining photoresistance glued membrane of metal substrate and the photoresistance glued membrane at the metal substrate back side are all removed.
Referring to Fig. 1 (F), utilize by coating equipment in the front of metal substrate and the back side be covered respectively and can carry out the photoresistance glued membrane 13 and 14 of exposure imaging, to protect follow-up etch process operation.And this photoresistance glued membrane can be a dry type photoresistance pellicle also can be wet type photoresistance glued membrane.
The photoresistance glued membrane at step 7, the metal substrate back side needs the exposure of etching area/develop and windows
Referring to Fig. 1 (G), exposure imaging removal part photoresistance glued membrane is carried out at the metal substrate back side that utilizes exposure imaging equipment that step 6 is accomplished photoresistance glued membrane lining operation, to expose the metal substrate back etched operation that the localized metallic substrate carries out in order to follow-up needs.
Referring to Fig. 1 (H), after the exposure/development and windowing task of completing steps seven, promptly carry out the etching operation of each figure at the back side of metal substrate, etch the back side of basic island 1 and pin 2, simultaneously the pin front is extended to next door, basic island as much as possible.
Photoresistance glued membrane striping is carried out at step 9, metal substrate front and the back side
Referring to Fig. 1 (I), the photoresistance glued membrane that the metal substrate front and back is remaining all removes.
Referring to Fig. 1 (J); Packless plastic packaging material (epoxy resin) operation is sealed at the metal substrate back side of completing steps nine said striping operations; And carry out the curing operation after plastic packaging material is sealed; Make zone and the zone between pin 2 and the pin 2 between basic island 1 and pin 2 peripheral zone, pin 2 and the basic island 1 all set packless plastic packaging material (epoxy resin) 3, this packless plastic packaging material (epoxy resin) 3 links into an integrated entity basic island 1 and periphery, pin bottom, pin 2 bottoms and 1 bottom, basic island and pin 2 bottoms and pin 2 bottoms.
Referring to Fig. 1 (K), utilize by coating equipment in the front that will accomplish the metal substrate of sealing the operation of no filler plastic packaging material and the back side be covered respectively and can carry out the photoresistance glued membrane 15 and 16 of exposure imaging, to protect follow-up etch process operation.And this photoresistance glued membrane can be a dry type photoresistance pellicle also can be wet type photoresistance glued membrane.
Referring to Fig. 1 (L); Exposure imaging removal part photoresistance glued membrane is carried out in the metal substrate front of sealing the operation of no filler plastic packaging material of accomplishing that utilizes exposure imaging equipment that step 11 is accomplished photoresistance glued membrane lining operation, carries out the operation of metal substrate front-side etch in order to follow-up needs.
Referring to Fig. 1 (M); After the exposure/development and windowing task of completing steps 12; Promptly carry out the etching operation of each figure in the metal substrate front that the operation of no filler plastic packaging material is sealed in completion; Etch the front of basic island 1 and pin 2, and make the positive size of the back side size of said basic island 1 and pin 2, form up big and down small basic island 1 and pin 2 structures less than basic island 1 and pin 2.
Photoresistance glued membrane striping is carried out at step 14, metal substrate front and the back side
Referring to Fig. 1 (N), the positive remaining photoresistance glued membrane of the metal substrate of completing steps 13 etching operations and the photoresistance glued membrane at the metal substrate back side are all removed, process lead frame.
Step 15, load
Referring to Fig. 1 (O), on the 1 front the first metal layer 4 of basic island, carry out the implantation of chip 7 through conduction or non-conductive bonding material 6.
Referring to Fig. 1 (P), the semi-finished product of accomplishing chip implantation operation are carried out playing metal wire 8 operations between chip front side and the pin front the first metal layer.
Referring to Fig. 1 (Q); The semi-finished product front that routing is accomplished is carried out local unit and is encapsulated with 9 operations of filler plastic packaging material; Pin 2 positive local unit zones are exposed filler plastic packaging material (epoxy resin) 9 is arranged; And carry out the curing operation after plastic packaging material is sealed, make top and the chip of Ji Dao and pin and metal wire all had filler plastic packaging material (epoxy resin) to seal outward.
The back side of step 10 eight, Ji Dao and pin and the front of pin are carried out metal level and are electroplated lining
Referring to Fig. 1 (R); Completing steps 17 is encapsulated with the said pin 2 positive local unit zones that filler plastic packaging material (epoxy resin) 9 is arranged of exposing of the back side and the step 10 seven of said Ji Dao and pin of filler plastic packaging material (epoxy resin) operation and carries out second metal level 5 respectively and electroplate the lining operations, and the material of electroplating can be tin, nickel gold, NiPdAu with the first metal layer 4 .... wait metal material.
Referring to Fig. 2 and Fig. 3, the semi-finished product of ten eight the second metal levels of completing steps being electroplated lining carry out cutting operation, make originally more than of chips that connect together with array formula aggregate mode independent, make single encapsulating structure finished product of two-sided graphic chips formal dress.
Embodiment 2: base island exposed type individual pen pin sinks
Referring to Fig. 4～6, Fig. 4 (A)～Fig. 4 (R) afterwards carves single method for packing embodiment 2 each operation sketch map for the two-sided graphic chips formal dress of the present invention plates earlier.Fig. 5 is single encapsulating structure embodiment 2 structural representations of the two-sided graphic chips formal dress of the present invention.Fig. 6 is the vertical view of Fig. 5.Can be found out that by Fig. 4, Fig. 5 and Fig. 6 embodiment 2 only is with the difference of embodiment 1: said basic island 1 is sinking type Ji Dao, and promptly basic island 1 front middle section sinks.
Embodiment 3: baried type base island individual pen pin
Referring to Fig. 7～9, Fig. 7 (A)～Fig. 7 (R) afterwards carves single method for packing embodiment 3 each operation sketch map for the two-sided graphic chips formal dress of the present invention plates earlier.Fig. 8 is single encapsulating structure embodiment 3 structural representations of the two-sided graphic chips formal dress of the present invention.Fig. 9 is the vertical view of Fig. 8.Can be found out that by Fig. 7, Fig. 8 and Fig. 9 embodiment 3 only is with the difference of embodiment 1: said basic island 1 is baried type Ji Dao, and 1 back side, promptly basic island is imbedded in the said packless plastic packaging material (epoxy resin) 3.
Embodiment 4: the base island exposed type individual pen of multi-convex point pin
Referring to Figure 10～12, Figure 10 (A)～Figure 10 (R) afterwards carves single method for packing embodiment 4 each operation sketch map for the two-sided graphic chips formal dress of the present invention plates earlier.Figure 11 is single encapsulating structure embodiment 4 structural representations of the two-sided graphic chips formal dress of the present invention.Figure 12 is the vertical view of Figure 11.Can be found out that by Figure 10, Figure 11 and Figure 12 embodiment 4 only is with the difference of embodiment 1: said basic island 1 is multi-convex point Ji Dao, and 1 surface, promptly basic island is provided with a plurality of salient points.
Embodiment 5: a plurality of base island exposed type individual pen pins
Referring to Figure 13～15, Figure 13 (A)～Figure 13 (R) afterwards carves single method for packing embodiment 5 each operation sketch map for the two-sided graphic chips formal dress of the present invention plates earlier.Figure 14 is single encapsulating structure embodiment 5 structural representations of the two-sided graphic chips formal dress of the present invention.Figure 15 is the vertical view of Figure 14.Can find out that by Figure 13～15 embodiment 5 is with the difference of embodiment 1: said basic island 1 has a plurality of, and pin 2 has individual pen.
Embodiment 6: the base island exposed type individual pen of a plurality of sinkings pin
Referring to Figure 16～18, Figure 16 (A)～Figure 16 (R) afterwards carves single method for packing embodiment 6 each operation sketch map for the two-sided graphic chips formal dress of the present invention plates earlier.Figure 17 is single encapsulating structure embodiment 6 structural representations of the two-sided graphic chips formal dress of the present invention.Figure 18 is the vertical view of Figure 17.Can find out that by Figure 16～18 embodiment 6 is with the difference of embodiment 2: said basic island 1 has a plurality of, and pin 2 has individual pen.
Embodiment 7: a plurality of baried type bases island individual pen pin
Referring to Figure 19～21, Figure 19 (A)～Figure 19 (R) afterwards carves single method for packing embodiment 7 each operation sketch map for the two-sided graphic chips formal dress of the present invention plates earlier.Figure 20 is single encapsulating structure embodiment 7 structural representations of the two-sided graphic chips formal dress of the present invention.Figure 21 is the vertical view of Figure 20.Can find out that by Figure 19～21 embodiment 7 is with the difference of embodiment 3: said basic island 1 has a plurality of, and pin 2 has individual pen.
Embodiment 8: the base island exposed type individual pen of a plurality of multi-convex points pin
Referring to Figure 22～24, Figure 22 (A)～Figure 22 (R) afterwards carves single method for packing embodiment 8 each operation sketch map for the two-sided graphic chips formal dress of the present invention plates earlier.Figure 23 is single encapsulating structure embodiment 8 structural representations of the two-sided graphic chips formal dress of the present invention.Figure 24 is the vertical view of Figure 23.Can find out that by Figure 22～24 embodiment 8 is with the difference of embodiment 4: said basic island 1 has a plurality of, and pin 2 has individual pen.
Embodiment 9: the base island exposed type and the base island exposed type individual pen pin that sinks
Referring to Figure 25～27, Figure 25 (A)～Figure 25 (R) afterwards carves single method for packing embodiment 9 each operation sketch map for the two-sided graphic chips formal dress of the present invention plates earlier.Figure 26 is single encapsulating structure embodiment 9 structural representations of the two-sided graphic chips formal dress of the present invention.Figure 27 is the vertical view of Figure 26.Can find out by Figure 25～27; Embodiment 9 is with the difference of embodiment 1: said basic island 1 has two groups also can be many group Ji Dao; One group is the first basic island 1.1; Another group is the second basic island 1.2; The said second basic island 1.2 front middle sections sink; Front at the said first basic island 1.1 and pin 2 is provided with the first metal layer 4; The back side at said first 1.1, the second basic island 1.2, basic island and pin 2 is provided with second metal level 5; Through conduction or non-conductive bonding material 6 chip 7 is set in the second basic island 1.2 positive central sunken regions and 1.1 fronts, the first basic island, chip 7 positive with pin 2 front the first metal layers 4 between and all be connected between chip 7 and the chip 7 with metal wire 8, no filler plastic packaging material 3 is set in zone between zone, the second basic island 1.2 and pin 2 between zone, the first basic island 1.1 and the second basic island 1.2 between zone, pin 2 and the first basic island 1.1 of said pin 2 peripheries and the zone between pin 2 and the pin 2; Said no filler plastic packaging material 3 links into an integrated entity with pin 2 bottoms and pin 2 periphery, pin bottom, pin 2 and 1.1 bottoms, the first basic island, the first basic island 1.1 and 1.2 bottoms, the second basic island, the second basic island 1.2 with pin 2 bottoms, said pin 2 has individual pen.
Embodiment 10: base island exposed type and baried type base island individual pen pin
Referring to Figure 28～30, Figure 28 (A)～Figure 28 (R) afterwards carves single method for packing embodiment 10 each operation sketch map for the two-sided graphic chips formal dress of the present invention plates earlier.Figure 29 is single encapsulating structure embodiment 10 structural representations of the two-sided graphic chips formal dress of the present invention.Figure 30 is the vertical view of Figure 29.Can find out by Figure 28～30; Embodiment 10 is with the difference of embodiment 1: said basic island 1 has two groups also can be many group Ji Dao; One group is the first basic island 1.1; Another group is the 3rd basic island 1.3; Front at said first the 3rd basic island 1.3, basic island 1.1 and pin 2 is provided with the first metal layer 4; The back side at the said first basic island 1.1 and pin 2 is provided with second metal level 5; Chip 7 positive with pin 2 front the first metal layers 4 between and all be connected between chip 7 and the chip 7 with metal wire 8; No filler plastic packaging material 3 is set in zone and the zone between pin and the pin between zone, the 3rd basic island 1.3 and pin 2 between zone, 1.3 back sides, the 3rd basic island, the 3rd basic island 1.3 and the first basic island 1.1 between zone, pin 2 and the first basic island 1.1 of said pin 2 peripheries, and said no filler plastic packaging material 3 links into an integrated entity periphery, pin bottom, pin 2 and 1.1 bottoms, the first basic island, 1.3 back sides, the 3rd basic island, the 3rd 1.3 back sides, basic island and 1.1 bottoms, the first basic island, the 3rd 1.3 back sides, basic island and pin 2 bottoms and pin 2 with pin 2 bottoms, and said pin 2 is provided with individual pen.
Embodiment 11: the base island exposed type individual pen of base island exposed type and multi-convex point pin
Referring to Figure 31～33, Figure 31 (A)～Figure 31 (R) afterwards carves single method for packing embodiment 11 each operation sketch map for the two-sided graphic chips formal dress of the present invention plates earlier.Figure 32 is single encapsulating structure embodiment 11 structural representations of the two-sided graphic chips formal dress of the present invention.Figure 33 is the vertical view of Figure 32.Can find out by Figure 31～33; Embodiment 11 is with the difference of embodiment 1: said basic island 1 has two groups also can be many group Ji Dao; One group is the first basic island 1.1; Another group is the 4th basic island 1.4; Multi-convex point shape structure is arranged in 1.4 fronts, the said the 4th basic island; No filler plastic packaging material 3 is set in zone between zone, the 4th basic island 1.4 and pin 2 between zone, the first basic island 1.1 and the 4th basic island 1.4 between zone, pin 2 and the first basic island 1.1 of said pin 2 peripheries and the zone between pin 2 and the pin 2, and said packless plastic packaging material (epoxy resin) 3 links into an integrated entity with pin 2 bottoms and pin 2 periphery, pin bottom, pin 2 and 1.1 bottoms, the first basic island, the first basic island 1.1 and 1.4 bottoms, the 4th basic island, the 4th basic island 1.4 with pin 2 bottoms, and said pin 2 is provided with individual pen.
Embodiment 12: the base island exposed type individual pen of base island exposed type and baried type pin sinks
Referring to Figure 34～36, Figure 34 (A)～Figure 34 (R) afterwards carves single method for packing embodiment 12 each operation sketch map for the two-sided graphic chips formal dress of the present invention plates earlier.Figure 35 is single encapsulating structure embodiment 12 structural representations of the two-sided graphic chips formal dress of the present invention.Figure 36 is the vertical view of Figure 35.Can find out by Figure 34～36; Embodiment 12 is with the difference of embodiment 1: said basic island 1 has two groups also can be many group Ji Dao; One group is the second basic island 1.2; Another group is the 3rd basic island 1.3; The said second basic island 1.2 front middle sections sink; Through conduction or non-conductive bonding material 6 chip 7 is set in the second basic island 1.2 positive central sunken regions and 1.3 fronts, the 3rd basic island; No filler plastic packaging material 3 is set in zone and the zone between pin and the pin between zone, the 3rd 1.3 back sides, basic island and pin 2 between zone, 1.3 back sides, the 3rd basic island, the second Ji Dao back side 1.2 and the second basic island 1.2 between zone, pin 2 and the second basic island 1.2 of said pin 2 peripheries, and said no filler plastic packaging material 3 links into an integrated entity periphery, pin bottom, pin 2 and 1.2 bottoms, the second basic island, the 3rd the 1.3, the 3rd basic island 1.3, basic island and 1.2 bottoms, the second basic island, the 3rd 1.3 back sides, basic island and pin 2 bottoms and pin 2 with pin 2 bottoms, and said pin 2 is provided with a circle.
Embodiment 13: the base island exposed type individual pen of base island exposed type and multi-convex point pin sinks
Referring to Figure 37～39, Figure 37 (A)～Figure 37 (R) afterwards carves single method for packing embodiment 13 each operation sketch map for the two-sided graphic chips formal dress of the present invention plates earlier.Figure 38 is single encapsulating structure embodiment 13 structural representations of the two-sided graphic chips formal dress of the present invention.Figure 39 is the vertical view of Figure 38.Can find out by Figure 37～39; Embodiment 13 is with the difference of embodiment 1: said basic island 1 has two groups also can be many group Ji Dao; One group is the second basic island 1.2; Another group is the 4th basic island 1.4; The said second basic island 1.2 front middle sections sink; Multi-convex point shape structure is arranged in 1.4 fronts, the 4th basic island; Front at the said the 4th basic island 1.4 and pin 2 is provided with the first metal layer 4; The back side at said second the 1.2, the 4th basic island 1.4, basic island and pin 2 is provided with second metal level 5, through conduction or non-conductive bonding material 6 chip 7 is set in the said second basic island 1.2 positive central sunken regions and 1.4 fronts, the 4th basic island, and no filler plastic packaging material 3 is set in zone between zone, the 4th basic island 1.4 and pin 2 between zone, the second basic island 1.2 and the 4th basic island 1.4 between zone, pin 2 and the second basic island 1.2 of said pin 2 peripheries and the zone between pin 2 and the pin 2; Said packless plastic packaging material (epoxy resin) 3 links into an integrated entity with pin 2 bottoms and pin 2 periphery, pin bottom, pin 2 and 1.2 bottoms, the second basic island, the second basic island 1.2 and 1.4 bottoms, the 4th basic island, the 4th basic island 1.4 with pin 2 bottoms, said pin 2 is provided with a circle.
Embodiment 14: the base island exposed type individual pen of baried type Ji Dao and multi-convex point pin
Referring to Figure 40～42, Figure 40 (A)～Figure 40 (R) afterwards carves single method for packing embodiment 14 each operation sketch map for the two-sided graphic chips formal dress of the present invention plates earlier.41 are single encapsulating structure embodiment 14 structural representations of the two-sided graphic chips formal dress of the present invention.Figure 42 is 41 vertical view.Can find out by Figure 40～42; Embodiment 14 is with the difference of embodiment 1: said basic island 1 has two groups also can be many group Ji Dao; One group is the 3rd basic island 1.3; Another group is the 4th basic island 1.4; Multi-convex point shape structure is arranged in 1.4 fronts, the said the 4th basic island; Front at the said the 3rd the 1.3, the 4th basic island 1.4, basic island and pin 2 is provided with the first metal layer 4; The back side at the said the 4th basic island 1.4 and pin 2 is provided with second metal level 5; No filler plastic packaging material 3 is set in zone and the zone between pin and the pin between zone, the 3rd basic island 1.3 and pin 2 between zone, 1.3 back sides, the 3rd basic island, the second basic island 1.2 and the 4th basic island 1.4 between zone, pin 2 and the 4th basic island 1.4 of said pin 2 peripheries, and said no filler plastic packaging material 3 links into an integrated entity periphery, pin bottom, pin 2 and 1.4 bottoms, the 4th basic island, 1.3 back sides, the 3rd basic island, the 3rd 1.3 back sides, basic island and 1.4 bottoms, the 4th basic island, the 3rd 1.3 back sides, basic island and pin 2 bottoms and pin 2 with pin 2 bottoms, and said pin 2 is provided with a circle.
Claims (12)
1. a two-sided graphic chips formal dress plates earlier and afterwards carves single method for packing, and it is characterized in that: said method comprises following processing step:
Step 1, get metal substrate
Get the suitable metal substrate of a slice thickness,
Step 2, metal substrate front and back side lining photoresistance glued membrane
Utilization by coating equipment in the front of metal substrate and the back side be covered respectively and can carry out the photoresistance glued membrane of exposure imaging, protecting follow-up electroplated metal layer process operation,
The positive photoresistance glued membrane of step 3, metal substrate needs the exposure of plated metal layer region/develop and windows
The metal substrate front that utilizes exposure imaging equipment that step 2 is accomplished photoresistance glued membrane lining operation is carried out exposure imaging and is removed part photoresistance glued membrane, carries out the zone of electroplated metal layer to expose the positive follow-up needs of metal substrate,
The zone of having windowed in step 4, metal substrate front is carried out metal level and is electroplated lining
The first metal layer plating lining is carried out in zone to having windowed in metal substrate front in the step 3, and this first metal layer places the front of Ji Dao and pin,
Photoresistance glued membrane striping is carried out at step 5, metal substrate front and the back side
The positive remaining photoresistance glued membrane of metal substrate and the photoresistance glued membrane at the metal substrate back side are all removed,
Step 6, metal substrate front and back side lining photoresistance glued membrane
Utilization by coating equipment in the front of metal substrate and the back side be covered respectively and can carry out the photoresistance glued membrane of exposure imaging, protecting follow-up etch process operation,
The photoresistance glued membrane at step 7, the metal substrate back side needs the exposure of etching area/develop and windows
Exposure imaging removal part photoresistance glued membrane is carried out at the metal substrate back side that utilizes exposure imaging equipment that step 6 is accomplished photoresistance glued membrane lining operation, prepares against the metal substrate back etched operation that follow-up needs carry out to expose the localized metallic substrate,
Step 8, metal substrate carry out the back etched operation
After the exposure/development and windowing task of completing steps seven, promptly carry out the etching operation of each figure, etch the back side of Ji Dao and pin, simultaneously the pin front is extended to next door, basic island as much as possible at the back side of metal substrate,
Photoresistance glued membrane striping is carried out at step 9, metal substrate front and the back side
The photoresistance glued membrane that the metal substrate front and back is remaining all removes,
Step 10, seal packless plastic packaging material
Packless plastic packaging material operation is sealed at the metal substrate back side of completing steps nine said striping operations; And carry out the curing operation after plastic packaging material is sealed; Make zone and the zone between pin and the pin between Ji Dao and pin peripheral zone, pin and the basic island all set packless plastic packaging material; This packless plastic packaging material is peripheral with Ji Dao and pin bottom, pin bottom and Ji Dao bottom and pin bottom and pin bottom link into an integrated entity
Step 11, lining photoresistance glued membrane
Utilization by coating equipment in the front that will accomplish the metal substrate of sealing the operation of no filler plastic packaging material and the back side be covered respectively and can carry out the photoresistance glued membrane of exposure imaging, protecting follow-up etch process operation,
Step 12, the front of having accomplished the metal substrate of sealing the operation of no filler plastic packaging material need the exposure of etching area/develop and window
Exposure imaging removal part photoresistance glued membrane is carried out in the metal substrate front of sealing the operation of no filler plastic packaging material of accomplishing that utilizes exposure imaging equipment that step 11 is accomplished photoresistance glued membrane lining operation, carries out the operation of metal substrate front-side etch in order to follow-up needs,
Step 13, the operation of metal substrate front-side etch
After the exposure/development and windowing task of completing steps 12; Promptly carry out the etching operation of each figure in the metal substrate front that the operation of no filler plastic packaging material is sealed in completion; Etch the front of Ji Dao and pin; And make the positive size of the back side size of said Ji Dao and pin, form up big and down small Ji Dao and pin configuration less than Ji Dao and pin
Photoresistance glued membrane striping is carried out at step 14, metal substrate front and the back side
The positive remaining photoresistance glued membrane of the metal substrate of completing steps 13 etching operations and the photoresistance glued membrane at the metal substrate back side are all removed, process lead frame,
Step 15, load
On the first metal layer of front, basic island, carry out the implantation of chip through conduction or non-conductive bonding material,
Step 10 six, break metal wire
The semi-finished product of accomplishing chip implantation operation are carried out playing the metal wire operation between chip front side and the pin front the first metal layer,
Step 10 seven, be encapsulated with the filler plastic packaging material
The semi-finished product front that routing is accomplished is carried out local unit and is encapsulated with the operation of filler plastic packaging material; The positive local unit of pin zone is exposed the filler plastic packaging material is arranged; And carry out the curing operation after plastic packaging material is sealed; Make top and chip and the metal wire of Ji Dao and pin all had the filler plastic packaging material to seal outward
The back side of step 10 eight, Ji Dao and pin and the front of pin are carried out metal level and are electroplated lining
Completing steps 17 is encapsulated with the said positive local unit of the pin zones that the filler plastic packaging material is arranged of exposing of the back side and the step 10 seven of said Ji Dao and pin of filler plastic packaging material operation and carries out second metal level and the first metal layer respectively and electroplate the operation that is covered,
Step 10 nine, cutting finished product
The semi-finished product of ten eight the second metal levels of completing steps being electroplated lining carry out cutting operation, make originally more than of chips that connect together with array formula aggregate mode independent, make single encapsulating structure finished product of two-sided graphic chips formal dress.
2. a kind of two-sided graphic chips formal dress according to claim 1 plates earlier afterwards carves single method for packing, it is characterized in that Ji Dao (1) back side exposes said packless plastic packaging material (3).
3. a kind of two-sided graphic chips formal dress according to claim 1 plates earlier afterwards carves single method for packing, it is characterized in that Ji Dao (1) front middle section sinks.
4. a kind of two-sided graphic chips formal dress according to claim 1 plates earlier afterwards carves single method for packing, it is characterized in that Ji Dao (1) back side imbeds in the said packless plastic packaging material (3).
5. a kind of two-sided graphic chips formal dress according to claim 1 plates earlier afterwards carves single method for packing, it is characterized in that said Ji Dao (1) front is arranged to multi-convex point shape structure.
6. plate earlier according to one of them described a kind of two-sided graphic chips formal dress of claim 2～5 and afterwards carve single method for packing, it is a plurality of to it is characterized in that said Ji Dao (1) has, and pin (2) has individual pen.
7. a kind of two-sided graphic chips formal dress according to claim 1 plates earlier afterwards carves single method for packing; It is characterized in that said Ji Dao (1) has two groups; One group is first Ji Dao (1.1); Another group is second Ji Dao (1.2); Said second Ji Dao (1.2) front middle section sinks; Front at said first Ji Dao (1.1) and pin (2) is provided with the first metal layer (4); The back side at said first Ji Dao (1.1), second Ji Dao (1.2) and pin (2) is provided with second metal level (5); Be provided with chip (7) in positive central sunken regions of second Ji Dao (1.2) and first Ji Dao (1.1) front through conduction or non-conductive bonding material (6); Chip (7) positive with pin (2) front the first metal layer (4) between and all use metal wire (8) to be connected between chip (7) and the chip (7); Nos filler plastic packaging material (3) is set in zone between zone, second Ji Dao (1.2) and pin (2) between zone, first Ji Dao (1.1) and second Ji Dao (1.2) between peripheral zone, pin (2) and first Ji Dao (1.1) of said pin (2) and the zone between pin (2) and the pin (2), and said no filler plastic packaging material (3) links into an integrated entity periphery, pin bottom, pin (2) and first Ji Dao (1.1) bottom, first Ji Dao (1.1) and second Ji Dao (1.2) bottom, second Ji Dao (1.2) and pin (2) bottom and pin (2) and pin (2) bottom, and said pin (2) is provided with individual pen.
8. a kind of two-sided graphic chips formal dress according to claim 1 plates earlier afterwards carves single method for packing; It is characterized in that said Ji Dao (1) has two groups; One group is first Ji Dao (1.1); Another group is the 3rd Ji Dao (1.3); Front at said first Ji Dao (1.1) the 3rd Ji Dao (1.3) and pin (2) is provided with the first metal layer (4); The back side at said first Ji Dao (1.1) and pin (2) is provided with second metal level (5); Be provided with chip (7) in Ji Dao (1) front through conduction or non-conductive bonding material (6); Chip (7) positive with pin (2) front the first metal layer (4) between and all use metal wire (8) to be connected between chip (7) and the chip (7); Outside the top of said Ji Dao (1) and pin (2) and chip (7) and metal wire (8), be encapsulated with filler plastic packaging material (9); No filler plastic packaging material (3) is set in zone and the zone between pin and the pin between zone, the 3rd Ji Dao (1.3) and pin (2) between zone, the 3rd Ji Dao (1.3) back side, second Ji Dao (1.2) and first Ji Dao (1.1) between zone, pin (2) and first Ji Dao (1.1) of said pin (2) periphery, and said no filler plastic packaging material (3) is peripheral with the pin bottom, pin (2) links into an integrated entity with pin (2) bottom with first Ji Dao (1.1) bottom, the 3rd Ji Dao (1.3) back side, the 3rd Ji Dao (1.3) back side and first Ji Dao (1.1) bottom, the 3rd Ji Dao (1.3) back side and pin (2) bottom and pin (2), and said pin (2) is provided with individual pen.
9. the method for packing of single encapsulating structure of a kind of two-sided graphic chips formal dress according to claim 1; It is characterized in that said Ji Dao (1) has two groups; One group is first Ji Dao (1.1); Another group is the 4th Ji Dao (1.4); Said the 4th Ji Dao (1.4) is arranged to multi-convex point shape structure in the front; No filler plastic packaging material (3) is set in zone between zone, the 4th Ji Dao (1.4) and pin (2) between zone, first Ji Dao (1.1) and the 4th Ji Dao (1.4) between zone, pin (2) and first Ji Dao (1.1) of said pin (2) periphery and the zone between pin (2) and the pin (2); Said packless plastic packaging material (3) is peripheral with the pin bottom, pin (2) links into an integrated entity with pin (2) bottom with pin (2) bottom and pin (2) with the 4th Ji Dao (1.4) bottom, the 4th Ji Dao (1.4) with first Ji Dao (1.1) bottom, first Ji Dao (1.1), and said pin (2) is provided with individual pen.
10. a kind of two-sided graphic chips formal dress according to claim 1 plates earlier afterwards carves single method for packing; It is characterized in that said Ji Dao (1) has two groups also can be many group Ji Dao; One group is second Ji Dao (1.2); Another group is the 3rd Ji Dao (1.3); Said second Ji Dao (1.2) front middle section sinks; Be provided with chip (7) in positive central sunken regions of second Ji Dao (1.2) and the 3rd Ji Dao (1.3) front through conduction or non-conductive bonding material (6); No filler plastic packaging material (3) is set in zone and the zone between pin and the pin between zone, the 3rd Ji Dao (1.3) back side and pin (2) between zone, the 3rd Ji Dao (1.3) back side, the second Ji Dao back side (1.2) and second Ji Dao (1.2) between zone, pin (2) and second Ji Dao (1.2) of said pin (2) periphery; Said no filler plastic packaging material (3) is peripheral with the pin bottom, pin (2) links into an integrated entity with pin (2) bottom with second Ji Dao (1.2) bottom, the 3rd Ji Dao (1.3) back side and pin (2) bottom and pin (2) with second Ji Dao (1.2) bottom, the 3rd Ji Dao (1.3), the 3rd Ji Dao (1.3), and said pin (2) is provided with individual pen.
11. plating earlier, a kind of two-sided graphic chips formal dress according to claim 1 afterwards carves single method for packing; It is characterized in that said Ji Dao (1) has two groups; One group is second Ji Dao (1.2); Another group is the 4th Ji Dao (1.4); Said second Ji Dao (1.2) front middle section sinks; The 4th Ji Dao (1.4) is arranged to multi-convex point shape structure in the front; Front at said the 4th Ji Dao (1.4) and pin (2) is provided with the first metal layer (4); The back side at said second Ji Dao (1.2), the 4th Ji Dao (1.4) and pin (2) is provided with second metal level (5), is provided with chip (7) in positive central sunken regions of said second Ji Dao (1.2) and the 4th Ji Dao (1.4) front through conduction or non-conductive bonding material (6), and no filler plastic packaging material (3) is set in zone between zone, the 4th Ji Dao (1.4) and pin (2) between zone, second Ji Dao (1.2) and the 4th Ji Dao (1.4) between zone, pin (2) and second Ji Dao (1.2) of said pin (2) periphery and the zone between pin (2) and the pin (2); Said packless plastic packaging material (3) is peripheral with the pin bottom, pin (2) links into an integrated entity with pin (2) bottom with pin (2) bottom and pin (2) with the 4th Ji Dao (1.4) bottom, the 4th Ji Dao (1.4) with second Ji Dao (1.2) bottom, second Ji Dao (1.2), and said pin (2) is provided with individual pen.
12. plating earlier, a kind of two-sided graphic chips formal dress according to claim 1 afterwards carves single method for packing; It is characterized in that said Ji Dao (1) has two groups; One group is the 3rd Ji Dao (1.3); Another group is the 4th Ji Dao (1.4); Said the 4th Ji Dao (1.4) is arranged to multi-convex point shape structure in the front; Front at said the 3rd Ji Dao (1.3), the 4th Ji Dao (1.4) and pin (2) is provided with the first metal layer (4); The back side at said the 4th Ji Dao (1.4) and pin (2) is provided with second metal level (5); No filler plastic packaging material (3) is set in zone and the zone between pin and the pin between zone, the 3rd Ji Dao (1.3) and pin (2) between zone, the 3rd Ji Dao (1.3) back side, second Ji Dao (1.2) and the 4th Ji Dao (1.4) between zone, pin (2) and the 4th Ji Dao (1.4) of said pin (2) periphery, and said no filler plastic packaging material (3) is peripheral with the pin bottom, pin (2) links into an integrated entity with pin (2) bottom with the 4th Ji Dao (1.4) bottom, the 3rd Ji Dao (1.3) back side, the 3rd Ji Dao (1.3) back side and the 4th Ji Dao (1.4) bottom, the 3rd Ji Dao (1.3) back side and pin (2) bottom and pin (2), and said pin (2) is provided with individual pen.
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| CN2010102730015A CN101950726B (en) | 2010-09-04 | 2010-09-04 | First-coating last-etching single package method for positively packaging double-sided graphic chip |
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| CN102324413B (en) * | 2011-09-13 | 2013-03-06 | 江苏长电科技股份有限公司 | Sequentially etched and plated lead frame structure with island prepacked plastic sealed material and producing method thereof |
| CN102376672B (en) * | 2011-11-30 | 2014-10-29 | 江苏长电科技股份有限公司 | Foundation island-free ball grid array packaging structure and manufacturing method thereof |
| CN102683315B (en) * | 2011-11-30 | 2015-04-29 | 江苏长电科技股份有限公司 | Barrel-plating four-side pinless packaging structure and manufacturing method thereof |
| JP6489615B2 (en) * | 2015-07-31 | 2019-03-27 | 大口マテリアル株式会社 | Semiconductor element mounting substrate, semiconductor device and manufacturing method thereof |
| JP6460407B2 (en) * | 2015-07-31 | 2019-01-30 | 大口マテリアル株式会社 | Semiconductor element mounting substrate, semiconductor device and manufacturing method thereof |
| CN109427698B (en) * | 2017-09-04 | 2023-08-29 | 恩智浦美国有限公司 | Method for assembling QFP type semiconductor device |
| CN113192900A (en) * | 2021-04-02 | 2021-07-30 | 江阴苏阳电子股份有限公司 | Packaging process of packaging structure with etched back first |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101131982A (en) * | 2007-09-13 | 2008-02-27 | 江苏长电科技股份有限公司 | Non-pin packaging structure of semiconductor element and packaging technology thereof |
| WO2010036051A2 (en) * | 2008-09-25 | 2010-04-01 | Lg Innotek Co., Ltd. | Structure and manufacture method for multi-row lead frame and semiconductor package |
| CN101770999A (en) * | 2010-01-29 | 2010-07-07 | 江苏长电科技股份有限公司 | External connection heat radiation cap encapsulation structure of positive installation lock hole heat radiation block projected post of base island embedded chip |
Family Cites Families (1)
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| KR100784497B1 (en) * | 2004-10-06 | 2007-12-11 | 삼성전자주식회사 | Film substrate of semiconductor package and manufacturing method thereof |
-
2010
- 2010-09-04 CN CN2010102730015A patent/CN101950726B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101131982A (en) * | 2007-09-13 | 2008-02-27 | 江苏长电科技股份有限公司 | Non-pin packaging structure of semiconductor element and packaging technology thereof |
| WO2010036051A2 (en) * | 2008-09-25 | 2010-04-01 | Lg Innotek Co., Ltd. | Structure and manufacture method for multi-row lead frame and semiconductor package |
| CN101770999A (en) * | 2010-01-29 | 2010-07-07 | 江苏长电科技股份有限公司 | External connection heat radiation cap encapsulation structure of positive installation lock hole heat radiation block projected post of base island embedded chip |
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