CN202003985U - Directly placed, first plated, then carved single packaging structure of two-sided figure chip - Google Patents
Directly placed, first plated, then carved single packaging structure of two-sided figure chip Download PDFInfo
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- CN202003985U CN202003985U CN2010205178690U CN201020517869U CN202003985U CN 202003985 U CN202003985 U CN 202003985U CN 2010205178690 U CN2010205178690 U CN 2010205178690U CN 201020517869 U CN201020517869 U CN 201020517869U CN 202003985 U CN202003985 U CN 202003985U
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- pin
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- packaging material
- plastic packaging
- metal wire
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Packaging Frangible Articles (AREA)
Abstract
The utility model relates to a directly placed, first plated, then carved single packaging structure of two-sided figure chip. The structure comprises a pin (2), packless plastic packaging material (3), non-conducting bonding substance (6), a chip (7), a metal wire (8) and packing plastic packaging material ((9), wherein the right side of the pin (2) extends to a lower portion of a subsequent pasted chip area as far as possible, a first metal layer (4) at the right side of the pin (2) at the lower portion of the subsequent pasted chip is provided with the chip (7) via the non-conducting bonding substance (6), the right side of the chip (7) is connected with the first metal layer (4) at the right side of the pin (2) via the metal wire (8), the packing plastic packaging material ((9) is packed on the outside of the upper portion of the pin (2), the chip (7) and the metal wire (8), The periphery of the pin (2) and area between two sides of the pin (2) are embedded with the packless plastic packaging material (3), and the packing plastic packaging material ((9) clads local part of the right side of the pin (2). The chip packaging structure of the utility model can avoid falling off of the pin, and can shorten the length of the metal wire.
Description
(1) technical field
The utility model relates to a kind of two-sided graphic chips and directly puts to plate earlier and afterwards carve single encapsulating structure.Belong to the semiconductor packaging field.
(2) background technology
The production method of traditional chip-packaging structure is: after chemical etching and surface electrical coating are carried out in the front of employing metal substrate, promptly finish the making (as shown in Figure 4) of lead frame.Etching is then carried out at the back side of lead frame again in encapsulation process.This method has the following disadvantages:
Because only carried out the work that etches partially before the plastic packaging in the metal substrate front, and plastic packaging material only wraps the height of half pin of pin in the plastic packaging process, so the constraint ability of plastic-sealed body and pin has just diminished, when if the plastic-sealed body paster is not fine to pcb board, do over again again and heavily paste, with regard to the problem (as shown in Figure 5) that is easy to generate pin.Especially the kind of plastic packaging material is to adopt when filler is arranged, because material is at the environment and the follow-up surface-pasted stress changing relation of production process, can cause metal and plastic packaging material to produce the crack of vertical-type, its characteristic is the high more then hard more crisp more crack that is easy to generate more of proportion of filler.
In addition, because the distance between chip and the pin is far away, the length of metal wire is longer, shown in Fig. 6～7, and metal wire cost higher (the especially metal wire of Ang Gui proof gold matter); Same because the length of metal wire is longer, make that the signal output speed of chip is slow (especially the product of storage class and the calculating that needs mass data are more outstanding); Too because the length of metal wire is longer, so also higher to the interference of signal in existing dead resistance/parasitic capacitance of metal wire and parasitic electric pole; Because the distance between chip and the pin is far away, make that the volume and the area of encapsulation are bigger again, material cost is higher, and discarded object is more.
(3) summary of the invention
The purpose of this utility model is to overcome above-mentioned deficiency, provide a kind of do not have the problem of producing pin again and can make the two-sided graphic chips of the contraction in length of metal wire directly put to plate earlier afterwards carve single encapsulating structure.
The purpose of this utility model is achieved in that a kind of two-sided graphic chips is directly put to plate earlier and afterwards carves single encapsulating structure, comprise pin, packless plastic packaging material (epoxy resin), non-conductive bonding material, chip, metal wire and filler plastic packaging material (epoxy resin) arranged, described pin front extends to the below in follow-up pasting chip zone as much as possible, front at described pin is provided with the first metal layer, be provided with second metal level at the back side of described pin, on the pin front the first metal layer below the described follow-up pasting chip, be provided with chip by non-conductive bonding material, be connected with metal wire between chip front side and the pin front the first metal layer, outside the top of described pin and chip and metal wire, be encapsulated with filler plastic packaging material (epoxy resin), zone and the zone between pin and the pin in described pin periphery are equipped with packless plastic packaging material (epoxy resin), described packless plastic packaging material (epoxy resin) links into an integrated entity periphery, pin bottom and pin bottom and pin bottom, and make described pin back side size less than the positive size of pin, form up big and down small pin configuration, it is characterized in that: described have filler plastic packaging material (epoxy resin) that the positive local unit of pin is coated.
The beneficial effects of the utility model are:
1, guarantees not have again the problem that produces pin
Because lead frame has adopted two-sided etched technology, so planning and designing easily with produce up big and down small pin configuration, the levels plastic packaging material is wrapped up big and down small pin configuration closely together, so the constraint ability of plastic-sealed body and pin just becomes big, do not have the problem that produces pin again.
2, guarantee the contraction in length of metal wire
1) separates etched technology owing to used the lead frame back side with the front, so the pin in lead frame front can be extended to as much as possible the center of packaging body, impel chip and pin distance significantly to shorten, as Fig. 2～Fig. 3, so the length of metal wire has also shortened, and the cost of metal wire also can significantly reduce (the especially metal wire of Ang Gui proof gold matter);
2) also because the contraction in length of metal wire makes also significantly speedup (the especially product of storage class and the calculating that needs mass data of signal output speed of chip, more outstanding), because the length of metal wire has shortened, so existing dead resistance/parasitic capacitance of metal wire and parasitic electric pole are to the also significantly reduction of interference of signal.
3, the volume of encapsulation and area can significantly be dwindled
Because of having used the elongation technology of pin,, make the volume and the area of encapsulation significantly to dwindle so can be easy to produce the distance between high pin number and highdensity pin and the pin.
4, material cost and material usage reduce
Because volume after being encapsulated is significantly dwindled, more direct embody material cost significantly descend with because the minimizing of material usage also significantly reduces the puzzlement of discarded object environmental protection.
5, adopt the advantage of single encapsulation of local unit to have:
1) in different application, the pin at plastic-sealed body edge can be stretched out plastic-sealed body.
2) pin at plastic-sealed body edge stretches out outside the plastic-sealed body and can clearly check out situation about being welded on the pcb board.
3) area of modular type is easy because multiple different shrinkage that material structure produces is different should stand distortion than conference, and single encapsulation of local unit just can disperse fully multiple different shrinkage that material structure produces different should stand distortion.
4) single is encapsulated in when carrying out the plastic-sealed body cutting and separating, because the thickness that cuts has only the thickness of pin, so the speed of cutting can be come much soon than the encapsulating structure of modular type, so and incisory blade because the thickness of cutting just approached life-span of cutting blade relative also just become longer.
(4) description of drawings
Fig. 1 (A)～Fig. 1 (R) directly puts to plate earlier for the two-sided graphic chips of the utility model and afterwards carves each operation schematic diagram of single encapsulating structure.
Fig. 2 directly puts single encapsulating structure embodiment 1 structural representation for the two-sided graphic chips of the utility model.
Fig. 3 is the vertical view of Fig. 2.
Fig. 4 was for to adopt the front of metal substrate to carry out chemical etching and surface electrical coating flow diagram in the past.
Fig. 5 pin figure for what formed in the past.
Fig. 6 is an encapsulating structure schematic diagram in the past.
Fig. 7 is 6 vertical view.
Reference numeral among the figure:
(5) embodiment
Referring to Fig. 2 and Fig. 3, Fig. 2 directly puts single encapsulating structure schematic diagram for the two-sided graphic chips of the utility model.Fig. 3 is the vertical view of Fig. 2.By Fig. 2 and Fig. 3 as can be seen, the two-sided graphic chips of the utility model is directly put single encapsulating structure, comprise pin 2, packless plastic packaging material (epoxy resin) 3, non-conductive bonding material 6, chip 7, metal wire 8 and filler plastic packaging material (epoxy resin) 9 is arranged, described pin 2 fronts extend to the below in follow-up pasting chip zone as much as possible, be provided with the first metal layer 4 in the front of described pin 2, be provided with second metal level 5 at the back side of described pin 2, on the 2 front the first metal layers 4 of the pin below the described follow-up pasting chip, be provided with chip 7 by non-conductive bonding material 6, chip 7 positive with pin 2 front the first metal layers 4 between be connected with metal wire 8, outside the top of described pin 2 and chip 7 and metal wire 8, be encapsulated with filler plastic packaging material (epoxy resin) 9, this has filler plastic packaging material (epoxy resin) 9 that pin 2 positive local unit are coated, be equipped with packless plastic packaging material (epoxy resin) 3 in the zone of described pin 2 peripheries and the zone between pin 2 and the pin 2, described packless plastic packaging material (epoxy resin) 3 links into an integrated entity periphery, pin bottom and pin 2 bottoms and pin 2 bottoms, and make described pin back side size less than the positive size of pin, form up big and down small pin configuration.
Its encapsulating structure is as follows:
Step 1, get metal substrate
Referring to Fig. 1 (A), get the suitable metal substrate of a slice thickness 10.The material of metal substrate can be carried out conversion according to the function and the characteristic of chip, for example: copper, aluminium, iron, copper alloy or dilval etc.
Referring to Fig. 1 (B), utilize by coating equipment in the front of metal substrate and the back side be covered respectively and can carry out the photoresistance glued membrane 11 and 12 of exposure imaging, to protect follow-up electroplated metal layer process operation.And this photoresistance glued membrane can be a dry type photoresistance pellicle also can be wet type photoresistance glued membrane.
The photoresistance glued membrane in step 3, metal substrate front needs the exposure of plated metal layer region/develop and windows
Referring to Fig. 1 (C), the metal substrate front that utilizes exposure imaging equipment that step 2 is finished photoresistance glued membrane lining operation is carried out exposure imaging and is removed part photoresistance glued membrane, carries out the zone of electroplated metal layer to expose the positive follow-up needs of metal substrate.
The zone of having windowed in step 4, metal substrate front is carried out metal level and is electroplated lining
Referring to Fig. 1 (D), the first metal layer 4 plating linings are carried out in the zone of having windowed in metal substrate front in the step 3, this first metal layer 4 places the front of described pin 2.
Photoresistance glued membrane striping is carried out at step 5, metal substrate front and the back side
Referring to Fig. 1 (E), the positive remaining photoresistance glued membrane of metal substrate and the photoresistance glued membrane at the metal substrate back side are all removed.
Referring to Fig. 1 (F), utilize by coating equipment in the front of metal substrate and the back side be covered respectively and can carry out the photoresistance glued membrane 13 and 14 of exposure imaging, to protect follow-up etch process operation.And this photoresistance glued membrane can be a dry type photoresistance pellicle also can be wet type photoresistance glued membrane.
The photoresistance glued membrane at step 7, the metal substrate back side needs the exposure of etching area/develop and windows
Referring to Fig. 1 (G), exposure imaging removal part photoresistance glued membrane is carried out at the metal substrate back side that utilizes exposure imaging equipment that step 6 is finished photoresistance glued membrane lining operation, to expose the metal substrate back etched operation that the localized metallic substrate carries out in order to follow-up needs.
Referring to Fig. 1 (H), after the exposure/development and windowing task of completing steps seven, promptly carry out the etching operation of each figure, etch the back side of pin 2, simultaneously the pin front is extended to as much as possible the below, zone of described follow-up pasting chip at the back side of metal substrate.
Photoresistance glued membrane striping is carried out at step 9, metal substrate front and the back side
Referring to Fig. 1 (I), the photoresistance glued membrane of metal substrate front and back remainder is all removed.
Step 10, seal packless plastic packaging material (epoxy resin)
Referring to Fig. 1 (J), packless plastic packaging material (epoxy resin) operation is sealed at the metal substrate back side of completing steps nine described striping operations, and carry out curing operation after plastic packaging material is sealed, make the zone of pin 2 peripheries and the zone between pin 2 and the pin 2 all set packless plastic packaging material (epoxy resin) 3, this packless plastic packaging material (epoxy resin) 3 links into an integrated entity periphery, pin bottom and pin 2 bottoms and pin 2 bottoms.
Referring to Fig. 1 (K), utilize by coating equipment in the front that will finish the metal substrate of sealing the operation of no filler plastic packaging material and the back side be covered respectively and can carry out the photoresistance glued membrane 15 and 16 of exposure imaging, to protect follow-up etch process operation.And this photoresistance glued membrane can be a dry type photoresistance pellicle also can be wet type photoresistance glued membrane.
Referring to Fig. 1 (L), exposure imaging removal part photoresistance glued membrane is carried out in the metal substrate front of sealing the operation of no filler plastic packaging material of finishing that utilizes exposure imaging equipment that step 11 is finished photoresistance glued membrane lining operation, carries out the operation of metal substrate front-side etch in order to follow-up needs.
Referring to Fig. 1 (M), after the exposure/development and windowing task of completing steps 12, promptly finish the etching operation that each figure is carried out in the metal substrate front of sealing the operation of no filler plastic packaging material, etch the front of pin 2, and make the positive size of the back side size of described pin 2, form up big and down small pin 2 structures less than pin 2.
Photoresistance glued membrane striping is carried out at step 14, metal substrate front and the back side
Referring to Fig. 1 (N), the positive remaining photoresistance glued membrane of the metal substrate of completing steps 13 etching operations and the photoresistance glued membrane at the metal substrate back side are all removed, make lead frame.
Step 15, load
Referring to Fig. 1 (O), on the 2 front the first metal layers 4 of the pin below the zone of described follow-up pasting chip, carry out the implantation of chip 7 by non-conductive bonding material 6.
Step 10 six, break metal wire
Referring to Fig. 1 (P), the semi-finished product of finishing chip implantation operation are carried out playing metal wire 8 operations between chip front side and the pin front the first metal layer.
Step 10 seven, be encapsulated with filler plastic packaging material (epoxy resin)
Referring to Fig. 1 (Q), the semi-finished product front that routing is finished is carried out local unit and is encapsulated with filler plastic packaging material (epoxy resin) 9 operations, pin 2 positive local unit zones are exposed filler plastic packaging material (epoxy resin) 9 is arranged, and carry out curing operation after plastic packaging material is sealed, make the top of pin and chip and metal wire all be had filler plastic packaging material (epoxy resin) to seal outward.
The back side of step 10 eight, pin and front are carried out metal level and are electroplated lining
Referring to Fig. 1 (R), completing steps 17 is encapsulated with the back side of described pin of filler plastic packaging material (epoxy resin) operation and step 10 seven are described exposes that second metal level 5 is carried out in the pin 2 positive zones that filler plastic packaging material (epoxy resin) 9 is arranged respectively and the first metal layer 4 is electroplated the lining operations, and the material of electroplating can be tin, nickel gold, NiPdAu .... wait metal material.
Step 10 nine, cutting finished product
Referring to Fig. 2 and Fig. 3, the semi-finished product of ten eight the second metal levels of completing steps being electroplated lining carry out cutting operation, make script independent, make two-sided graphic chips and directly put single encapsulating structure finished product with more than of the chips that array formula aggregate mode connects together.
Described pin 2 can be provided with individual pen, shown in Fig. 1～3, also can be provided with multi-turn.
Claims (1)
1. a two-sided graphic chips is directly put to plate earlier and is afterwards carved single encapsulating structure, comprise pin (2), packless plastic packaging material (3), non-conductive bonding material (6), chip (7), metal wire (8) and filler plastic packaging material (9) is arranged, the positive below that extends to follow-up pasting chip zone as much as possible of described pin (2), be provided with the first metal layer (4) in the front of described pin (2), be provided with second metal level (5) at the back side of described pin (2), pin below described follow-up pasting chip (2) front the first metal layer (4) is gone up and is provided with chip (7) by non-conductive bonding material (6), chip (7) positive with pin (2) front the first metal layer (4) between be connected with metal wire (8), outside the top of described pin (2) and chip (7) and metal wire (8), be encapsulated with filler plastic packaging material (9), be equipped with packless plastic packaging material (3) in the zone of described pin (2) periphery and the zone between pin (2) and the pin (2), described packless plastic packaging material (3) links into an integrated entity periphery, pin bottom and pin (2) bottom and pin (2) bottom, and make described pin back side size less than the positive size of pin, form up big and down small pin configuration, it is characterized in that: described have filler plastic packaging material (9) that the positive local unit of pin (2) is coated.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010205178690U CN202003985U (en) | 2010-09-04 | 2010-09-04 | Directly placed, first plated, then carved single packaging structure of two-sided figure chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010205178690U CN202003985U (en) | 2010-09-04 | 2010-09-04 | Directly placed, first plated, then carved single packaging structure of two-sided figure chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202003985U true CN202003985U (en) | 2011-10-05 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010205178690U Expired - Lifetime CN202003985U (en) | 2010-09-04 | 2010-09-04 | Directly placed, first plated, then carved single packaging structure of two-sided figure chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202003985U (en) |
-
2010
- 2010-09-04 CN CN2010205178690U patent/CN202003985U/en not_active Expired - Lifetime
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Granted publication date: 20111005 |