CN201936874U - Double-sided graphics chip positive single packaging structure - Google Patents

Double-sided graphics chip positive single packaging structure Download PDF

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Publication number
CN201936874U
CN201936874U CN2010205178864U CN201020517886U CN201936874U CN 201936874 U CN201936874 U CN 201936874U CN 2010205178864 U CN2010205178864 U CN 2010205178864U CN 201020517886 U CN201020517886 U CN 201020517886U CN 201936874 U CN201936874 U CN 201936874U
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China
Prior art keywords
pin
dao
zone
plastic packaging
packaging material
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CN2010205178864U
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Chinese (zh)
Inventor
王新潮
梁志忠
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JCET Group Co Ltd
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Jiangsu Changjiang Electronics Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/32257—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the layer connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

The utility model relates to a double-sided graphics chip positive single packaging structure. The structure comprises base islands (1), pins (2), packless molding compounds (epoxide resin)(3), conductive or non-conductive bonding materials (6), chips (7), metal wires (8) and packed molding compounds (epoxide resin)(9). The front sides of the pins (2) extend beside the base islands (1). By the packless molding compounds (3), the base islands (1) are connected with the peripheries of the lower parts of the pins (2) into one whole body, the lower parts of the pins (2) are connected with the lower parts of the base islands (1) into one whole body, and the lower parts of the pins (2) are connected mutually into one whole body. The back surface sizes of the base islands and the pins are smaller than the front surface sizes of the pins, so that a base island and pin structure with a large upper part and a small lower part is formed. Part of units at the front sides of the pins (2) are coated with the packed molding compounds (9). The back surfaces of the pins (2) are provided with pillars (10). The root parts of the pillars (10) are embedded into the packless molding compounds (3). In the loading process, the double-sided graphics chip positive single packaging structure can bear an ultrahigh temperature, the distortion of a lead frame cannot be generated due to different physical properties of different materials, and the problems that the pins fall down and the lengths of the metal wires are shortened cannot be generated.

Description

Single encapsulating structure of two-sided graphic chips formal dress
(1) technical field
The utility model relates to single encapsulating structure of a kind of two-sided graphic chips formal dress.Belong to the semiconductor packaging field.
(2) background technology
The production method of traditional chip-packaging structure is: after chemical etching and surface electrical coating are carried out in the front of employing metal substrate, promptly finish the making (as shown in figure 43) of lead frame.Etching is then carried out at the back side of lead frame again in encapsulation process.This method has the following disadvantages:
Because only carried out the work that etches partially before the plastic packaging in the metal substrate front, and plastic packaging material only wraps the height of half pin of pin in the plastic packaging process, so the constraint ability of plastic-sealed body and pin has just diminished, when if the plastic-sealed body paster is not fine to pcb board, do over again again and heavily paste, with regard to the problem (as shown in figure 44) that is easy to generate pin.Especially the kind of plastic packaging material is to adopt when filler is arranged, because material is at the environment and the follow-up surface-pasted stress changing relation of production process, can cause metal and plastic packaging material to produce the crack of vertical-type, its characteristic is the high more then hard more crisp more crack that is easy to generate more of proportion of filler.
In addition, because the distance between chip and the pin is far away, the length of metal wire is longer, shown in Figure 45～46, and metal wire cost higher (the especially metal wire of Ang Gui proof gold matter); Same because the length of metal wire is longer, make that the signal output speed of chip is slow (especially the product of storage class and the calculating that needs mass data are more outstanding); Too because the length of metal wire is longer, so also higher to the interference of signal in existing dead resistance/parasitic capacitance of metal wire and parasitic electric pole; Because the distance between chip and the pin is far away, make that the volume and the area of encapsulation are bigger again, material cost is higher, and discarded object is more.
For this reason, the applicant in first to file name be called the patent of invention of " base island lead frame structure and production method thereof are arranged ", its application number is: 201010165476.0.Its major technique feature is: adopt the back side of metal substrate to etch partially earlier, form the half-etched regions of depression at the back side of metal substrate, form the back side of Ji Dao and pin simultaneously relatively, again in described half-etched regions, packless soft gap filler in the full-filling, and toast simultaneously, make packless soft underfill cures become packless plastic packaging material (epoxy resin), to wrap the back side of pin.And then etch partially in the front of metal substrate, form the front of Ji Dao and pin simultaneously relatively.Its beneficial effect mainly contains:
1) because the zone between the back side of described metal substrate pin and pin is equipped with packless soft gap filler, this packless soft gap filler has filler plastic packaging material (epoxy resin) to wrap the height of whole pin with the routine in the metal substrate front in the plastic packaging process, so the constraint ability of plastic-sealed body and pin just becomes big, do not have the problem that produces pin again, as Figure 47.
2) owing to adopted the positive method of separating the etching operation of lead frame with the back side, so in the etching operation, can form slightly little and the structure that positive pin size is big slightly of the size of back side pin, and slide and fall pin in the tighter more difficult generation of being wrapped up by packless plastic packaging material (epoxy resin) with the size that varies in size up and down of a pin.
3) separate etched technology owing to used the lead frame back side with the front, so the pin in lead frame front can be extended to as much as possible the next door of Ji Dao, impel chip and pin distance significantly to shorten, as Figure 47～48, so the employed cost of metal wire also can significantly reduce (the especially metal wire of Ang Gui proof gold matter).
4) also because the shortening of metal wire makes also significantly speedup (the especially product of storage class and the calculating that needs mass data of signal output speed of chip, more outstanding), because the length of metal wire has shortened, so existing dead resistance/parasitic capacitance of metal wire and parasitic electric pole are to the also significantly reduction of interference of signal.
5) because of having used the elongation technology of pin,, make the volume and the area of encapsulation significantly to dwindle so can be easy to produce the distance between high pin number and the highdensity pin.
6) because volume after being encapsulated is significantly dwindled, more direct embody material cost significantly descend with because the minimizing of material usage also significantly reduces the puzzlement of discarded object environmental protection.
But, still have following deficiency: because the preceding advanced line lead frame back side of encapsulation does not have the parcel pin operation of filler plastic packaging material, when carrying out the high temperature load in lead frame front and routing operation again, because of the physical property of two kinds of materials of lead frame and no filler plastic packaging material different, the coefficient of expansion of two kinds of materials is also different, at high temperature be subjected to the thermal deformation difference, lead frame produces distortion when causing follow-up load.Therefore this kind encapsulating structure can not superhigh temperature resistant (more than 200 ℃) when load.And be by the packaging body volume being done to such an extent that reach resistant to elevated temperatures requirement very greatly, be with regard to not anti-superhigh temperature under the increasing situation but require the more and more littler and power of the volume of packaging body now. in the past
(3) summary of the invention
The purpose of this utility model is to overcome above-mentioned deficiency, can bear superhigh temperature when a kind of load is provided and can not produce the lead frame distortion, also not have the problem that produces pin and single the encapsulating structure of two-sided graphic chips formal dress that can make the contraction in length of metal wire again because of the different physical properties of different material.
The purpose of this utility model is achieved in that single encapsulating structure of a kind of two-sided graphic chips formal dress, comprise Ji Dao, pin, packless plastic packaging material (epoxy resin), conduction or non-conductive bonding material, chip, metal wire and filler plastic packaging material (epoxy resin) arranged, described pin front extends to next door, basic island, front at described Ji Dao and pin is provided with the first metal layer, be provided with second metal level at the back side of described Ji Dao and pin, on the first metal layer of front, described basic island, be provided with chip by conduction or non-conductive bonding material, be connected with metal wire between chip front side and the pin front the first metal layer, outside the top of described Ji Dao and pin and chip and metal wire, be encapsulated with filler plastic packaging material (epoxy resin), zone in described Ji Dao and pin periphery, zone and the zone between pin and the pin between pin and the basic island are equipped with packless plastic packaging material (epoxy resin), described packless plastic packaging material (epoxy resin) is with Ji Dao and periphery, pin bottom, pin bottom and Ji Dao bottom and pin bottom and pin bottom link into an integrated entity, and make described Ji Dao and pin back side size less than Ji Dao and the positive size of pin, form up big and down small Ji Dao and pin configuration, be characterized in: described have filler plastic packaging material (epoxy resin) that the positive local unit of pin is coated, be provided with pillar at the described pin back side, the pillar root is imbedded in the described packless plastic packaging material (epoxy resin).
The beneficial effects of the utility model are:
1, lead frame superhigh temperature resistant (more than 200 ℃)
Owing to adopted two-sided figure etched lead frame technology, once finish lead frame just, the back of the body the two-sided etching in two sides, the high temperature load routing in advanced line lead frame front carries out the pin parcel operation at the lead frame back side again when encapsulating simultaneously, has only a kind of material of lead frame when making the load routing, superhigh temperature resistant (generally being below the 200 ℃) performance of lead frame has been guaranteed in impact because of there not being multiple material coefficient of expansion difference to be brought in using the processing procedure process of superhigh temperature.
2, can guarantee lead frame load intensity
Do not seal because do not do in advance earlier, the pressure that bears during the lead frame load is big, can make lead frame produce vibration during routing, and the phenomenon of sinking can appear in lead frame.The utility model is by leaving the design of pillar, the intensity of lead frame during with the increase routing at the lead frame back side.
3, guarantee not have again the problem that produces pin
Owing to adopted two-sided etched technology, so planning and designing easily with produce up big and down small pin configuration, the levels plastic packaging material is wrapped up big and down small pin configuration closely together, so the constraint ability of plastic-sealed body and pin just becomes big, do not have the problem that produces pin again.
4, guarantee the contraction in length of metal wire
1) owing to used the lead frame back side with the positive while and separate etched technology, so the pin in lead frame front can be extended to as much as possible the follow-up next door, zone that needs cartridge chip, impel chip and pin distance significantly to shorten, as Figure 47～Figure 48, so the length of metal wire has also shortened, and the cost of metal wire also can significantly reduce (the especially metal wire of Ang Gui proof gold matter);
2) also because the contraction in length of metal wire makes also significantly speedup (the especially product of storage class and the calculating that needs mass data of signal output speed of chip, more outstanding), because the length of metal wire has shortened, so existing dead resistance/parasitic capacitance of metal wire and parasitic electric pole are to the also significantly reduction of interference of signal.
5, the volume of encapsulation and area can significantly be dwindled
Because of having used the elongation technology of pin,, make the volume and the area of encapsulation significantly to dwindle so can be easy to produce the distance between high pin number and highdensity pin and the pin.
6, material cost and material usage reduce
Because volume after being encapsulated is significantly dwindled, more direct embody material cost significantly descend with because the minimizing of material usage also significantly reduces the puzzlement of discarded object environmental protection.
7, the advantage of single encapsulation of the local Single of employing unit has:
1) in different application, the pin at plastic-sealed body edge can be stretched out plastic-sealed body.
2) pin at plastic-sealed body edge stretches out outside the plastic-sealed body and can clearly check out situation about being welded on the pcb board.
3) area of modular type is easy because multiple different shrinkage that material structure produces is different should stand distortion than conference, and single encapsulation of local unit just can disperse fully multiple different shrinkage that material structure produces different should stand distortion.
4) single is encapsulated in when carrying out the plastic-sealed body cutting and separating, because the thickness that cuts has only the thickness of pin, so the speed of cutting can be come much soon than the encapsulating structure of modular type, so and incisory blade because the thickness of cutting just approached life-span of cutting blade relative also just become longer.
(4) description of drawings
Fig. 1 (A)～Fig. 1 (R) is single method for packing embodiment of the two-sided graphic chips formal dress of the utility model 1 each operation schematic diagram.
Fig. 2 is single encapsulating structure embodiment 1 structural representation of the two-sided graphic chips formal dress of the utility model.
Fig. 3 is the vertical view of Fig. 2.
Fig. 4 (A)～Fig. 4 (R) is single method for packing embodiment of the two-sided graphic chips formal dress of the utility model 2 each operation schematic diagram.
Fig. 5 is single encapsulating structure embodiment 2 structural representations of the two-sided graphic chips formal dress of the utility model.
Fig. 6 is the vertical view of Fig. 5.
Fig. 7 (A)～Fig. 7 (R) is single method for packing embodiment of the two-sided graphic chips formal dress of the utility model 3 each operation schematic diagram.
Fig. 8 is single encapsulating structure embodiment 3 structural representations of the two-sided graphic chips formal dress of the utility model.
Fig. 9 is the vertical view of Fig. 8.
Figure 10 (A)～Figure 10 (R) is single method for packing embodiment of the two-sided graphic chips formal dress of the utility model 4 each operation schematic diagram.
Figure 11 is single encapsulating structure embodiment 4 structural representations of the two-sided graphic chips formal dress of the utility model.
Figure 12 is the vertical view of Figure 11.
Figure 13 (A)～Figure 13 (R) is single method for packing embodiment of the two-sided graphic chips formal dress of the utility model 5 each operation schematic diagram.
Figure 14 is single encapsulating structure embodiment 5 structural representations of the two-sided graphic chips formal dress of the utility model.
Figure 15 is the vertical view of Figure 14.
Figure 16 (A)～Figure 16 (R) is single method for packing embodiment of the two-sided graphic chips formal dress of the utility model 6 each operation schematic diagram.
Figure 17 is single encapsulating structure embodiment 6 structural representations of the two-sided graphic chips formal dress of the utility model.
Figure 18 is the vertical view of Figure 17.
Figure 19 (A)～Figure 19 (R) is single method for packing embodiment of the two-sided graphic chips formal dress of the utility model 7 each operation schematic diagram.
Figure 20 is single encapsulating structure embodiment 7 structural representations of the two-sided graphic chips formal dress of the utility model.
Figure 21 is the vertical view of Figure 20.
Figure 22 (A)～Figure 22 (R) is single method for packing embodiment of the two-sided graphic chips formal dress of the utility model 8 each operation schematic diagram.
Figure 23 is single encapsulating structure embodiment 8 structural representations of the two-sided graphic chips formal dress of the utility model.
Figure 24 is the vertical view of Figure 23.
Figure 25 (A)～Figure 25 (R) is single method for packing embodiment of the two-sided graphic chips formal dress of the utility model 9 each operation schematic diagram.
Figure 26 is single encapsulating structure embodiment 9 structural representations of the two-sided graphic chips formal dress of the utility model.
Figure 27 is the vertical view of Figure 26.
Figure 28 (A)～Figure 28 (R) is single method for packing embodiment of the two-sided graphic chips formal dress of the utility model 10 each operation schematic diagram.
Figure 29 is single encapsulating structure embodiment 10 structural representations of the two-sided graphic chips formal dress of the utility model.
Figure 30 is the vertical view of Figure 29.
Figure 31 (A)～Figure 31 (R) is single method for packing embodiment of the two-sided graphic chips formal dress of the utility model 11 each operation schematic diagram.
Figure 32 is single encapsulating structure embodiment 11 structural representations of the two-sided graphic chips formal dress of the utility model.
Figure 33 is the vertical view of Figure 32.
Figure 34 (A)～Figure 34 (R) is single method for packing embodiment of the two-sided graphic chips formal dress of the utility model 12 each operation schematic diagram.
Figure 35 is single encapsulating structure embodiment 12 structural representations of the two-sided graphic chips formal dress of the utility model.
Figure 36 is the vertical view of Figure 35.
Figure 37 (A)～Figure 37 (R) is single method for packing embodiment of the two-sided graphic chips formal dress of the utility model 13 each operation schematic diagram.
Figure 38 is single encapsulating structure embodiment 13 structural representations of the two-sided graphic chips formal dress of the utility model.
Figure 39 is the vertical view of Figure 38.
Figure 40 (A)～Figure 40 (R) is single method for packing embodiment of the two-sided graphic chips formal dress of the utility model 14 each operation schematic diagram.
Figure 41 is single encapsulating structure embodiment 14 structural representations of the two-sided graphic chips formal dress of the utility model.
Figure 42 is the vertical view of Figure 41.
Figure 43 was for to adopt the front of metal substrate to carry out chemical etching and surface electrical coating flow diagram in the past.
Figure 44 pin figure for what formed in the past.
Figure 45 is encapsulating structure one schematic diagram in the past.
Figure 46 is 45 vertical view.
Figure 47 is encapsulating structure two schematic diagrames in the past.
Figure 48 is 47 vertical view.
Reference numeral among the figure:
Base island 1, pin 2, packless plastic packaging material (epoxy resin) 3, the first metal layer 4, second metal level 5, conduction or non-conductive bonding material 6, chip 7, metal wire 8, filler plastic packaging material (epoxy resin) 9, pillar 10, metal substrate 11, photoresistance glued membrane 12, photoresistance glued membrane 13, photoresistance glued membrane 14, photoresistance glued membrane 15 are arranged, connect muscle 16, photoresistance glued membrane 17, photoresistance glued membrane 18; The 1.3, the 4th basic island 1.4, the 1.2, the 3rd basic island, the 1.1, the 3rd basic island, the 3rd basic island.
(5) embodiment
Single encapsulating structure of the two-sided graphic chips formal dress of the utility model is as follows:
Embodiment 1: single basic island individual pen pin
Referring to Fig. 2 and Fig. 3, Fig. 2 is single encapsulating structure embodiment 1 structural representation of the two-sided graphic chips formal dress of the utility model.Fig. 3 is the vertical view of Fig. 2.By Fig. 2 and Fig. 3 as can be seen, single encapsulating structure of the two-sided graphic chips formal dress of the utility model, comprise basic island 1, pin 2, packless plastic packaging material (epoxy resin) 3, conduction or non-conductive bonding material 6, chip 7, metal wire 8 and filler plastic packaging material (epoxy resin) 9 is arranged, described pin 2 fronts extend to 1 next door, basic island, front at described basic island 1 and pin 2 is provided with the first metal layer 4, the back side at described basic island 1 and pin 2 is provided with second metal level 5, on the 1 front the first metal layer 4 of described basic island, be provided with chip 7 by conduction or non-conductive bonding material 6, chip 7 positive with pin 2 front the first metal layers 4 between be connected with metal wire 8, outside the top of described basic island 1 and pin 2 and chip 7 and metal wire 8, be encapsulated with filler plastic packaging material (epoxy resin) 9, this has filler plastic packaging material (epoxy resin) 9 that pin 2 positive local unit are coated, zone in described basic island 1 and pin 2 peripheries, zone between zone between pin 2 and the basic island 1 and pin 2 and the pin 2 is equipped with packless plastic packaging material (epoxy resin) 3, described packless plastic packaging material (epoxy resin) 3 is with basic island 1 and periphery, pin 2 bottom, pin 2 bottoms and 1 bottom, basic island and pin 2 bottoms and pin 2 bottoms link into an integrated entity, and make described Ji Dao and pin back side size less than Ji Dao and the positive size of pin, form up big and down small Ji Dao and pin configuration, be provided with pillar 10 at described pin 2 back sides, pillar 10 roots are imbedded in the described packless plastic packaging material (epoxy resin) 3.
Its method for packing is as follows:
Step 1, get metal substrate
Referring to Fig. 1 (A), get the suitable metal substrate of a slice thickness 11.The material of metal substrate can be carried out conversion according to the function and the characteristic of chip, for example: copper, aluminium, iron, copper alloy or dilval etc.
Step 2, metal substrate front and back side lining photoresistance glued membrane
Referring to Fig. 1 (B), utilize by coating equipment in the front of metal substrate and the back side be covered respectively and can carry out the photoresistance glued membrane 12 and 13 of exposure imaging, to protect follow-up electroplated metal layer process operation.And this photoresistance glued membrane can be a dry type photoresistance pellicle also can be wet type photoresistance glued membrane.
The photoresistance glued membrane in step 3, metal substrate front needs the exposure of plated metal layer region/develop and windows
Referring to Fig. 1 (C), the metal substrate front that utilizes exposure imaging equipment that step 2 is finished photoresistance glued membrane lining operation is carried out exposure imaging and is removed part photoresistance glued membrane, carries out the zone of electroplated metal layer to expose the positive follow-up needs of metal substrate.
The zone of having windowed in step 4, metal substrate front is carried out metal level and is electroplated lining
Referring to Fig. 1 (D), the first metal layer 4 plating linings are carried out in the zone of having windowed in metal substrate front in the step 3, this first metal layer 4 places the front of described basic island 1 and pin 2.
Photoresistance glued membrane striping is carried out at step 5, metal substrate front and the back side
Referring to Fig. 1 (E), the positive remaining photoresistance glued membrane of metal substrate and the photoresistance glued membrane at the metal substrate back side are all removed.
Step 6, metal substrate front and back side lining photoresistance glued membrane
Referring to Fig. 1 (F), utilize by coating equipment in the front of metal substrate and the back side be covered respectively and can carry out the photoresistance glued membrane 14 and 15 of exposure imaging, to protect follow-up etch process operation.And this photoresistance glued membrane can be a dry type photoresistance pellicle also can be wet type photoresistance glued membrane.
The photoresistance glued membrane of step 7, metal substrate needs the exposure of two-sided etching area/develop and windows
Referring to Fig. 1 (G), exposure imaging removal part photoresistance glued membrane is carried out at the metal substrate front and the back side that utilize exposure imaging equipment that step 6 is finished photoresistance glued membrane lining operation, to expose the two-sided etching operation of metal substrate that the localized metallic substrate carries out in order to follow-up needs.
Step 8, metal substrate carry out two-sided etching operation
Referring to Fig. 1 (H), after the exposure/development and windowing task of completing steps seven, the i.e. etching operation of carrying out each figure at the front and the back side of metal substrate, etch the front and back of basic island 1 and pin 2, simultaneously the pin front is extended to as much as possible next door, basic island, and make the positive size of the back side size of described basic island 1 and pin 2, form up big and down small basic island 1 and pin 2 structures less than basic island 1 and pin 2; And form pillar 10 at pin 2 back sides, and at the company's of leaving muscle 16 between basic island 1 and the pin 2 and between pin 2 and the pin 2.
Photoresistance glued membrane striping is carried out at step 9, metal substrate front and the back side
Referring to Fig. 1 (I), the photoresistance glued membrane of metal substrate front and back remainder is all removed, make lead frame,
Step 10, load
Referring to Fig. 1 (J), on the 1 front the first metal layer 4 of basic island, carry out the implantation of chip 7 by conduction or non-conductive bonding material 6.
Step 11, break metal wire
Referring to Fig. 1 (K), the semi-finished product of finishing chip implantation operation are carried out playing metal wire 8 operations between chip front side and the pin front the first metal layer.
Step 12, be encapsulated with filler plastic packaging material (epoxy resin)
Referring to Fig. 1 (L), the semi-finished product front that routing is finished is carried out local unit and is encapsulated with filler plastic packaging material (epoxy resin) 9 operations, pin 2 positive local unit zones are exposed filler plastic packaging material (epoxy resin) 9 is arranged, and carry out curing operation after plastic packaging material is sealed, make the top of Ji Dao and pin and chip and metal wire all be had filler plastic packaging material (epoxy resin) to seal outward.
Step 13, lining photoresistance glued membrane
Referring to Fig. 1 (M), utilize by coating equipment to be covered respectively and can to carry out the photoresistance glued membrane 17 and 18 of exposure imaging will finishing the half-finished front that is encapsulated with filler plastic packaging material (epoxy resin) operation and the back side, to protect follow-up etch process operation.And this photoresistance glued membrane can be a dry type photoresistance pellicle also can be wet type photoresistance glued membrane.
Step 14, finish the exposure that the half-finished back side that is encapsulated with filler plastic packaging material (epoxy resin) operation needs etching area/develop and windowing
Referring to Fig. 1 (N), exposure imaging removal part photoresistance glued membrane is carried out at the semi-finished product back side that is encapsulated with filler plastic packaging material (epoxy resin) operation of finishing that utilizes exposure imaging equipment that step 13 is finished photoresistance glued membrane lining operation, to expose company's muscle 16 that leaves after the two-sided etching operation of step 8 metal substrate and the pillar 10 that forms at pin 2 back sides, carry out the pillar root and connect muscle etching operation in order to follow-up needs.
Step 15, the operation of etching for the second time
Referring to Fig. 1 (O), after the exposure/development and windowing task of completing steps 14, promptly carry out the etching operation of each figure finishing the semi-finished product back side that is encapsulated with filler plastic packaging material (epoxy resin) operation, the company's muscle 16 that leaves after the two-sided etching operation of step 8 metal substrate is all etched away, root at pillar 10 described in this process also can etch away relative thickness simultaneously, make the pillar root not expose the encapsulating structure back side after sealing, avoid producing and open circuit.
Photoresistance glued membrane striping is carried out at step 10 six, semi-finished product front and the back side
Referring to Fig. 1 (P), the photoresistance glued membrane of the semi-finished product back side remainder of completing steps 15 etching operations and the photoresistance glued membrane in semi-finished product front are all removed.
Step 10 seven, seal packless plastic packaging material (epoxy resin)
Referring to Fig. 1 (Q), packless plastic packaging material (epoxy resin) operation is sealed at the semi-finished product back side of completing steps 16 described striping operations, and carry out curing operation after plastic packaging material is sealed, make zone between zone, pin 2 and the basic island 1 of basic island 1 and pin 2 peripheries and the zone between pin 2 and the pin 2 all set packless plastic packaging material (epoxy resin) 3, this packless plastic packaging material
(epoxy resin) 3 links into an integrated entity basic island 1 and periphery, pin 2 bottom, pin 2 bottoms and 1 bottom, basic island and pin 2 bottoms and pin 2 bottoms, and described pillar 10 roots are imbedded in this packless plastic packaging material (epoxy resin) 3.
Specify: but also because many described pillars 10 in packaging body, the structure in packaging body is more strong on the contrary (can be compared to mix increased reinforcing bar in the earth intensity but also flexible are arranged not only)
The back side of step 10 eight, Ji Dao and pin and the front of pin are carried out metal level and are electroplated lining
Referring to Fig. 1 (R), completing steps 17 is sealed the back side of the described Ji Dao of no filler plastic packaging material operation and pin and step 12 is described exposes the plating lining operation that the pin 2 positive local unit zones that filler plastic packaging material (epoxy resin) is arranged are carried out second metal level 5 and the first metal layer 4 respectively, and the material of electroplating can be tin, nickel gold, NiPdAu .... wait metal material.
Step 10 nine, cutting finished product
Referring to Fig. 2 and Fig. 3, the semi-finished product of ten eight the second metal levels of completing steps being electroplated lining carry out cutting operation, make originally more than of chips that connect together in array formula aggregate mode independent, make single encapsulating structure finished product of two-sided graphic chips formal dress.
Embodiment 2: base island exposed type individual pen pin sinks
Referring to Fig. 4～6, Fig. 4 (A)～Fig. 4 (R) is single method for packing embodiment of the two-sided graphic chips formal dress of the utility model 2 each operation schematic diagram.Fig. 5 is single encapsulating structure embodiment 2 structural representations of the two-sided graphic chips formal dress of the utility model.Fig. 6 is the vertical view of Fig. 5.By Fig. 4, Fig. 5 and Fig. 6 as can be seen, embodiment 2 only is with the difference of embodiment 1: described basic island 1 is sinking type Ji Dao, and promptly basic island 1 front middle section sinks.
Embodiment 3: baried type base island individual pen pin
Referring to Fig. 7～9, Fig. 7 (A)～Fig. 7 (R) is single method for packing embodiment of the two-sided graphic chips formal dress of the utility model 3 each operation schematic diagram.Fig. 8 is single encapsulating structure embodiment 3 structural representations of the two-sided graphic chips formal dress of the utility model.Fig. 9 is the vertical view of Fig. 8.By Fig. 7, Fig. 8 and Fig. 9 as can be seen, embodiment 3 only is with the difference of embodiment 1: described basic island 1 is baried type Ji Dao, and 1 back side, promptly basic island is imbedded in the described packless plastic packaging material (epoxy resin) 3.
Embodiment 4: the base island exposed type individual pen of multi-convex point pin
Referring to Figure 10～12, Figure 10 (A)～Figure 10 (R) is single method for packing embodiment of the two-sided graphic chips formal dress of the utility model 4 each operation schematic diagram.Figure 11 is single encapsulating structure embodiment 4 structural representations of the two-sided graphic chips formal dress of the utility model.Figure 12 is the vertical view of Figure 11.By Figure 10, Figure 11 and Figure 12 as can be seen, embodiment 4 only is with the difference of embodiment 1: described basic island 1 is multi-convex point Ji Dao, and 1 surface, promptly basic island is provided with a plurality of salient points.
Embodiment 5: a plurality of base island exposed type individual pen pins
Referring to Figure 13～15, Figure 13 (A)～Figure 13 (R) is single method for packing embodiment of the two-sided graphic chips formal dress of the utility model 5 each operation schematic diagram.Figure 14 is single encapsulating structure embodiment 5 structural representations of the two-sided graphic chips formal dress of the utility model.Figure 15 is the vertical view of Figure 14.By Figure 13～15 as can be seen, embodiment 5 is with the difference of embodiment 1: described basic island 1 has a plurality of, and pin 2 has individual pen.
Embodiment 6: the base island exposed type individual pen of a plurality of sinkings pin
Referring to Figure 16～18, Figure 16 (A)～Figure 16 (R) is single method for packing embodiment of the two-sided graphic chips formal dress of the utility model 6 each operation schematic diagram.Figure 17 is single encapsulating structure embodiment 6 structural representations of the two-sided graphic chips formal dress of the utility model.Figure 18 is the vertical view of Figure 17.By Figure 16～18 as can be seen, embodiment 6 is with the difference of embodiment 2: described basic island 1 has a plurality of, and pin 2 has individual pen.
Embodiment 7: a plurality of baried type bases island individual pen pin
Referring to Figure 19～21, Figure 19 (A)～Figure 19 (R) is single method for packing embodiment of the two-sided graphic chips formal dress of the utility model 7 each operation schematic diagram.Figure 20 is single encapsulating structure embodiment 7 structural representations of the two-sided graphic chips formal dress of the utility model.Figure 21 is the vertical view of Figure 20.By Figure 19～21 as can be seen, embodiment 7 is with the difference of embodiment 3: described basic island 1 has a plurality of, and pin 2 has individual pen.
Embodiment 8: the base island exposed type individual pen of a plurality of multi-convex points pin
Referring to Figure 22～24, Figure 22 (A)～Figure 22 (R) is single method for packing embodiment of the two-sided graphic chips formal dress of the utility model 8 each operation schematic diagram.Figure 23 is single encapsulating structure embodiment 8 structural representations of the two-sided graphic chips formal dress of the utility model.Figure 24 is the vertical view of Figure 23.By Figure 22～24 as can be seen, embodiment 8 is with the difference of embodiment 4: described basic island 1 has a plurality of, and pin 2 has individual pen.
Embodiment 9: the base island exposed type and the base island exposed type individual pen pin that sinks
Referring to Figure 25～27, Figure 25 (A)～Figure 25 (R) is single method for packing embodiment of the two-sided graphic chips formal dress of the utility model 9 each operation schematic diagram.Figure 26 is single encapsulating structure embodiment 9 structural representations of the two-sided graphic chips formal dress of the utility model.Figure 27 is the vertical view of Figure 26.By Figure 25～27 as can be seen, embodiment 9 is with the difference of embodiment 1: described basic island 1 has two groups also can be many group Ji Dao, one group is the first basic island 1.1, another group is the second basic island 1.2, the described second basic island 1.2 front middle sections sink, front at the described first basic island 1.1 and pin 2 is provided with the first metal layer 4, on the described first basic island 1.1, the back side of the second basic island 1.2 and pin 2 is provided with second metal level 5, by conduction or non-conductive bonding material 6 chip 7 is set in the second basic island 1.2 positive central sunken regions and 1.1 fronts, the first basic island, chip 7 positive with pin 2 front the first metal layers 4 between and all be connected between chip 7 and the chip 7 with metal wire 8, zone in described pin 2 peripheries, zone between the pin 2 and the first basic island 1.1, zone between the first basic island 1.1 and the second basic island 1.2, no filler plastic packaging material 3 is set in zone between the second basic island 1.2 and the pin 2 and the zone between pin 2 and the pin 2, described no filler plastic packaging material 3 is with periphery, pin bottom, pin 2 and 1.1 bottoms, the first basic island, the first basic island 1.1 and 1.2 bottoms, the second basic island, the second basic island 1.2 links into an integrated entity with pin 2 bottoms with pin 2 bottoms and pin 2, and described pin 2 has individual pen.
Embodiment 10: base island exposed type and baried type base island individual pen pin
Referring to Figure 28～30, Figure 28 (A)～Figure 28 (R) is single method for packing embodiment of the two-sided graphic chips formal dress of the utility model 10 each operation schematic diagram.Figure 29 is single encapsulating structure embodiment 10 structural representations of the two-sided graphic chips formal dress of the utility model.Figure 30 is the vertical view of Figure 29.By Figure 28～30 as can be seen, embodiment 10 is with the difference of embodiment 1: described basic island 1 has two groups also can be many group Ji Dao, one group is the first basic island 1.1, another group is the 3rd basic island 1.3, front at described first the 3rd basic island 1.3, basic island 1.1 and pin 2 is provided with the first metal layer 4, the back side at the described first basic island 1.1 and pin 2 is provided with second metal level 5, chip 7 positive with pin 2 front the first metal layers 4 between and all be connected between chip 7 and the chip 7 with metal wire 8, zone in described pin 2 peripheries, zone between the pin 2 and the first basic island 1.1,1.3 back sides, the 3rd basic island, zone between the 3rd basic island 1.3 and the first basic island 1.1, no filler plastic packaging material 3 is set in zone and the zone between pin and the pin between the 3rd basic island 1.3 and the pin 2, described no filler plastic packaging material 3 is with periphery, pin bottom, pin 2 and 1.1 bottoms, the first basic island, 1.3 back sides, the 3rd basic island, the 3rd 1.3 back sides, basic island and 1.1 bottoms, the first basic island, the 3rd 1.3 back sides, basic island and pin 2 bottoms and pin 2 link into an integrated entity with pin 2 bottoms, and described pin 2 is provided with individual pen.
Embodiment 11: the base island exposed type individual pen of base island exposed type and multi-convex point pin
Referring to Figure 31～33, Figure 31 (A)～Figure 31 (R) is single method for packing embodiment of the two-sided graphic chips formal dress of the utility model 11 each operation schematic diagram.Figure 32 is single encapsulating structure embodiment 11 structural representations of the two-sided graphic chips formal dress of the utility model.Figure 33 is the vertical view of Figure 32.By Figure 31～33 as can be seen, embodiment 11 is with the difference of embodiment 1: described basic island 1 has two groups also can be many group Ji Dao, one group is the first basic island 1.1, another group is the 4th basic island 1.4, multi-convex point shape structure is arranged in 1.4 fronts, the described the 4th basic island, zone in described pin 2 peripheries, zone between the pin 2 and the first basic island 1.1, zone between the first basic island 1.1 and the 4th basic island 1.4, no filler plastic packaging material 3 is set in zone between the 4th basic island 1.4 and the pin 2 and the zone between pin 2 and the pin 2, described packless plastic packaging material (epoxy resin) 3 is with periphery, pin bottom, pin 2 and 1.1 bottoms, the first basic island, the first basic island 1.1 and 1.4 bottoms, the 4th basic island, the 4th basic island 1.4 links into an integrated entity with pin 2 bottoms with pin 2 bottoms and pin 2, and described pin 2 is provided with individual pen.
Embodiment 12: the base island exposed type individual pen of base island exposed type and baried type pin sinks
Referring to Figure 34～36, Figure 34 (A)～Figure 34 (R) is single method for packing embodiment of the two-sided graphic chips formal dress of the utility model 12 each operation schematic diagram.Figure 35 is single encapsulating structure embodiment 12 structural representations of the two-sided graphic chips formal dress of the utility model.Figure 36 is the vertical view of Figure 35.By Figure 34～36 as can be seen, embodiment 12 is with the difference of embodiment 1: described basic island 1 has two groups also can be many group Ji Dao, one group is the second basic island 1.2, another group is the 3rd basic island 1.3, the described second basic island 1.2 front middle sections sink, by conduction or non-conductive bonding material 6 chip 7 is set in the second basic island 1.2 positive central sunken regions and 1.3 fronts, the 3rd basic island, zone in described pin 2 peripheries, zone between the pin 2 and the second basic island 1.2,1.3 back sides, the 3rd basic island, zone between the second Ji Dao back side 1.2 and the second basic island 1.2, no filler plastic packaging material 3 is set in zone and the zone between pin and the pin between the 3rd 1.3 back sides, basic island and the pin 2, described no filler plastic packaging material 3 is with periphery, pin bottom, pin 2 and 1.2 bottoms, the second basic island, the 3rd basic island 1.3, the 3rd basic island 1.3 and 1.2 bottoms, the second basic island, the 3rd 1.3 back sides, basic island and pin 2 bottoms and pin 2 link into an integrated entity with pin 2 bottoms, and described pin 2 is provided with a circle.
Embodiment 13: the base island exposed type individual pen of base island exposed type and multi-convex point pin sinks
Referring to Figure 37～39, Figure 37 (A)～Figure 37 (R) is single method for packing embodiment of the two-sided graphic chips formal dress of the utility model 13 each operation schematic diagram.Figure 38 is single encapsulating structure embodiment 13 structural representations of the two-sided graphic chips formal dress of the utility model.Figure 39 is the vertical view of Figure 38.By Figure 37～39 as can be seen, embodiment 13 is with the difference of embodiment 1: described basic island 1 has two groups also can be many group Ji Dao, one group is the second basic island 1.2, another group is the 4th basic island 1.4, the described second basic island 1.2 front middle sections sink, multi-convex point shape structure is arranged in 1.4 fronts, the 4th basic island, front at the described the 4th basic island 1.4 and pin 2 is provided with the first metal layer 4, on the described second basic island 1.2, the back side of the 4th basic island 1.4 and pin 2 is provided with second metal level 5, by conduction or non-conductive bonding material 6 chip 7 is set in the described second basic island 1.2 positive central sunken regions and 1.4 fronts, the 4th basic island, zone in described pin 2 peripheries, zone between the pin 2 and the second basic island 1.2, zone between the second basic island 1.2 and the 4th basic island 1.4, no filler plastic packaging material 3 is set in zone between the 4th basic island 1.4 and the pin 2 and the zone between pin 2 and the pin 2, described packless plastic packaging material (epoxy resin) 3 is with periphery, pin bottom, pin 2 and 1.2 bottoms, the second basic island, the second basic island 1.2 and 1.4 bottoms, the 4th basic island, the 4th basic island 1.4 links into an integrated entity with pin 2 bottoms with pin 2 bottoms and pin 2, and described pin 2 is provided with a circle.
Embodiment 14: the base island exposed type individual pen of baried type Ji Dao and multi-convex point pin
Referring to Figure 40～42, Figure 40 (A)～Figure 40 (R) is single method for packing embodiment of the two-sided graphic chips formal dress of the utility model 14 each operation schematic diagram.Figure 41 is single encapsulating structure embodiment 14 structural representations of the two-sided graphic chips formal dress of the utility model.Figure 42 is the vertical view of Figure 41.By Figure 40～42 as can be seen, embodiment 14 is with the difference of embodiment 1: described basic island 1 has two groups also can be many group Ji Dao, one group is the 3rd basic island 1.3, another group is the 4th basic island 1.4, multi-convex point shape structure is arranged in 1.4 fronts, the described the 4th basic island, on the described the 3rd basic island 1.3, the front of the 4th basic island 1.4 and pin 2 is provided with the first metal layer 4, the back side at the described the 4th basic island 1.4 and pin 2 is provided with second metal level 5, zone in described pin 2 peripheries, zone between pin 2 and the 4th basic island 1.4,1.3 back sides, the 3rd basic island, zone between the second basic island 1.2 and the 4th basic island 1.4, no filler plastic packaging material 3 is set in zone and the zone between pin and the pin between the 3rd basic island 1.3 and the pin 2, described no filler plastic packaging material 3 is with periphery, pin bottom, pin 2 and 1.4 bottoms, the 4th basic island, 1.3 back sides, the 3rd basic island, the 3rd 1.3 back sides, basic island and 1.4 bottoms, the 4th basic island, the 3rd 1.3 back sides, basic island and pin 2 bottoms and pin 2 link into an integrated entity with pin 2 bottoms, and described pin 2 is provided with a circle.

Claims (12)

1. single encapsulating structure of a two-sided graphic chips formal dress, comprise Ji Dao (1), pin (2), packless plastic packaging material (3), conduction or non-conductive bonding material (6), chip (7), metal wire (8) and filler plastic packaging material (9) is arranged, described pin (2) front extends to Ji Dao (1) next door, front at described Ji Dao (1) and pin (2) is provided with the first metal layer (4), the back side at described Ji Dao (1) and pin (2) is provided with second metal level (5), upward be provided with chip (7) at described Ji Dao (1) front the first metal layer (4) by conduction or non-conductive bonding material (6), chip (7) positive with pin (2) front the first metal layer (4) between be connected with metal wire (8), outside the top of described Ji Dao (1) and pin (2) and chip (7) and metal wire (8), be encapsulated with filler plastic packaging material (9), in described Ji Dao (1) and the peripheral zone of pin (2), zone between zone between pin (2) and the Ji Dao (1) and pin (2) and the pin (2) is equipped with packless plastic packaging material (3), described packless plastic packaging material (3) is with Ji Dao (1) and pin (2) periphery, bottom, pin (2) bottom and Ji Dao (1) bottom and pin (2) bottom and pin (2) bottom link into an integrated entity, and make described Ji Dao and pin back side size less than Ji Dao and the positive size of pin, form up big and down small Ji Dao and pin configuration, it is characterized in that: described have filler plastic packaging material (9) that the positive local unit of pin (2) is coated, be provided with pillar (10) at described pin (2) back side, pillar (10) root is imbedded in the described packless plastic packaging material (3).
2. single encapsulating structure of a kind of two-sided graphic chips formal dress according to claim 1 is characterized in that Ji Dao (1) back side exposes described packless plastic packaging material (3).
3. single encapsulating structure of a kind of two-sided graphic chips formal dress according to claim 1 is characterized in that Ji Dao (1) front middle section sinks.
4. single encapsulating structure of a kind of two-sided graphic chips formal dress according to claim 1 is characterized in that Ji Dao (1) back side imbeds in the described packless plastic packaging material (3).
5. single encapsulating structure of a kind of two-sided graphic chips formal dress according to claim 1 is characterized in that described Ji Dao (1) front is arranged to multi-convex point shape structure.
6. according to single encapsulating structure of one of them described a kind of two-sided graphic chips formal dress of claim 1～5, it is a plurality of to it is characterized in that described Ji Dao (1) has, and pin (2) has individual pen.
7. single encapsulating structure of a kind of two-sided graphic chips formal dress according to claim 1, it is characterized in that described Ji Dao (1) has two groups, one group is first Ji Dao (1.1), another group is second Ji Dao (1.2), described second Ji Dao (1.2) front middle section sinks, front at described first Ji Dao (1.1) and pin (2) is provided with the first metal layer (4), at described first Ji Dao (1.1), the back side of second Ji Dao (1.2) and pin (2) is provided with second metal level (5), be provided with chip (7) in positive central sunken regions of second Ji Dao (1.2) and first Ji Dao (1.1) front by conduction or non-conductive bonding material (6), chip (7) positive with pin (2) front the first metal layer (4) between and all use metal wire (8) to be connected between chip (7) and the chip (7), in the peripheral zone of described pin (2), zone between pin (2) and first Ji Dao (1.1), zone between first Ji Dao (1.1) and second Ji Dao (1.2), no filler plastic packaging material (3) is set in zone between zone between second Ji Dao (1.2) and the pin (2) and pin (2) and the pin (2), described no filler plastic packaging material (3) is with periphery, pin bottom, pin (2) and first Ji Dao (1.1) bottom, first Ji Dao (1.1) and second Ji Dao (1.2) bottom, second Ji Dao (1.2) links into an integrated entity with pin (2) bottom with pin (2) bottom and pin (2), and described pin (2) is provided with individual pen.
8. single encapsulating structure of a kind of two-sided graphic chips formal dress according to claim 1, it is characterized in that described Ji Dao (1) has two groups, one group is first Ji Dao (1.1), another group is the 3rd Ji Dao (1.3), front at described first Ji Dao (1.1) the 3rd Ji Dao (1.3) and pin (2) is provided with the first metal layer (4), the back side at described first Ji Dao (1.1) and pin (2) is provided with second metal level (5), be provided with chip (7) in Ji Dao (1) front by conduction or non-conductive bonding material (6), chip (7) positive with pin (2) front the first metal layer (4) between and all use metal wire (8) to be connected between chip (7) and the chip (7), outside the top of described Ji Dao (1) and pin (2) and chip (7) and metal wire (8), be encapsulated with filler plastic packaging material (9), in the peripheral zone of described pin (2), zone between pin (2) and first Ji Dao (1.1), the 3rd Ji Dao (1.3) back side, zone between second Ji Dao (1.2) and first Ji Dao (1.1), no filler plastic packaging material (3) is set in zone and the zone between pin and the pin between the 3rd Ji Dao (1.3) and the pin (2), described no filler plastic packaging material (3) is with periphery, pin bottom, pin (2) and first Ji Dao (1.1) bottom, the 3rd Ji Dao (1.3) back side, the 3rd Ji Dao (1.3) back side and first Ji Dao (1.1) bottom, the 3rd Ji Dao (1.3) back side and pin (2) bottom and pin (2) link into an integrated entity with pin (2) bottom, and described pin (2) is provided with individual pen.
9. single encapsulating structure of a kind of two-sided graphic chips formal dress according to claim 1, it is characterized in that described Ji Dao (1) has two groups, one group is first Ji Dao (1.1), another group is the 4th Ji Dao (1.4), described the 4th Ji Dao (1.4) is arranged to multi-convex point shape structure in the front, in the peripheral zone of described pin (2), zone between pin (2) and first Ji Dao (1.1), zone between first Ji Dao (1.1) and the 4th Ji Dao (1.4), no filler plastic packaging material (3) is set in zone between zone between the 4th Ji Dao (1.4) and the pin (2) and pin (2) and the pin (2), described packless plastic packaging material (3) is with periphery, pin bottom, pin (2) and first Ji Dao (1.1) bottom, first Ji Dao (1.1) and the 4th Ji Dao (1.4) bottom, the 4th Ji Dao (1.4) links into an integrated entity with pin (2) bottom with pin (2) bottom and pin (2), and described pin (2) is provided with individual pen.
10. single encapsulating structure of a kind of two-sided graphic chips formal dress according to claim 1, it is characterized in that described Ji Dao (1) has two groups also can be many group Ji Dao, one group is second Ji Dao (1.2), another group is the 3rd Ji Dao (1.3), described second Ji Dao (1.2) front middle section sinks, be provided with chip (7) in positive central sunken regions of second Ji Dao (1.2) and the 3rd Ji Dao (1.3) front by conduction or non-conductive bonding material (6), in the peripheral zone of described pin (2), zone between pin (2) and second Ji Dao (1.2), the 3rd Ji Dao (1.3) back side, zone between the second Ji Dao back side (1.2) and second Ji Dao (1.2), no filler plastic packaging material (3) is set in zone and the zone between pin and the pin between the 3rd Ji Dao (1.3) back side and the pin (2), described no filler plastic packaging material (3) is with periphery, pin bottom, pin (2) and second Ji Dao (1.2) bottom, the 3rd Ji Dao (1.3), the 3rd Ji Dao (1.3) and second Ji Dao (1.2) bottom, the 3rd Ji Dao (1.3) back side and pin (2) bottom and pin (2) link into an integrated entity with pin (2) bottom, and described pin (2) is provided with individual pen.
11. single encapsulating structure of a kind of two-sided graphic chips formal dress according to claim 1, it is characterized in that described Ji Dao (1) has two groups, one group is second Ji Dao (1.2), another group is the 4th Ji Dao (1.4), described second Ji Dao (1.2) front middle section sinks, the 4th Ji Dao (1.4) is arranged to multi-convex point shape structure in the front, front at described the 4th Ji Dao (1.4) and pin (2) is provided with the first metal layer (4), at described second Ji Dao (1.2), the back side of the 4th Ji Dao (1.4) and pin (2) is provided with second metal level (5), be provided with chip (7) in positive central sunken regions of described second Ji Dao (1.2) and the 4th Ji Dao (1.4) front by conduction or non-conductive bonding material (6), in the peripheral zone of described pin (2), zone between pin (2) and second Ji Dao (1.2), zone between second Ji Dao (1.2) and the 4th Ji Dao (1.4), no filler plastic packaging material (3) is set in zone between zone between the 4th Ji Dao (1.4) and the pin (2) and pin (2) and the pin (2), described packless plastic packaging material (3) is with periphery, pin bottom, pin (2) and second Ji Dao (1.2) bottom, second Ji Dao (1.2) and the 4th Ji Dao (1.4) bottom, the 4th Ji Dao (1.4) links into an integrated entity with pin (2) bottom with pin (2) bottom and pin (2), and described pin (2) is provided with individual pen.
12. single encapsulating structure of a kind of two-sided graphic chips formal dress according to claim 1, it is characterized in that described Ji Dao (1) has two groups, one group is the 3rd Ji Dao (1.3), another group is the 4th Ji Dao (1.4), described the 4th Ji Dao (1.4) is arranged to multi-convex point shape structure in the front, at described the 3rd Ji Dao (1.3), the front of the 4th Ji Dao (1.4) and pin (2) is provided with the first metal layer (4), the back side at described the 4th Ji Dao (1.4) and pin (2) is provided with second metal level (5), in the peripheral zone of described pin (2), zone between pin (2) and the 4th Ji Dao (1.4), the 3rd Ji Dao (1.3) back side, zone between second Ji Dao (1.2) and the 4th Ji Dao (1.4), no filler plastic packaging material (3) is set in zone and the zone between pin and the pin between the 3rd Ji Dao (1.3) and the pin (2), described no filler plastic packaging material (3) is with periphery, pin bottom, pin (2) and the 4th Ji Dao (1.4) bottom, the 3rd Ji Dao (1.3) back side, the 3rd Ji Dao (1.3) back side and the 4th Ji Dao (1.4) bottom, the 3rd Ji Dao (1.3) back side and pin (2) bottom and pin (2) link into an integrated entity with pin (2) bottom, and described pin (2) is provided with individual pen.
CN2010205178864U 2010-09-04 2010-09-04 Double-sided graphics chip positive single packaging structure Expired - Lifetime CN201936874U (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101958303A (en) * 2010-09-04 2011-01-26 江苏长电科技股份有限公司 Double-side graph chip forward single package structure and package method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101958303A (en) * 2010-09-04 2011-01-26 江苏长电科技股份有限公司 Double-side graph chip forward single package structure and package method thereof

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