CN201838579U - Module packaging structure for direct arranging of chip with double-sided graphics - Google Patents
Module packaging structure for direct arranging of chip with double-sided graphics Download PDFInfo
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- CN201838579U CN201838579U CN201020517878XU CN201020517878U CN201838579U CN 201838579 U CN201838579 U CN 201838579U CN 201020517878X U CN201020517878X U CN 201020517878XU CN 201020517878 U CN201020517878 U CN 201020517878U CN 201838579 U CN201838579 U CN 201838579U
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- pin
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- plastic packaging
- packaging material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
The utility model relates to a module packaging structure for the direct arranging of a chip with double-sided graphics, which comprises a pin (2), packless plastic package material (epoxy resin) (3), nonconductive bonding material (6), a chip (7), metal wires (8) and pack plastic package material (epoxy resin) (9), wherein the front surface of the pin (2) extends below the area of a chip attached subsequently as much as possible; the pack plastic package material (9) is packaged at the upper part of the pin (2) and outside the chip (7) and the metal wires (8); the packless plastic package material (3) is embedded in the peripheral area of the pin (2) and in the area between the pins (2), so that the back size of the pin (2) is less than the front size of the pin (2); a pin structure with larger upper part and smaller lower part is formed; the back surface of a pin (1) is provided with a pillar (10); and the root of the pillar (10) is embedded in the packless plastic package material (3). When being used for packaging, according to the structure, the ultra-temperature can be born, lead frame is not distorted due to different physical properties of different materials, and the pin-falling problem never occurs.
Description
(1) technical field
The utility model relates to a kind of two-sided graphic chips and directly puts module package structure.Belong to the semiconductor packaging field.
(2) background technology
The production method of traditional chip-packaging structure is: after chemical etching and surface electrical coating are carried out in the front of employing metal substrate, promptly finish the making (as shown in Figure 4) of lead frame.Etching is then carried out at the back side of lead frame again in encapsulation process.This method has the following disadvantages:
Because only carried out the work that etches partially before the plastic packaging in the metal substrate front, and plastic packaging material only wraps the height of half pin of pin in the plastic packaging process, so the constraint ability of plastic-sealed body and pin has just diminished, when if the plastic-sealed body paster is not fine to pcb board, do over again again and heavily paste, with regard to the problem (as shown in Figure 5) that is easy to generate pin.Especially the kind of plastic packaging material is to adopt when filler is arranged, because material is at the environment and the follow-up surface-pasted stress changing relation of production process, can cause metal and plastic packaging material to produce the crack of vertical-type, its characteristic is the high more then hard more crisp more crack that is easy to generate more of proportion of filler.
In addition, because the distance between chip and the pin is far away, the length of metal wire is longer, shown in Fig. 6～7, and metal wire cost higher (the especially metal wire of Ang Gui proof gold matter); Same because the length of metal wire is longer, make that the signal output speed of chip is slow (especially the product of storage class and the calculating that needs mass data are more outstanding); Too because the length of metal wire is longer, so also higher to the interference of signal in existing dead resistance/parasitic capacitance of metal wire and parasitic electric pole; Because the distance between chip and the pin is far away, make that the volume and the area of encapsulation are bigger again, material cost is higher, and discarded object is more.
For this reason, the applicant in first to file name be called the utility model patent of " direct chip placing encapsulating structure ", its application number is: 201020182528.2.Its major technique feature is: adopt the back side of metal substrate to etch partially earlier, form the half-etched regions of depression at the back side of metal substrate, form the back side of Ji Dao and pin simultaneously relatively, again in described half-etched regions, packless soft gap filler in the full-filling, and toast simultaneously, make packless soft underfill cures become packless plastic packaging material (epoxy resin), to wrap the back side of pin.And then etch partially in the front of metal substrate, form the front of Ji Dao and pin simultaneously relatively.Its beneficial effect mainly contains:
1) because the zone between the back side of described metal substrate pin and pin is equipped with packless soft gap filler, this packless soft gap filler has filler plastic packaging material (epoxy resin) to wrap the height of whole pin with the routine in the metal substrate front in the plastic packaging process, so the constraint ability of plastic-sealed body and pin just becomes big, do not have the problem that produces pin again, as Fig. 8～9.
2) owing to adopted the positive method of separating the etching operation of lead frame with the back side, so in the etching operation, can form slightly little and the structure that positive pin size is big slightly of the size of back side pin, and slide and fall pin in the tighter more difficult generation of being wrapped up by packless plastic packaging material (epoxy resin) with the size that varies in size up and down of a pin.
3) separate etched technology owing to used the lead frame back side with the front, so the pin in lead frame front can be extended to as much as possible the center of packaging body, impel chip and pin distance significantly to shorten, as Fig. 8～9, so the employed cost of metal wire also can significantly reduce (the especially metal wire of Ang Gui proof gold matter).
4) also because the shortening of metal wire makes also significantly speedup (the especially product of storage class and the calculating that needs mass data of signal output speed of chip, more outstanding), because the length of metal wire has shortened, so existing dead resistance/parasitic capacitance of metal wire and parasitic electric pole are to the also significantly reduction of interference of signal.
5) because of having used the elongation technology of pin,, make the volume and the area of encapsulation significantly to dwindle so can be easy to produce the distance between high pin number and the highdensity pin.
6) because volume after being encapsulated is significantly dwindled, more direct embody material cost significantly descend with because the minimizing of material usage also significantly reduces the puzzlement of discarded object environmental protection.
But, still have following deficiency: because the preceding advanced line lead frame back side of encapsulation does not have the parcel pin operation of filler plastic packaging material, when carrying out the high temperature load in lead frame front and routing operation again, because of the physical property of two kinds of materials of lead frame and no filler plastic packaging material different, the coefficient of expansion of two kinds of materials is also different, at high temperature be subjected to the thermal deformation difference, lead frame produces distortion when causing follow-up load.Therefore this kind encapsulating structure can not superhigh temperature resistant (more than 200 ℃) when load.And be by the packaging body volume being done to such an extent that reach resistant to elevated temperatures requirement very greatly, be with regard to not anti-superhigh temperature under the increasing situation but require the more and more littler and power of the volume of packaging body now. in the past
(3) summary of the invention
The purpose of this utility model is to overcome above-mentioned deficiency, can bear superhigh temperature when a kind of load is provided and can not produce the lead frame distortion, also not have the problem that produces pin again and can make the two-sided graphic chips of the contraction in length of metal wire directly put module package structure because of the different physical properties of different material.
The purpose of this utility model is achieved in that a kind of two-sided graphic chips directly puts module package structure, comprise pin, packless plastic packaging material (epoxy resin), non-conductive bonding material, chip, metal wire and filler plastic packaging material (epoxy resin) arranged, described pin front extends to the below, zone of follow-up pasting chip as much as possible, front at described pin is provided with the first metal layer, be provided with second metal level at the back side of described pin, pin front below the zone of described follow-up pasting chip is provided with chip by non-conductive bonding material, be connected with metal wire between chip front side and the pin front the first metal layer, outside the top of described pin and chip and metal wire, be encapsulated with filler plastic packaging material (epoxy resin).Zone and the zone between pin and the pin in described pin periphery are equipped with packless plastic packaging material (epoxy resin), described packless plastic packaging material (epoxy resin) links into an integrated entity periphery, pin bottom and pin bottom and pin bottom, and make described pin back side size less than the positive size of pin, form up big and down small pin configuration, be provided with pillar at the described pin back side, the pillar root is imbedded in the described packless plastic packaging material (epoxy resin).
The beneficial effects of the utility model are:
1, lead frame superhigh temperature resistant (more than 200 ℃)
Owing to adopted two-sided figure etched lead frame technology, once finish lead frame just, the back of the body the two-sided etching in two sides, the high temperature load routing in advanced line lead frame front carries out the pin parcel operation at the lead frame back side again when encapsulating simultaneously, has only a kind of material of lead frame when making the load routing, superhigh temperature resistant (generally being below the 200 ℃) performance of lead frame has been guaranteed in impact because of there not being multiple material coefficient of expansion difference to be brought in using the processing procedure process of superhigh temperature.
2, can guarantee lead frame load intensity
Do not seal because do not do in advance earlier, the pressure that bears during the lead frame load is big, can make lead frame produce vibration during load, and the phenomenon of sinking can appear in lead frame.The utility model is by leaving the design of pillar, the intensity of lead frame during with the increase load at the lead frame back side.
3, guarantee not have again the problem that produces pin
Owing to adopted two-sided etched technology, so planning and designing easily with produce up big and down small pin configuration, the levels plastic packaging material is wrapped up big and down small pin configuration closely together, so the constraint ability of plastic-sealed body and pin just becomes big, do not have the problem that produces pin again.
4, guarantee the contraction in length of metal wire
1) owing to used the lead frame back side with the positive while and separate etched technology, so the pin in lead frame front can be extended to as much as possible the center of packaging body, impel chip and pin distance significantly to shorten, so the length of metal wire has also shortened, and the cost of metal wire also can significantly reduce (the especially metal wire of Ang Gui proof gold matter);
2) also because the contraction in length of metal wire makes also significantly speedup (the especially product of storage class and the calculating that needs mass data of signal output speed of chip, more outstanding), because the length of metal wire has shortened, so existing dead resistance/parasitic capacitance of metal wire and parasitic electric pole are to the also significantly reduction of interference of signal.
5, the volume of encapsulation and area can significantly be dwindled
Because of having used the elongation technology of pin,, make the volume and the area of encapsulation significantly to dwindle so can be easy to produce the distance between high pin number and highdensity pin and the pin.
6, material cost and material usage reduce
Because volume after being encapsulated is significantly dwindled, more direct embody material cost significantly descend with because the minimizing of material usage also significantly reduces the puzzlement of discarded object environmental protection.
(4) description of drawings
Fig. 1 (A)～Fig. 1 (R) directly puts each production process schematic diagram of module package structure for the two-sided graphic chips of the utility model.
Fig. 2 directly puts the module package structure schematic diagram for the two-sided graphic chips of the utility model.
Fig. 3 is the vertical view of Fig. 2.
Fig. 4 was for to adopt the front of metal substrate to carry out chemical etching and surface electrical coating flow diagram in the past.
Fig. 5 pin figure for what formed in the past.
Fig. 6 is encapsulating structure one schematic diagram in the past.
Fig. 7 is the vertical view of Fig. 6.
Fig. 8 is encapsulating structure two schematic diagrames in the past.
Fig. 9 is the vertical view of Fig. 8.
Reference numeral among the figure:
(5) embodiment
Referring to Fig. 2 and Fig. 3, Fig. 2 directly puts the module package structure schematic diagram for the two-sided graphic chips of the utility model.Fig. 3 is the vertical view of Fig. 2.By Fig. 2 and Fig. 3 as can be seen, the two-sided graphic chips of the utility model is directly put module package structure, comprise pin 2, packless plastic packaging material (epoxy resin) 3, non-conductive bonding material 6, chip 7, metal wire 8 and filler plastic packaging material (epoxy resin) 9 is arranged, described pin 2 fronts extend to the below, zone of follow-up pasting chip as much as possible, be provided with the first metal layer 4 in the front of described pin 2, be provided with second metal level 5 at the back side of described pin 2, pin 2 fronts below the zone of described follow-up pasting chip are provided with chip 7 by non-conductive bonding material 6, chip 7 positive with pin 2 front the first metal layers 4 between be connected with metal wire 8, outside the top of described pin 2 and chip 7 and metal wire 8, be encapsulated with filler plastic packaging material (epoxy resin) 9.Be equipped with packless plastic packaging material (epoxy resin) 3 in the zone of described pin 2 peripheries and the zone between pin 2 and the pin 2, described packless plastic packaging material (epoxy resin) 3 links into an integrated entity pin periphery, 2 bottom and pin 2 bottoms and pin 2 bottoms, and make described pin 2 back side sizes less than pin 2 positive sizes, form up big and down small pin configuration, be provided with pillar 10 at described pin 2 back sides, pillar 10 roots are imbedded in the described packless plastic packaging material (epoxy resin) 3.
Its method for packing is as follows:
Step 1, get metal substrate
Referring to Fig. 1 (A), get the suitable metal substrate of a slice thickness 11.The material of metal substrate can be carried out conversion according to the function and the characteristic of chip, for example: copper, aluminium, iron, copper alloy or dilval etc.
Referring to Fig. 1 (B), utilize by coating equipment in the front of metal substrate and the back side be covered respectively and can carry out the photoresistance glued membrane 12 and 13 of exposure imaging, to protect follow-up electroplated metal layer process operation.And this photoresistance glued membrane can be a dry type photoresistance pellicle also can be wet type photoresistance glued membrane.
The photoresistance glued membrane in step 3, metal substrate front needs the exposure of plated metal layer region/develop and windows
Referring to Fig. 1 (C), the metal substrate front that utilizes exposure imaging equipment that step 2 is finished photoresistance glued membrane lining operation is carried out exposure imaging and is removed part photoresistance glued membrane, carries out the zone of electroplated metal layer to expose the positive follow-up needs of metal substrate.
The zone of having windowed in step 4, metal substrate front is carried out metal level and is electroplated lining
Referring to Fig. 1 (D), the first metal layer 4 plating linings are carried out in the zone of having windowed in metal substrate front in the step 3, this first metal layer 4 places the front of described pin 2.
Photoresistance glued membrane striping is carried out at step 5, metal substrate front and the back side
Referring to Fig. 1 (E), the positive remaining photoresistance glued membrane of metal substrate and the photoresistance glued membrane at the metal substrate back side are all removed.
Referring to Fig. 1 (F), utilize by coating equipment in the front of metal substrate and the back side be covered respectively and can carry out the photoresistance glued membrane 14 and 15 of exposure imaging, to protect follow-up etch process operation.And this photoresistance glued membrane can be a dry type photoresistance pellicle also can be wet type photoresistance glued membrane.
The photoresistance glued membrane of step 7, metal substrate needs the exposure of two-sided etching area/develop and windows
Referring to Fig. 1 (G), exposure imaging removal part photoresistance glued membrane is carried out at the metal substrate front and the back side that utilize exposure imaging equipment that step 6 is finished photoresistance glued membrane lining operation, to expose the two-sided etching operation of metal substrate that the localized metallic substrate carries out in order to follow-up needs.
Referring to Fig. 1 (H), after the exposure/development and windowing task of completing steps seven, the i.e. etching operation of carrying out each figure at the front and the back side of metal substrate, etch the front and back of pin 2, simultaneously the pin front is extended to as much as possible the below, zone of follow-up pasting chip, and make the positive size of the back side size of described pin 2, form up big and down small pin 2 structures less than pin 2; And form pillar 10 at pin 2 back sides, and between pin 2 and pin 2 company's of leaving muscle 16.
Photoresistance glued membrane striping is carried out at step 9, metal substrate front and the back side
Referring to Fig. 1 (I), the photoresistance glued membrane of metal substrate front and back remainder is all removed, make lead frame,
Referring to Fig. 1 (J), mounting of chip 7 carried out by non-conductive bonding material 6 in pin 2 fronts below the zone of described follow-up pasting chip.
Step 11, break metal wire
Referring to Fig. 1 (K), the semi-finished product of finishing the chip attachment operation are carried out playing metal wire 8 operations between chip front side and the pin front the first metal layer.
Referring to Fig. 1 (L), the semi-finished product front that routing is finished is encapsulated with filler plastic packaging material (epoxy resin) 9 operations, and carry out curing operation after plastic packaging material is sealed, make the top of pin and chip and metal wire all be had filler plastic packaging material (epoxy resin) to seal outward.
Referring to Fig. 1 (M), utilize by coating equipment to be covered respectively and can to carry out the photoresistance glued membrane 17 and 18 of exposure imaging will finishing the half-finished front that is encapsulated with filler plastic packaging material (epoxy resin) operation and the back side, to protect follow-up etch process operation.And this photoresistance glued membrane can be a dry type photoresistance pellicle also can be wet type photoresistance glued membrane.
Referring to Fig. 1 (N), exposure imaging removal part photoresistance glued membrane is carried out at the semi-finished product back side that is encapsulated with filler plastic packaging material (epoxy resin) operation of finishing that utilizes exposure imaging equipment that step 13 is finished photoresistance glued membrane lining operation, to expose company's muscle 16 that leaves after the two-sided etching operation of step 8 metal substrate and the pillar 10 that forms at pin 2 back sides, carry out the pillar root and connect muscle etching operation in order to follow-up needs.
Referring to Fig. 1 (O), after the exposure/development and windowing task of completing steps 14, promptly carry out the etching operation of each figure finishing the semi-finished product back side that is encapsulated with filler plastic packaging material (epoxy resin) operation, the company's muscle 16 that leaves after the two-sided etching operation of step 8 metal substrate is all etched away, root at pillar 10 described in this process also can etch away relative thickness simultaneously, make the pillar root not expose the encapsulating structure back side after sealing, avoid producing and open circuit.
Photoresistance glued membrane striping is carried out at step 10 six, semi-finished product front and the back side
Referring to Fig. 1 (P), the photoresistance glued membrane of the semi-finished product back side remainder of completing steps 15 etching operations and the photoresistance glued membrane in semi-finished product front are all removed.
Referring to Fig. 1 (Q), packless plastic packaging material (epoxy resin) operation is sealed at the semi-finished product back side of completing steps 16 described striping operations, and carry out curing operation after plastic packaging material is sealed, make the zone of pin 2 peripheries and the zone between pin 2 and the pin 2 all set packless plastic packaging material (epoxy resin) 3, this packless plastic packaging material (epoxy resin) 3 links into an integrated entity periphery, pin bottom and pin 2 bottoms and pin 2 bottoms, and described pillar 10 roots are imbedded in this packless plastic packaging material (epoxy resin) 3.
Specify: but also because many described pillars 10 in packaging body, the structure in packaging body is more strong on the contrary (can be compared to mix increased reinforcing bar in the earth intensity but also flexible are arranged not only).
The back side of step 10 eight, pin is carried out metal level and is electroplated lining
Referring to Fig. 1 (R), the back side that completing steps 17 is sealed the described pin of no filler plastic packaging material operation is carried out second metal level 5 and is electroplated the lining operations, and the material of electroplating can be tin, nickel gold, NiPdAu .... wait metal material.
Referring to Fig. 2 and Fig. 3, the semi-finished product of ten eight the second metal levels of completing steps being electroplated lining carry out cutting operation, make script independent, make two-sided graphic chips and directly put the module package structure finished product with more than of the chips that array formula aggregate mode connects together.
Described pin 2 can be provided with individual pen, shown in Fig. 1～3, also can be provided with multi-turn.
Claims (1)
1. a two-sided graphic chips is directly put module package structure, comprise pin (2), packless plastic packaging material (3), non-conductive bonding material (6), chip (7), metal wire (8) and filler plastic packaging material (9) is arranged, the positive below, zone that extends to follow-up pasting chip as much as possible of described pin (2), be provided with the first metal layer (4) in the front of described pin (2), be provided with second metal level (5) at the back side of described pin (2), pin below the zone of described follow-up pasting chip (2) is positive to be provided with chip (7) by non-conductive bonding material (6), chip (7) positive with pin (2) front the first metal layer (4) between be connected with metal wire (8), outside the top of described pin (2) and chip (7) and metal wire (8), be encapsulated with filler plastic packaging material (9), be equipped with packless plastic packaging material (3) in the zone of described pin (2) periphery and the zone between pin (2) and the pin (2), described packless plastic packaging material (3) links into an integrated entity pin (2) periphery, bottom and pin (2) bottom and pin (2) bottom, and make described pin (2) back side size less than the positive size of pin (2), form up big and down small pin configuration, it is characterized in that: be provided with pillar (10) at described pin (1) back side, pillar (10) root is imbedded in the described packless plastic packaging material (3).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201020517878XU CN201838579U (en) | 2010-09-04 | 2010-09-04 | Module packaging structure for direct arranging of chip with double-sided graphics |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201020517878XU CN201838579U (en) | 2010-09-04 | 2010-09-04 | Module packaging structure for direct arranging of chip with double-sided graphics |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201838579U true CN201838579U (en) | 2011-05-18 |
Family
ID=44008682
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201020517878XU Expired - Lifetime CN201838579U (en) | 2010-09-04 | 2010-09-04 | Module packaging structure for direct arranging of chip with double-sided graphics |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN201838579U (en) |
-
2010
- 2010-09-04 CN CN201020517878XU patent/CN201838579U/en not_active Expired - Lifetime
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