CN201838581U - Encapsulation structure without pin around - Google Patents

Encapsulation structure without pin around Download PDF

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Publication number
CN201838581U
CN201838581U CN2010205556637U CN201020555663U CN201838581U CN 201838581 U CN201838581 U CN 201838581U CN 2010205556637 U CN2010205556637 U CN 2010205556637U CN 201020555663 U CN201020555663 U CN 201020555663U CN 201838581 U CN201838581 U CN 201838581U
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China
Prior art keywords
pin
metal
chip
plastic
dao
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Expired - Lifetime
Application number
CN2010205556637U
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Chinese (zh)
Inventor
王新潮
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JCET Group Co Ltd
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Jiangsu Changjiang Electronics Technology Co Ltd
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Priority to CN2010205556637U priority Critical patent/CN201838581U/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The utility model relates to an encapsulation structure without a pin around, comprising a base island (1), a pin (2), a chip (5), a metal wire (6) and a plastic encapsulation body (7), wherein the front surfaces and the back surfaces of the base island (1) and the pin (2) are respectively provided with a first metal layer (3) and a second metal layer (9); the front surface of the base island (1) is provided with the chip (5) through a conductive or non-conductive adhesive material (4); the front surface of the chip (5) and the first metal layer (3) at the front surface of the pin (2) are connected by the metal wire (6); the base island (1), the pin (2), the chip (5) and the metal wire (6) are externally encapsulated by the plastic encapsulation body (7); and the back surfaces of the base island (1) and the pin (2) are exposed outside the plastic encapsulation body (7). The encapsulation structure is characterized in that the second metal layers (9) at the back surfaces of the base island (1) and the pin (2) exposed outside the plastic encapsulation body (7) are provided with tin balls (10). The adoption of the encapsulation structure can avoid the problems that the pin falls off and the tin is difficult to melt when the plastic encapsulation body is attached to the surface of a PCB (printed circuit board) in an SMT (surface mounting technology).

Description

The four sides non-leaded package
(1) technical field
The utility model relates to the four sides non-leaded package of a kind of integrated circuit or discrete device.Belong to the semiconductor packaging field.
(2) background technology
The production method of traditional chip-packaging structure is: after chemical etching and surface electrical coating are carried out in the front of employing metal substrate, promptly finish the making of lead frame.Etching is then carried out at the back side of lead frame again in encapsulation process.This method has the following disadvantages: because only carried out the work that etches partially in the metal substrate front before the plastic packaging, and plastic-sealed body only wraps the height of half pin of pin in the plastic packaging process, so the constraint ability of plastic-sealed body and pin has just diminished, when if the plastic-sealed body paster is not fine to pcb board, do over again again and heavily paste, with regard to the problem (as shown in figure 22) that is easy to generate pin.Especially the kind of plastic-sealed body is to adopt when filler is arranged, because material is at the environment and the follow-up surface-pasted stress changing relation of production process, can cause metal and plastic-sealed body to produce the crack of vertical-type, its characteristic is the high more then hard more crisp more crack that is easy to generate more of proportion of filler.
In addition, when the plastic-sealed body paster is to pcb board, because of the spacing between the plastic-sealed body back side and the pcb board less, space between the plastic-sealed body back side and the pcb board is less, the inner ring pin of plastic-sealed body or Ji Dao can cause tin fusion difficulty because of hot blast rate is not enough, especially more pin or the difficult more hot blast that absorbs immediately of Ji Dao arranged of center, as shown in figure 23.
Moreover, if when the plastic-sealed body paster is not fine to pcb board, does over again again and heavily paste, because the tin cream place does not have enough height, cleaning agent is not easy cleaning, as Figure 23.
(3) summary of the invention
First purpose of the present utility model is to overcome above-mentioned deficiency, and a kind of four sides non-leaded package of not having the problem of tin fusion difficulty when the plastic-sealed body paster is to pcb board again is provided.
Second purpose of the present utility model is to overcome above-mentioned deficiency, and a kind of four sides non-leaded package of not having the problem that produces pin again is provided.
First purpose of the present utility model is achieved in that a kind of four sides non-leaded package, comprise Ji Dao, pin, chip, metal wire and plastic-sealed body, the front and back of Ji Dao and pin is respectively arranged with the first metal layer and second metal level, front, base island is provided with chip by conduction or non-conductive bonding material, be connected with metal wire between chip front side and the pin front the first metal layer, at described Ji Dao, pin, chip and metal wire are encapsulated with plastic-sealed body outward, and expose outside the described plastic-sealed body at the back side that makes Ji Dao and pin, and second metal level that exposes the back side of outer Ji Dao of described plastic-sealed body and pin is provided with the tin ball.
Second purpose of the present utility model is achieved in that described plastic-sealed body includes filler plastic packaging material epoxy resin and two kinds of no filler plastic packaging material epoxy resin, have the filler plastic packaging material epoxy resin enclosed outside the top and chip and metal wire of described Ji Dao and pin, no filler plastic packaging material epoxy resin links into an integrated entity periphery, pin bottom, Ji Dao and pin bottom and pin and pin bottom.
The beneficial effects of the utility model are:
1, because no filler plastic packaging material epoxy resin is set in the zone between the back side of described metal substrate pin and pin, this no filler plastic packaging material epoxy resin wraps the height of whole pin with the filler plastic packaging material epoxy resin that has of the routine in the metal substrate front in the plastic packaging process, so the constraint ability of plastic-sealed body and pin just becomes big, do not have the problem that produces pin again, as Figure 15.
2, when the plastic-sealed body paster is to pcb board, because of implanting or be coated with the tin ball at plastic-sealed body pin and Ji Dao position, it is big that spacing between the plastic-sealed body back side and the pcb board becomes, especially the inner ring pin of plastic-sealed body or zone, basic island can be because of hot blast can blow the problem that causes tin fusion difficulty, as the comparative descriptions of Figure 24 and Figure 23.
When if 3 plastic-sealed body pasters are not fine to pcb board, do over again again and heavily paste, because there are enough height at the tin cream place, as Figure 24, cleaning agent cleans easily.The maintenance easily behind the tin ball of burn-oning does not weld as the tin ball and to weld a ball again again after taking away the tin ball.
(4) description of drawings
Fig. 1～20 do not have each operation schematic diagram of pin package method on four sides for the utility model.
Figure 21 is the utility model four sides non-leaded package schematic diagram.
Figure 22 pin figure for what formed in the past.
Figure 23 is the tin fusion difficulty figure that in the past forms.
Figure 24 schemes easily for the tin fusion that the utility model forms.
Reference numeral among the figure:
The base island 1, pin 2, the first metal layer 3, conduction or non-conductive bonding material 4, chip 5, metal wire 6, plastic-sealed body 7, filler plastic packaging material epoxy resin 7-1, no filler plastic packaging material epoxy resin 7-2, second metal level 9, tin ball 10, metal substrate 11, photoresist film 12 and 13, photoresist film 14 and 15, half-etched regions 16, photoresist film 17, metal otter board 18, tin glue 19, pcb board 20, hot blast 21 are arranged.
(5) embodiment
The encapsulating structure of the utility model four sides non-leaded package, its method for packing comprises following processing step:
Step 1, get metal substrate
Referring to Fig. 1, get the suitable metal substrate of a slice thickness 11.The material of metal substrate can be carried out conversion according to the function and the characteristic of chip, for example: copper, aluminium, iron, copper alloy or dilval etc.
Step 2, pad pasting operation
Referring to Fig. 2, utilize film sticking equipment to stick the photoresist film 12 and 13 that can carry out exposure imaging respectively, to protect follow-up etch process operation at the front and the back side of metal substrate.And this photoresistance glued membrane can be a dry type photoresistance pellicle also can be wet type photoresistance glued membrane.
Step 3, the positive part photoresist film of removing of metal substrate
Referring to Fig. 3, the metal substrate front that utilizes exposure imaging equipment that step 2 is finished the pad pasting operation is carried out exposure imaging and is removed the part photoresist film, carries out the zone of Ji Dao and pin front metal cladding to expose follow-up needs on the metal substrate.
Step 4, metal substrate front metal cladding
Referring to Fig. 4, the zone of the metal cladding that exposes in step 3 plates the first metal layer 3, can be tightr, firm between metal wire and chip region and the routing Nei Jiao district during in order to follow-up bonding wire engage is increased in simultaneously and impels the conjugation that has between filler plastic packaging material epoxy resin in the encapsulating process.And the one-tenth branch of metal level can be to adopt golden nickel gold, golden ambrose alloy nickel gold, NiPdAu, golden NiPdAu, nickel gold, silver or tin etc. because of different chip materials.
Film operation and pad pasting operation are again taken off in step 5, the positive back side of metal substrate
Referring to Fig. 5, the positive remaining photoresist film of metal substrate and the photoresist film at the metal substrate back side are removed, and then sticked the photoresist film 14 and 15 that exposure imaging is used separately at the front and back of metal substrate.And this photoresistance glued membrane can be a dry type photoresistance pellicle also can be wet type photoresistance glued membrane.
Step 6, the positive part photoresist film of removing of metal substrate
Referring to Fig. 6, exposure imaging removal part photoresist film is carried out in the metal substrate front that utilizes exposure imaging equipment that step 5 is finished the pad pasting operation, to expose the zone that follow-up needs etch partially on the metal substrate.
Step 7, metal substrate front etch partially
Referring to Fig. 7, the positive zone of removing the part photoresist film of metal substrate in the step 6 is etched partially, in the positive half-etched regions 16 that forms depression of metal substrate, form basic island 1 and pin 2 simultaneously relatively, its purpose mainly is to avoid occurring in subsequent job the glue that overflows.
The film operation is taken off at step 8, the positive back side of metal substrate
Referring to Fig. 8, the positive remaining photoresist film of metal substrate and the photoresist film at the metal substrate back side are removed, make lead frame.
Step 9, load routing
Referring to Fig. 9, on the front, basic island of metal substrate the first metal layer 3, carry out the implantation of chip 5, and between chip 5 fronts and pin 2 front the first metal layers 3, play metal wire 6 operations by conduction or non-conductive bonding material 4.
Step 10, seal
Referring to Figure 10, utilize the plastic packaging material injection device, implant and beat the metal substrate of metal wire operation and be encapsulated with filler plastic packaging material epoxy resin 7-1 operation finishing chip, and the epoxy resin enclosed curing operation afterwards of filler plastic packaging material is arranged.
Step 11, the pad pasting operation of the metal substrate back side
Referring to Figure 11, stick the photoresist film 17 that exposure imaging is used finishing the filler plastic packaging material metal substrate back side epoxy resin enclosed and curing operation.
The part photoresist film is removed at step 12, the metal substrate back side
Referring to Figure 12, utilize exposure and visualization way, remove the photoresist film at the half-etched regions back side of the described metal substrate of step 7, purpose is to expose the follow-up needs in the metal substrate back side to carry out etched zone.
Step 13, the metal substrate back side etch partially
Referring to Figure 13, is that the metal of the described half-etched regions remaining part of step 7 carries out etching once more at the back side of metal substrate to the zone that is not covered by photoresist film, the metal of the described half-etched regions remaining part of step 7 is all etched away, thereby make the back side of Ji Dao and pin protrude from the described filler plastic packaging material epoxy resin that has.
The film operation is taken off at step 14, the metal substrate back side
Referring to Figure 14, utilize exposure and visualization way, remove the photoresist film of metal substrate back side remainder.
Step 15, there is the back side full-filling of filler plastic packaging material epoxy resin not have filler plastic packaging material epoxy resin
Referring to Figure 15, no filler plastic packaging material epoxy resin 7-2 in the regional full-filling of the etched metal at the described metal substrate of the step 13 back side, and do not have the epoxy resin enclosed back of filler plastic packaging material curing operation,
Step 10 six, metal substrate back side metal cladding
Referring to Figure 16, second metal level 9 that plates at the metal substrate back side.The one-tenth branch of metal level can be to adopt golden nickel gold, golden ambrose alloy nickel gold, NiPdAu, golden NiPdAu, nickel gold, silver or tin etc. because of different chip materials.
Step 10 seven, cover metal otter board
Referring to Figure 17, cover a metal otter board 18 at the metal substrate back side, so that the operation of follow-up brush tin glue.
Step 10 eight, fill out tin glue
Referring to Figure 18, the place inserts tin glue at the metal otter board mesh.
Step 10 nine, removal metal otter board
Referring to Figure 19, remove the metal otter board that step 10 seven covers.
Step 2 ten, formation tin ball
Referring to Figure 20, the tin glue that step 10 eight is inserted carries out Reflow Soldering, forms tin ball 10 on second metal level at the Ji Dao and the pin back side.
Step 2 11, cutting finished product
Referring to Figure 21, the semi-finished product that completing steps 20 is formed the tin balls carry out cutting operation, make originally more than of chips that connect together in array formula aggregate mode independent, make four sides non-leaded package finished product.
Described pin 2 can be provided with individual pen, also can be provided with multi-turn.
The utility model can also make step 10 seven, step 10 eight, step 10 nine and step 2 ten into: the direct implantation tin ball at the Ji Dao and the pin back side.
End product is referring to Figure 21:
Figure 21 is the utility model four sides non-leaded package schematic diagram.Among Figure 21, base island 1, pin 2, the first metal layer 3, conduction or non-conductive bonding material 4, chip 5, metal wire 6, plastic-sealed body 7, filler plastic packaging material epoxy resin 7-1 is arranged, no filler plastic packaging material epoxy resin 7-2, second metal level 9 and tin ball 10, as seen from Figure 21, the utility model four sides non-leaded package, comprise basic island 1, pin 2, chip 5, metal wire 6 and plastic-sealed body 7, the front and back of base island 1 and pin 2 is respectively arranged with the first metal layer 3 and second metal level 9,1 front, base island is provided with chip 5 by conduction or non-conductive bonding material 4, chip 5 positive with pin 2 front the first metal layers 3 between be connected with metal wire 6, on described basic island 1, pin 2, chip 5 and the metal wire 6 outer plastic-sealed bodies 7 that are encapsulated with, and expose outside the described plastic-sealed body 7 at the back side that makes basic island 1 and pin 2, and second metal level 9 that exposes the back side of outer basic island 1 of described plastic-sealed body 7 and pin 2 is provided with tin ball 10.
Described plastic-sealed body 7 includes filler plastic packaging material epoxy resin 7-1 and two kinds of no filler plastic packaging material epoxy resin 7-2, have filler plastic packaging material epoxy resin 7-1 to be encapsulated in outside the top and chip 5 and metal wire 6 of described basic island 1 and pin 2, no filler plastic packaging material epoxy resin 7-2 links into an integrated entity with pin 2 bottoms and pin 2 periphery, pin 2 bottom, basic island 1 with pin 2 bottoms.

Claims (2)

  1. One kind the four sides non-leaded package, comprise Ji Dao (1), pin (2), chip (5), metal wire (6) and plastic-sealed body (7), the front and back of Ji Dao (1) and pin (2) is respectively arranged with the first metal layer (3) and second metal level (9), Ji Dao (1) is positive to be provided with chip (5) by conduction or non-conductive bonding material (4), chip (5) positive with pin (2) front the first metal layer (3) between be connected with metal wire (6), in described Ji Dao (1), pin (2), the outer plastic-sealed body (7) that is encapsulated with of chip (5) and metal wire (6), and the back side of Ji Dao (1) and pin (2) is exposed outside the described plastic-sealed body (7), it is characterized in that: second metal level (9) that exposes the back side of outer Ji Dao (1) of described plastic-sealed body (7) and pin (2) is provided with tin ball (10).
  2. 2. a kind of four sides according to claim 1 non-leaded package, it is characterized in that: described plastic-sealed body (7) includes two kinds of filler plastic packaging material epoxy resin (7-1) and no filler plastic packaging material epoxy resin (7-2), have filler plastic packaging material epoxy resin (7-1) to be encapsulated in outside the top and chip (5) and metal wire (6) of described Ji Dao (1) and pin (2), no filler plastic packaging material epoxy resin (7-2) links into an integrated entity with pin (2) bottom and pin (2) pin (2) periphery, bottom, Ji Dao (1) with pin (2) bottom.
CN2010205556637U 2010-09-30 2010-09-30 Encapsulation structure without pin around Expired - Lifetime CN201838581U (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102005432A (en) * 2010-09-30 2011-04-06 江苏长电科技股份有限公司 Packaging structure with four pin-less sides and packaging method thereof
CN102856288A (en) * 2012-05-09 2013-01-02 江苏长电科技股份有限公司 First etched and then packaged packaging structure with multiple chips normally installed and base islands buried as well as preparation method thereof
WO2013078750A1 (en) * 2011-11-30 2013-06-06 Jiangsu Changjiang Electronics Technology Co. Ltd First-plating-then-etching quad flat no-lead (qfn) packaging structures and method for manufacturing the same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102005432A (en) * 2010-09-30 2011-04-06 江苏长电科技股份有限公司 Packaging structure with four pin-less sides and packaging method thereof
WO2013078750A1 (en) * 2011-11-30 2013-06-06 Jiangsu Changjiang Electronics Technology Co. Ltd First-plating-then-etching quad flat no-lead (qfn) packaging structures and method for manufacturing the same
CN102856288A (en) * 2012-05-09 2013-01-02 江苏长电科技股份有限公司 First etched and then packaged packaging structure with multiple chips normally installed and base islands buried as well as preparation method thereof
CN102856288B (en) * 2012-05-09 2015-02-11 江苏长电科技股份有限公司 First etched and then packaged packaging structure with multiple chips normally installed and base islands buried as well as preparation method thereof

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