CN203573966U - Four-surface flat no-pin packaging part with solder ball surface array - Google Patents
Four-surface flat no-pin packaging part with solder ball surface array Download PDFInfo
- Publication number
- CN203573966U CN203573966U CN201320659559.6U CN201320659559U CN203573966U CN 203573966 U CN203573966 U CN 203573966U CN 201320659559 U CN201320659559 U CN 201320659559U CN 203573966 U CN203573966 U CN 203573966U
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- pin
- groove
- chip
- bare copper
- packaging part
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Lead Frames For Integrated Circuits (AREA)
Abstract
The utility model provides a four-surface flat no-pin packaging part with a solder ball surface array, which comprises a bare copper frame that is provided with a plurality of grooves parallelly. First pins are arranged outside the grooves at two ends. The bottom of each groove is provided with a second pin. The second pins at two ends are connected with the first pins which are adjacent to the second pins. A connecting layer is arranged below each of the rest second pins. A connecting layer which is connected with the first pin is also arranged below each first pin. Each connecting layer and a connector are respectively provided with a solder ball. Each gap between the connector and the connecting layer and each gap between two adjacent connecting layers are respectively filled by passivating member. An IC chip is reversely arranged on the front surface of the bare copper frame. Chip bumps are arranged in the grooves. The bottom end of the chip is connected with the bottom of the groove. Lower filler is filled between each chip bump and a corresponding groove. A plastic sealing member is packaged at the front surface of the bare copper frame. The packaging part can replace a CPS manufactured from a substrate and realizes flexible application of the IC chip on CSP packaging of a lead frame; thereby reducing frame thickness and satisfying requirement of thin-type packaging.
Description
Technical field
The utility model belongs to electronic information Element of automatic control technical field, relates to a kind of AAQFN packaging part, is specifically related to a kind of tape welding spherical array flat-four-side without pin (AAQFN) packaging part.
Background technology
For a long time, be subject to the restriction of etching template and etch process technology, conventional QFN product is continuing individual pen (1 circle) the lead frame pattern of the exploitation nineties in 20th century always.Owing to being limited in individual pen encapsulation, therefore pins of products is few, and I/O is few, can not meet the demand of high density, many I/O encapsulation.Nearly 2 years domestic has started to research and develop multi-turn QFN, but because framework manufacturing process difficulty is larger, only has indivedual international vendors can design, produce, and be subject to the restriction of associated companies patent, and pin is less relatively, and the R&D cycle is long.Therefore, although compare, adopt the BGA encapsulation of substrate production soldered ball as output, lead frame multi-turn QFN packaging efficiency is high, and cost is relatively low, use encapsulation flexibly, but multi-turn QFN is limited to lead frame manufacturer, can not meet the requirement of the flexible Application of short, flat, fast and different chips.
Utility model content
The purpose of this utility model is to provide a kind of tape welding spherical array flat-four-side pin-less packaging part, breaks away from the restriction of lead frame manufacturer, produces and meets the packaging part that short, flat, fast and different chip flexible Application require.
For achieving the above object, the technical scheme that the utility model adopts is: a kind of tape welding spherical array flat-four-side pin-less packaging part, comprise bare copper frame, bare copper frame front is provided with multiple grooves side by side, the outside of the groove in two ends is the first pin, each bottom portion of groove is the second pin, the second all pins is not connected mutually, the second pin that is positioned at two ends in all the second pins is connected with first pin adjacent with this second pin by connector, below remaining second pin, be equipped with the articulamentum being connected with this second pin, below the first pin, be also provided with an articulamentum being connected with this first pin, on each articulamentum, be equipped with a soldered ball, each connector surface is also equipped with a soldered ball, all articulamentums are not connected mutually with connector, in the space between adjacent connector and articulamentum, are filled with passivation, in the gap between adjacent articulamentum, are filled with passivation, the positive upside-down mounting of bare copper frame has the IC chip with salient point, and chip bump is positioned at groove, and chip bump bottom is connected with bottom portion of groove, is filled with lower filler in the gap between chip bump and groove, and bare copper frame front plastic packaging has plastic-sealed body.
Between adjacent notches, be pin partition wall, pin partition wall is not connected with the second pin.
The utility model packaging part can substitute the CPS of substrate production, realizes IC chip flexible Application in the CSP of lead frame encapsulation; Its production cost and construction cycle, far below substrate package, there is larger advantage.Break away from the restriction of lead frame manufacturer, produce the packaging part that short, flat, fast and different chip flexible Application require, reduce the thickness of framework, meet thin encapsulation requirement.
Accompanying drawing explanation
Fig. 1 is the generalized section that applies photoresist in the utility model packaging part on bare copper frame.
Fig. 2 is the generalized section that in the utility model packaging part, exposure imaging is made pattern post bake.
Fig. 3 is the generalized section that etches groove in the utility model packaging part on bare copper frame.
Fig. 4 is the generalized section that applies the first passivation layer in the utility model packaging part and carve UBM1 window on bare copper frame.
Fig. 5 be in the utility model packaging part in groove high-frequency sputtering multiple layer metal form the generalized section of UBM1 layer.
Fig. 6 is the large figure of P prescription in Fig. 5.
Fig. 7 is the generalized section of core and lower filling in upside-down mounting in the utility model packaging part.
Fig. 8 is plastic packaging and rear curing generalized section in the utility model packaging part.
Fig. 9 applies the generalized section after the second passivation layer etching in the utility model packaging part.
Figure 10 is that in the utility model packaging part, lead frame back-etching goes out the 3rd groove and removes the generalized section of the second passivation layer.
Figure 11 is the generalized section that applies the 3rd passivation layer etching the 4th groove in the utility model packaging part.
Figure 12 is the generalized section at the 3rd passivation layer surface metal cladding etching the 4th groove in the utility model packaging part.
Figure 13 is the generalized section that applies the 4th passivation layer etching the 5th groove in the utility model packaging part.
Figure 14 is the generalized section that in the utility model packaging part, sputter multiple layer metal in bottom forms UBM2 layer;
Figure 15 plants the generalized section after ball, Reflow Soldering in the utility model packaging part.
In figure: 1. bare copper frame, 2. descends filler, 3.IC chip, 4. chip bump, 5. pin partition wall, 6. plastic-sealed body, 7. passivation, 8. tin ball, 9. articulamentum, 10. scolder, 11. first pins, 12. second pins, 13. photoresist layers, 14. first grooves, 15. second grooves, 16. first passivation layers, 17.UBM
1window, 18.UBM
1layer, 18. second passivation layers, 20. first pattern grooves, 21. the 3rd grooves, 22. the 3rd passivation layers, 23. second pattern grooves, 24. the first metal layers, 25. the 4th grooves, 26. the 4th passivation layers, 27. the 5th grooves, 28.UBM
2layer, a.Cu metal level, b.Ni metal level, c.Au metal level.
Embodiment
Below in conjunction with the drawings and specific embodiments, the utility model is elaborated.
As shown in Figure 1, the utility model packaging part, comprise bare copper frame 1, bare copper frame 1 front is provided with multiple grooves side by side, it between adjacent notches, is pin partition wall 5, the outside of the groove in two ends is the first pin 11, the bottom of each groove is the second pin 12, the second all pins 12 is not connected mutually, pin partition wall 5 is not connected with the second pin 12, the second pin 12 that is positioned at two ends in all the second pins 12 is connected with first pin 11 adjacent with this second pin 12 by connector, remaining second pin 12 is equipped with the articulamentum 9 being connected with this second pin below, below the first pin 11, be also provided with an articulamentum 9 being connected with this first pin 11, each articulamentum 9 surfaces are equipped with a soldered ball 8, each connector surface is also equipped with a soldered ball 8, all articulamentums 9 are not connected mutually with connector, in the space between adjacent connector and articulamentum 9, are filled with passivation 7, in the gap between adjacent articulamentum 9, are filled with passivation 7, the positive upside-down mounting of bare copper frame 1 has the IC chip 3 with salient point, chip bump 4 on IC chip 3 lays respectively in different grooves, chip bump 4 bottoms are connected with bottom portion of groove, in gap between chip bump 4 and groove, be filled with lower filler 2, bare copper frame 1 front plastic packaging has plastic-sealed body 6, and IC chip 3 and bare copper frame 1 front are positioned at plastic-sealed body 6.
The production method of the utility model packaging part:
Step 1: wafer reduction scribing, apply photoresist on bare copper frame
Use the attenuate machine of 8 inch～12 inch, adopt corase grind, the thin anti-warpage technique of fine-grinding and polishing, will with the wafer of salient point, be thinned to 200～250 μ m, corase grind speed 6 μ m/s, fine grinding speed 1.0 μ m/s; Adopt A-WD-300TXB scribing machine to carry out scribing, scribing feed velocity≤10mm/s; Form IC chip 3;
Adopt sol evenning machine or coating machine, in the front of bare copper frame 1, evenly apply the photoresist that a layer thickness is at least 10 μ m (positive negativity all can), form photoresist layer 13, as shown in Figure 2, then at the temperature of 60 ℃～70 ℃, toast 25 ± 5 minutes;
Step 2: exposure imaging post bake
On exposure machine, the bare copper frame 1 that applies photoresist is aimed to exposure, then development, photographic fixing, remove the photoresist of exposure area, make to form on photoresist layer 13 multiple the first grooves 14 side by side, the bare copper frame 1 of each the first groove 14 positions exposes, bare copper frame 1 region of exposing demonstrates pattern, post bake 30 ± 5 seconds at the temperature of 120 ℃ ± 5 ℃ afterwards, as shown in Figure 3;
Step 3: etching the second groove
Bare copper frame after post bake 1 is placed in to etching, cleans on all-in-one, make photoresist layer 13 upwards, spray corrosive liquid (acid or alkalescence) downwards, in bare copper frame 1 front-side etch of exposing, go out the figure of needs, at multiple the second grooves 15 side by side of bare copper frame 1 positive formation, between adjacent two second grooves 15, there is pin partition wall 5, then remove remaining photoresist layer 13, as shown in Figure 4;
Step 4: apply the first passivation layer and etching UBM
1window
Adopt coating machine, at the bare copper frame 1 that etches figure surface uniform surperficial and all the second grooves 15, apply the first passivation layer 16, then on the first passivation layer 16 of all the second groove 15 bottoms, etch UBM
1window 17, as Fig. 5;
Step 5: growth UBM
1layer
Adopt high-frequency sputtering method at all UBM
1in window 17 and the first passivation layer 16 surface high frequency sputter copper metal layer a on the second groove 15 surfaces, the two ends of copper metal layer a lay respectively on first passivation layer 16 on bare copper frame 1 surface, then at copper metal layer a surface high frequency sputter nickel metal layer b, then at nickel metal layer b surface high frequency sputter gold metal layer c; Copper metal layer a, nickel metal layer b and gold metal layer c composition UBM
1layer 18, UBM
1layer 18 is high-frequency sputtering Cu-Ni-Au layer; By photoetching, etching step, remove unnecessary metal level, make the UBM of adjacent two the second groove 15 interior formation
1layer 18 does not contact, and obtains semi-finished product lead frame, as shown in Figure 6 and Figure 7;
Step 6: core and lower filling in upside-down mounting
Get the IC chip 3 that step 1 makes, first on chip bump 4, be stained with scolder 10, adopt upside-down mounting chip feeder, by core in these IC chip 3 upside-down mountings on the semi-finished product lead frame of step 5, chip bump 4 is entered in the second groove 15 and with the UBM of the second groove 15 bottoms
1layer 18 is connected, and then with lower filler 2, fills space and chip bump 4 and the UBM between the interior chip bump 4 of the second groove 15
1the space of layer between 18, lower filler 2 plays insulating effect, makes to insulate between salient point on IC chip 3 and salient point, as Fig. 8;
Core and lower fill process in upside-down mounting: on special upside-down mounting chip feeder, first chip is overturn, be stained with after scolder, auto-alignment is placed into UBM(metalization under bump corresponding on the bare copper frame 1 of core in upside-down mounting, under salient point, metallize) position, on whole piece framework, after complete chip, income is transmitted box automatically, and in flip-chip, the semi-finished product lead frame after core transmits box and delivers to Reflow Soldering operation by the gross.Passing through DOE (Design of Experiment, EXPERIMENTAL DESIGN) test under definite thermal reflow profile, by UBM corresponding on tin salient point, scolder and lead frame on chip by Reflow Soldering hot melt, UBM on chip and lead frame is firmly welded together, directly substituted traditional upper core and bond technology;
By DOE (Design of Experiment, EXPERIMENTAL DESIGN) test, choose suitable lower inserts (less filler), lower filling mould has Incision Machine's.Under vacuum suction, lower inserts can be filled the space between chip bump and salient point fully completely, do not have cavity, prevent that soldered ball is shifted at high temperature.
Step 7: plastic packaging and rear solidifying
Use full-automatic sealing machine, adopt low stress (a
1≤ 1) the semi-finished product lead frame of the environment-friendly type plastic packaging material that meets the Weee of European Union, ROHS standard and SoNY standard of, low moisture absorption (water absorption rate <0.25%) after to core in step 6 upside-down mounting carries out plastic packaging, at the positive plastic-sealed body 6 that forms of bare copper frame 1, IC chip 3 and bare copper frame 1 front are all packaged in plastic-sealed body 6, as shown in Figure 9, then by general anti-absciss layer technique, carry out rear solidifying;
Step 8: the grinding bare copper frame back side
On equipment for grinding, to the semi-finished product lead frame back side after solidifying after plastic packaging, grinding is carried out at the back side of bare copper frame 1, and grinding thickness 0.03mm～0.035mm, then cleans, dries;
Step 9: apply the second passivation layer and etch the first pattern groove
Adopt and apply exposure all-in-one, bare copper frame 1 backside coating the second passivation layer 19 after grinding; Then on mask aligner, expose, development, photographic fixing, on the second passivation layer 19, etch again the first pattern groove 20, the correspondence position of each pin partition wall 5 on the second passivation layer 19 all has a first pattern groove 20, i.e. the first pattern groove 20 of pin partition wall 5 correspondences, be positioned at this pin partition wall 5 under, as shown in figure 10;
Step 10: framework etching
At the framework back side the second passivation layer 19, etch on the semi-finished product lead frame of the first pattern groove 20 and carry out again etching, remove the metal between the first corresponding pattern groove 20 of pin partition wall 5 and this pin partition wall 5, form the 3rd groove 21, as shown in figure 11, the 3rd groove 21 communicates with pin partition wall 5;
Step 11: apply the 3rd passivation layer etching the second pattern groove
On covering and answering a pager's call, not only cover the back side of semi-finished product lead frame to backside coating the 3rd passivation layer 22, the three passivation layers 22 of the semi-finished product lead frame of completing steps 10, fill up again this all groove in semi-finished product lead frame back side; Then the position that etches the second pattern groove 23, the second pattern groove 23 places on the 3rd passivation layer 22 is position, pin bottom surface and the place that needs copper cash framework 1 to expose, as shown in figure 12;
Step 12: splash-proofing sputtering metal layer
At the semi-finished product lead frame back spatter the first metal layer 24 of completing steps 11, the first metal layer 24 is positioned at the 3rd passivation layer 22 surfaces, and be full of all second graph grooves 23, then on the first metal layer 24, etch the 4th groove 25, as shown in figure 13, the first metal layer 24 is copper metal layer;
Step 13: apply the 4th passivation layer etching the 4th groove
At the 3rd passivation layer 22 surface-coated the 4th passivation layer 26, and make the 4th passivation layer 26 be full of the 4th all grooves 25, then on the 4th passivation layer 26, etching the 5th groove 27(is UBM
2window), as shown in figure 14;
Step 14: form UBM
2
At all interior equal sputter multiple layer metals of the 5th groove 27, this multiple layer metal is filled the 5th all grooves 27, forms UBM
2layer 28, as shown in figure 15;
Step 15: plant ball
By ball attachment machine, at the UBM at the semi-finished product lead frame back side of completing steps 14
2on layer 28, brush scolder, then tin ball 8 is placed on and is brushed on scolder, by Reflow Soldering, make tin ball 8 and UBM
2layer 28 strong bonded, clean;
Step 16: printing and the cutting and separating technique that adopts QFN to encapsulate prints, cutting and separating, but need protection tin ball 8 not damage; Adopt the test technology of BGA encapsulation to test the product separating, qualified product are the tape welding spherical array flat-four-side pin-less packaging part shown in Fig. 1.
The printing of wafer attenuate, scribing and the product of this encapsulation, cutting and separating, test adopt and encapsulate identical equipment and technique with BGA.
The photoetching in chip manufacturing (plate-making, gluing, development, post bake), etching in this packaging part, have been adopted.Front surface coated passivation layer, etching UBM
1window, high-frequency sputtering multiple layer metal form UBM
1layer.Use band salient point IC chip, adopt core and lower filling in the upside-down mounting in packaging technology, plastic packaging and rear curing process, complete the positive production of packaging part.The framework back side adopts grinding process, and attenuate frame thickness, meets Ultrathin packaging.Continue to adopt passivation and the etch process of chip production, by applying the second passivation layer 18, etching the first pattern groove 20, continue etching the first pattern groove 20, form the 3rd groove 21 communicating with pin partition wall 5, and remove the second passivation layer 18.Apply the 3rd passivation layer 22 and etch the second pattern groove 23, high-frequency sputtering metallic copper, forms the first metal layer 24, etches the 4th groove 25 on the first metal layer 24, applies the 4th passivation layer 26, etches the 5th groove 27(UBM
2window), high-frequency sputtering metal, at the interior formation of the 5th groove 27 UBM
2layer 28.Adopt the general printing of encapsulation, plant ball reflow soldering process, make tin ball 8 and UBM
2layer 28 strong bonded, make tape welding spherical array flat-four-side pin-less packaging part.The utility model packaging part can substitute the CPS of substrate production, realizes IC chip flexible Application in the CSP of lead frame encapsulation.
Although illustrated and described the utility model in conjunction with preferred embodiment, it will be understood by those skilled in the art that under the prerequisite of the spirit and scope of the present utility model that limit without prejudice to claims, can modify and convert.
Claims (2)
1. a tape welding spherical array flat-four-side pin-less packaging part, comprise bare copper frame (1), it is characterized in that, bare copper frame (1) front is provided with multiple grooves side by side, the outside of the groove in two ends is the first pin (11), each bottom portion of groove is the second pin (12), all the second pins (12) are not connected mutually, the second pin (12) that is positioned at two ends in all the second pins (12) is connected with first pin (11) adjacent with this second pin (12) by connector, remaining second pin (12) is equipped with the articulamentum (9) being connected with this second pin below, below the first pin (11), be also provided with an articulamentum (9) being connected with this first pin (11), on each articulamentum (9), be equipped with a soldered ball (8), each connector surface is also equipped with a soldered ball (8), all articulamentums (9) are not connected mutually with connector, are filled with passivation (7) in the space between adjacent connector and articulamentum (9), are filled with passivation (7) in the gap between adjacent articulamentum (9), the positive upside-down mounting of bare copper frame (1) has the IC chip (3) with salient point, chip bump (4) is positioned at groove, chip bump (4) bottom is connected with bottom portion of groove, in gap between chip bump (4) and groove, be filled with lower filler (2), bare copper frame (1) front plastic packaging has plastic-sealed body (6).
2. a kind of tape welding spherical array flat-four-side pin-less packaging part according to claim 1, is characterized in that, is pin partition wall (5) between adjacent notches, and pin partition wall (5) is not connected with the second pin (12).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320659559.6U CN203573966U (en) | 2013-10-24 | 2013-10-24 | Four-surface flat no-pin packaging part with solder ball surface array |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320659559.6U CN203573966U (en) | 2013-10-24 | 2013-10-24 | Four-surface flat no-pin packaging part with solder ball surface array |
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| Publication Number | Publication Date |
|---|---|
| CN203573966U true CN203573966U (en) | 2014-04-30 |
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|---|---|---|---|
| CN201320659559.6U Expired - Fee Related CN203573966U (en) | 2013-10-24 | 2013-10-24 | Four-surface flat no-pin packaging part with solder ball surface array |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108695266A (en) * | 2017-04-12 | 2018-10-23 | 力成科技股份有限公司 | Encapsulating structure and preparation method thereof |
| CN113380638A (en) * | 2021-05-21 | 2021-09-10 | 苏州通富超威半导体有限公司 | Method for setting through hole on packaging body and method for preparing packaging body |
| CN115513147A (en) * | 2022-11-24 | 2022-12-23 | 河北北芯半导体科技有限公司 | Flip chip packaging structure partially filled with underfill |
-
2013
- 2013-10-24 CN CN201320659559.6U patent/CN203573966U/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108695266A (en) * | 2017-04-12 | 2018-10-23 | 力成科技股份有限公司 | Encapsulating structure and preparation method thereof |
| CN113380638A (en) * | 2021-05-21 | 2021-09-10 | 苏州通富超威半导体有限公司 | Method for setting through hole on packaging body and method for preparing packaging body |
| CN115513147A (en) * | 2022-11-24 | 2022-12-23 | 河北北芯半导体科技有限公司 | Flip chip packaging structure partially filled with underfill |
| CN115513147B (en) * | 2022-11-24 | 2023-03-24 | 河北北芯半导体科技有限公司 | Flip chip packaging structure partially filled with underfill |
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| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20140430 Termination date: 20181024 |