CN103730443B - Tape welding spherical array four limit is without pin IC chip stacked packaging piece and production method - Google Patents
Tape welding spherical array four limit is without pin IC chip stacked packaging piece and production method Download PDFInfo
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- CN103730443B CN103730443B CN201310749972.6A CN201310749972A CN103730443B CN 103730443 B CN103730443 B CN 103730443B CN 201310749972 A CN201310749972 A CN 201310749972A CN 103730443 B CN103730443 B CN 103730443B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
- H01L2224/48147—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked with an intermediate bond, e.g. continuous wire daisy chain
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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Abstract
A kind of tape welding spherical array four limit is without pin IC chip stacked packaging piece and production method, including being provided with groove and the bare copper frame of multiple mounting groove, the chip of upside-down mounting band salient point, filling out lower filler between chip bump and mounting groove, groove both sides are respectively the first pin and the second pin being connected by passivation；There is articulamentum bottom pin and mounting groove, bottom all articulamentums, be provided with soldering ball sealing the first plastic-sealed body；Stacking gradually layers of chips on band bump chip, lower die is connected by bonding line and two pins；Upper die is connected with lower die and the first pin by bonding line.Wafer reduction scribing, etching pin groove and mounting groove, upper core, bonding wire, for the first time plastic packaging, the process bare copper frame back side, the coating operation such as passivation layer, high-frequency sputtering metal level, prepare stack package.The volume of this packaging part is less, and packaging density is higher, function is more, can be with Substitute For Partial BGA stacked package and CSP stacked package.
Description
Technical field
The invention belongs to electronic information Element of automatic control technical field, relate to a kind of IC chip stacked packaging piece, it is specifically related to a kind of tape welding spherical array flat-four-side without pin (Area Array Quad Flat No Lead Package, it is called for short AAQFN) IC chip stack package (Package In Package is called for short PiP) part；The invention still further relates to the production method of this packaging part a kind of.
Background technology
Although domestic having started to researched and developed multi-turn QFN in nearly 2 years, owing to frame manufacturing process difficulty is bigger, only indivedual international vendors can design, produce, but limited by associated companies patent, relatively pin is less, and the R&D cycle is long, and encapsulates multi-turn QFN and be limited to lead frame manufacturer, can not meet short, flat, fast, the requirement of the flexible Application of different chips.High density, the demand of many I/O encapsulation can not be met.
Summary of the invention
It is an object of the invention to provide a kind of tape welding spherical array flat-four-side without pin IC chip stacked packaging piece, be not only restricted to lead frame, meet high density, many I/O encapsulation and the requirement of different chip package.
It is a further object to provide the production method of a kind of above-mentioned IC chip stacked packaging piece.
For achieving the above object, the technical solution adopted in the present invention is: a kind of tape welding spherical array four limit is without pin IC chip stacked packaging piece, including bare copper frame, bare copper frame is provided with the first groove and multiple mounting groove, it is provided with partition wall between adjacent two mounting grooves, the upside-down mounting of bare copper frame front has the IC chip of band salient point, chip bump on this IC chip stretches in mounting groove, space between chip bump and mounting groove is filled with lower filler, bare copper frame front plastic packaging has the second plastic-sealed body, the first groove both sides to be respectively the first pin and the second pin；First bottom portion of groove is connected with passivation, and the first pin is connected with the second pin by passivation, is provided with the second articulamentum bottom the first pin；By being connected bottom the first articulamentum and the second pin bottom the mounting groove adjacent with the second pin, the first articulamentum it is equipped with bottom remaining mounting groove, all of first articulamentum and all of second articulamentum are all not attached to, bottom each first articulamentum and it is equipped with soldering ball bottom each second articulamentum, all passivation surfaces and all articulamentum surfaces plastic packaging have the first plastic-sealed body, all of soldering ball to be exposed independent from outside the first plastic-sealed body；IC chip with salient point has stacked gradually two-layer IC chip, and the IC chip being positioned at lower section is connected by the first bonding line and the second pin, is connected by fourth bond line and the first pin simultaneously；IC chip above is connected with the IC chip being positioned at lower section by the second bonding line, and IC chip above is connected by third bond line and the first pin.
Another technical scheme of the present invention is: a kind of above-mentioned tape welding spherical array four limit, without the production method of pin IC chip stacked packaging piece, specifically sequentially includes the following steps:
Step 1: wafer reduction scribing；
Step 2: uniformly coat photoresist in bare copper frame front, forms photoresist layer；Toast 25 ± 5 minutes at a temperature of 60 DEG C～70 DEG C；Be then aligned with exposure, development, fixing, photoresist layer forms multiple second groove and multiple 3rd groove, post bake 30 ± 5 minutes at a temperature of 120 DEG C ± 5 DEG C；Then going out the first groove in the bare copper frame front-side etch that the second groove is corresponding, the bare copper frame front-side etch that the 3rd groove is corresponding goes out the 4th groove, forms partition wall, remove photoresist layer between adjacent two the 4th grooves；
Step 3: the surface etching the first groove and the 4th groove at bare copper frame uniformly coats the first passivation layer, the first passivation layer covers the first groove surfaces and the 3rd groove surfaces simultaneously；Then on the first passivation layer of the 4th bottom portion of groove, UBM is etched1Window, etches framework pad openings on first passivation layer on the first bare copper frame surface, groove both sides；
Step 4: the many metal levels of high-frequency sputtering, forms UBM at the 4th groove inner surface1Layer；Framework pad openings is formed framework pad, removes excess metal layer so that the UBM in adjacent 4th groove1Layer is not attached to, framework pad openings and UBM1Layer is not attached to, the UBM in the 4th groove and the 4th groove1Layer constitutes mounting groove；UBM1The structure of layer is identical with the structure of framework pad, is constituted by three-layer metal layer or two metal layers, and when using three-layer metal layer, this three-layer metal layer is the first metal layer, the second metal level and the 3rd metal level set gradually；When using two metal layers, this two metal layers is the first metal layer set gradually and the 3rd metal level；The first metal layer is Cu layer, Ni layer or Cr layer, and the second metal level is Ni layer, Cr layer, and the 3rd metal level is Au layer；The first metal layer is connected with the first passivation layer and the 4th groove floor；
Step 5: by the IC flip-chip of band salient point, core is on bare copper frame, chip bump stretches in mounting groove；Then use the lower filling mould of band vac sorb that the space between chip bump and mounting groove is carried out lower filling, make chip bump be insulated by lower filler with framework；
Step 6: the IC chip back at band salient point stacks the 2nd IC chip, baking, then making a call to the first bonding line from the 2nd IC chip to the framework pad between the first groove and mounting groove, the pad from the 2nd IC chip plays fourth bond line to the framework pad being positioned at outside the first groove；
Step 7: stack the 3rd IC chip, baking on the 2nd IC chip, then make a call to the second bonding line from the 3rd IC chip to the 2nd IC chip, then on the framework pad being positioned at outside the first groove bare copper frame, play third bond line from the 3rd IC chip；
Step 8: employing meets European Union's Weee, ROHS standard and Sony standard environment-friendly type plastic packaging material carries out plastic packaging for the first time to bare copper frame front, form the second plastic-sealed body, second plastic-sealed body covers all IC chips and all of bonding line, second plastic-sealed body embeds in the first groove, solidifies after carrying out by general anti-absciss layer technique after plastic packaging；
Step 9: the grinding bare copper frame back side, cleans, dries；
Step 10: bare copper frame backside coating the second passivation layer after grinding, then exposes, develops, fixing, etches the 5th groove and the 6th groove on the second passivation layer, and the 5th groove is positioned at below the first groove, all has the 6th groove below each partition wall；
Step 11: along the 5th groove and the 6th recess etch bare copper frame, the bare copper frame that 5th groove is corresponding etches the 7th groove, the 7th groove and the first groove is made to communicate, the bare copper frame that 6th groove is corresponding etches the 8th groove, making the 8th groove below partition wall communicate with corresponding partition wall, the degree of depth of the 8th groove of remaining position is identical with the degree of depth of the 8th groove below partition wall, is pin between adjacent two grooves, remove the second passivation layer, expose pin bottom surface；
Step 12: at bare copper frame backside coating the 3rd passivation layer, 3rd passivation layer fills up all of 7th groove in the bare copper frame back side and all of 8th groove simultaneously, then etches the 9th groove on the 3rd passivation layer of relative the 3rd passivation layer of pin and the position of needs；
Step 13: at bare copper frame back side high-frequency sputtering copper metal layer, then etches the tenth groove on copper metal layer, and the tenth groove and the 3rd passivation layer communicate；
Step 14: at copper metal layer surface-coated the 4th passivation layer, the 4th passivation layer fills the tenth groove simultaneously, then etches UBM on the 4th passivation layer2Window, UBM2Window communicates with copper metal layer；
Step 15: at UBM2On window, high-frequency sputtering forms UBM2Layer, UBM2The structure of layer and UBM1The structure of layer is identical；
Step 16: by planting ball, Reflow Soldering at UBM2Weld soldering ball on layer, clean；
Step 17: carrying out second time plastic packaging in the 4th passivation layer surface, form the first plastic-sealed body, all of soldering ball is exposed independent from outside the second plastic-sealed body, then prints, cuts separation, test, prepare tape welding spherical array flat-four-side without pin IC chip stacked packaging piece.
IC chip stacked packaging piece of the present invention has disappeared the pin limitation of traditional multi-turn QFN peripheral leads structure, meets high density, the demand of many I/O encapsulation.Although many as the I/O of the BGA package of output less than using substrate production soldered ball, but compare the BGA package using substrate production soldered ball as output, the AAQFN packaging efficiency of lead-frame ribbon soldered ball is high, and cost is relatively low, uses flexibly.And in this foundational development face array QFN IC chip stack package (PiP), its small product size is less, packaging density is higher, function is more, can be with Substitute For Partial BGA stacked package and CSP stacked package, realize IC chip and be flexibly applied to the CSP encapsulation of lead frame, shortening cycle development period, its production cost and construction cycle, far below substrate package, have bigger advantage.
Accompanying drawing explanation
Fig. 1 is the structural representation of IC chip stacked packaging piece of the present invention.
Fig. 2 is the generalized section after coating photoresist and exposure imaging post bake in production method of the present invention on bare copper frame.
Fig. 3 is the generalized section after etching the first groove and the 4th groove in production method of the present invention on bare copper frame.
Fig. 4 is to coat the first passivation layer, etching UBM in production method of the present invention1Generalized section after window and framework pad openings.
Fig. 5 is that production method medium-high frequency of the present invention sputtering multiple layer metal forms UBM1Generalized section after layer and framework pad.
Fig. 6 is enlarged drawing at the P of Fig. 5.
Fig. 7 is generalized section after core and lower filling in upside-down mounting in production method of the present invention.
Fig. 8 is the generalized section after stacking the 2nd IC chip in production method of the present invention and being bonded for the first time.
Fig. 9 is the generalized section after stacking the 3rd IC chip and second time bonding in production method of the present invention.
Figure 10 is the generalized section in production method of the present invention after for the first time plastic packaging and rear solidification.
Figure 11 is the generalized section after coating the second passivation layer and etching the 5th groove and the 6th groove in production method of the present invention.
Figure 12 is the generalized section in production method of the present invention after bare copper frame back-etching goes out the 7th groove and the 8th groove.
Figure 13 is the generalized section after coating the 3rd passivation layer and etching the 9th groove in production method of the present invention.
Figure 14 is the generalized section after production method medium-high frequency of the present invention sputtering copper metal layer and etching the tenth groove.
Figure 15 is to coat the 4th passivation layer and etching UBM in production method of the present invention2Generalized section after window.
Figure 16 is to sputter multiple layer metal in production method of the present invention bottom pin to form UBM2Generalized section after Ceng.
Figure 17 is the generalized section after planting ball and Reflow Soldering in production method of the present invention.
In figure: 1. bare copper frame, 2. passivation, 3. the first articulamentum, 4. the first plastic-sealed body, 5. soldering ball, 6. solder, 7. chip bump, 8. partition wall, 9. an IC chip, 10. descend filler, 11. first grooves, 12. first bonding lines, 13. second bonding lines, 14. a DAF sheet, 15. the 2nd IC chip, 16. the 2nd DAF sheet, 17. the 3rd IC chip, 18. third bond lines, 19. fourth bond lines, 20. second plastic-sealed bodies, 21. framework pads, 22. second articulamentums, 23. first pins, 24. second pins, 25. photoresist layers, 26. second grooves, 27. the 3rd grooves, 28. the 4th grooves, 29. first passivation layers, 30.UBM1Window, 31. framework pad openings, 32.UBM1Layer, 33. second passivation layers, 34. the 5th grooves, 35. the 6th grooves, 36. the 7th grooves, 37. the 8th grooves, 39. the 3rd passivation layers, 40. the 9th grooves, 41. copper metal layers, 42. the tenth grooves, 43. the 4th passivation layers, 44.UBM2Window, 45.UBM2Layer.
A. the first metal layer, b. the second metal level, c. the 3rd metal level.
Detailed description of the invention
The present invention is described in detail with detailed description of the invention below in conjunction with the accompanying drawings.
As it is shown in figure 1, IC chip stacked packaging piece of the present invention, including bare copper frame 1, bare copper frame 1 is provided with the first groove 11 and multiple mounting groove, and the first groove 11 and multiple mounting groove are arranged side by side, the
One groove 11 both sides are respectively the first pin 23 and the second pin 24, and the second pin 24 is between the first groove 11 and the mounting groove adjacent with the first groove 11；Being connected with passivation 2 bottom first groove 11, the first pin 23 is connected with the second pin 24 by passivation 2, is provided with the second articulamentum 22 bottom the first pin 23；It is provided with partition wall 8 between adjacent two mounting grooves, it is connected bottom the second pin 24 by the first articulamentum 3 bottom the mounting groove adjacent with the second pin 24, the first articulamentum 3 it is equipped with bottom remaining mounting groove, all of first articulamentum 3 and all of second articulamentum 22 are all not attached to, bottom each first articulamentum 3 and it is equipped with soldering ball 5 bottom each second articulamentum 22, soldering ball 5 is connected with corresponding articulamentum by solder 6, all passivation 2 surfaces and all articulamentum surfaces plastic packaging have the first plastic-sealed body 4, all of soldering ball 5 is exposed independent from outside the first plastic-sealed body 4；Bare copper frame 1 front upside-down mounting has an IC chip 9, oneth IC chip 9 is the IC chip of band salient point, chip bump 7 on oneth IC chip 9 stretches in mounting groove, and is connected with bottom mounting groove by solder 6, and the space between chip bump 7 and mounting groove is filled with lower filler 10；Being stacked with the 2nd IC chip 15 on oneth IC chip 9, the 2nd IC chip 15 is bonding with an IC chip 9 by a DAF sheet 14, and the 2nd IC chip 15 is stacked with the 3rd IC chip 17, and the 3rd IC chip 17 is bonding with the 2nd IC chip 15 by DAF sheet 16；It is equipped with framework pad 21 on first pin 23 and the second pin 24；2nd IC chip 15 is connected with the framework pad 21 on the second pin 24 by the first bonding line 12, and the 2nd IC chip 15 is connected with the framework pad on the first pin 23 by fourth bond line 19；3rd IC chip 17 is connected with the 2nd IC chip 15 by the second bonding line 13, and the 3rd IC chip 17 is connected with the framework pad 21 on the first pin 23 by third bond line 18；Bare copper frame 1 front plastic packaging has the second plastic-sealed body 20；Bare copper frame 1 front, all of IC chip, all of bonding line and all of framework pad 21 are all packaged in the second plastic-sealed body 20, and the second plastic-sealed body 20 embeds in the first groove 11.
The technological process of production of IC chip stacked packaging piece of the present invention:
Reduction scribing → bare copper frame gluing, exposure imaging post bake, etch the first groove and the 4th groove → coat the first passivation layer and etch UBM1Window and framework pad openings → high-frequency sputtering multiple layer metal form UBM1On layer and framework pad → upside-down mounting core and lower filling → stacking the 2nd IC chip and for the first time the plastic packaging of bonding → stacking the 3rd IC chip and second time bonding → for the first time and the rear solidification → grinding framework back side → coat the second passivation layer etch on the 5th groove and six grooves → framework etching the 7th groove and the 8th groove and remove the second passivation layer → coating the 3rd passivation layer and etch nine grooves → high-frequency sputtering copper metal layer and etch the tenth groove → coating the 4th passivation layer and etch UBM2Window → bottom sputtering multiple layer metal forms UBM2The plastic packaging of layer → plant ball and Reflow Soldering → for the second time and after solidify.
The production method of a kind of above-mentioned IC chip stacked packaging piece that the present invention provides, specifically sequentially includes the following steps:
Step 1: use 8～12 thinning machines, uses corase grind, thin fine-grinding and polishing warpage preventing technique, and the wafer of band bump chip is thinned to 180 μm～200 μm, roughly grinds speed 6 μm/s, refines speed 1.0 μm/s；Use corase grind, thin fine-grinding and polishing warpage preventing technique, the wafer without bump chip is thinned to 50 μm～75 μm, roughly grind speed 2 μm/s, refine speed 6.0 μm/min；Employing prevents chip warpage technique；
Use A-WD-300TXB scribing machine that the wafer after thinning is carried out scribing, scribing feed velocity≤10mm/s；
Step 2: on sol evenning machine or coating machine, uniformly coats the photoresist (positive negativity) of a layer thickness >=10 μm in bare copper frame 1 front, forms photoresist layer 25；Toast 25 ± 5 minutes at a temperature of 60 DEG C～70 DEG C；Then on exposure machine, the bare copper frame 1 having been coated with photoresist layer 25 is carried out alignment exposure, development, fixing, photoresist layer 25 is formed multiple second groove 26 and multiple 3rd groove 27, as shown in Figure 2, pattern is demonstrated, post bake 30 ± 5 minutes at a temperature of 120 DEG C ± 5 DEG C on the bare copper frame 1 of the second groove 26 and the 3rd groove 27 correspondence；Then in etching, clean on all-in-one, by spray acid etching solution or alkaline corrosion liquid downwards, bare copper frame 1 front-side etch in the second groove 26 correspondence goes out the first groove 11 of the accompanying drawing shape needed, first groove 11 is pin groove, bare copper frame 1 front-side etch of the 3rd groove 27 correspondence goes out the 4th groove 28 of the accompanying drawing shape needed, partition wall 8 is formed, as it is shown on figure 3, remove photoresist layer 25 between adjacent two the 4th grooves 28；
Step 3: in coating machine, the surface etching the first groove 11 and the 4th groove 28 at bare copper frame 1 uniformly coats the first passivation layer 29, and the first passivation layer 29 covers the first groove 11 surface and the 4th groove 28 surface simultaneously；Then UBM is etched on the first passivation layer 29 bottom the 4th groove 281Window 30, etches framework pad openings 31, as shown in Figure 4 on first passivation layer 29 on the first bare copper frame 1 surface, groove 11 both sides；
Step 4: at the 4th groove 28 many metal levels of inner surface high-frequency sputtering, forms UBM1Layer 32；The many metal levels of high-frequency sputtering on framework pad openings 31, form framework pad 21, by photoetching, etching step, remove unnecessary metal level so that the UBM in adjacent 4th groove 281Layer 32 is not attached to, framework pad openings 31 and UBM1Layer 32 is not attached to, as it is shown in fig. 7, the 4th groove 28 and the UBM in the 4th groove 281Layer 32 constitutes mounting groove；UBM1The structure of layer 32 is identical with the structure of framework pad 21, is constituted by three-layer metal layer or two metal layers, and when using three-layer metal layer, this three-layer metal layer is the first metal layer a, the second metal level b and the 3rd metal level c set gradually；When using two metal layers, this two metal layers is the first metal layer a and the 3rd metal level c set gradually；The first metal layer a is Cu layer, Ni layer or Cr layer, and the second metal level b is Ni layer, Cr layer, and the 3rd metal level c is Au layer；The first metal layer a is connected, as shown in Figure 6 with the first passivation layer 29 and the 4th groove 28 bottom surface；
Step 5: use upside-down mounting chip feeder, the chip bump 7 of an IC chip 9 of band salient point is stained with solder 6, by core in IC chip 9 upside-down mounting on bare copper frame 1, making chip bump 7 stretch in mounting groove, chip bump 7 top is by solder 6 and the UBM in mounting groove1Layer 32 is connected；Then use the lower filling mould of band vac sorb that the space between chip bump 7 and mounting groove is carried out lower filling, make chip bump 7 be insulated, as shown in Figure 7 by lower filler 10 with framework；
Step 6: at the IC chip of band salient point, i.e. the oneth IC chip 9 back side stacks the 2nd IC chip 15 by a DAF sheet 14, baking, then the pad from the 2nd IC chip 15 makes a call to the first bonding line 12 to framework pad 21 between the first groove 11 and mounting groove, pad from the 2nd IC chip 15 is to 21 dozens of fourth bond lines 19 of the framework pad being positioned at outside the first groove 11, as shown in Figure 8；
Step 7: stack the 3rd IC chip 17 on the 2nd IC chip 15,3rd IC chip 17 is bonding with the 2nd IC chip 15 by the 2nd DAF sheet 16, baking, then the pad from the 3rd IC chip 17 makes a call to the second bonding line 13 to the pad of the 2nd IC chip 15, pad from the 3rd IC chip 17 plays third bond line 18, as shown in Figure 9 to being positioned on the framework pad 21 outside the first groove 11 on bare copper frame 1 again；
Step 8: use full-automatic sealing machine, uses low stress (a1≤ 1) meet European Union's Weee, ROHS standard and the Sony standard environment-friendly type plastic packaging material of, low moisture absorption (water absorption rate < 0.25%) carry out plastic packaging for the first time to bare copper frame 1 front, form the second plastic-sealed body 20, second plastic-sealed body 20 covers IC chip the 9, the 2nd IC chip the 15, the 3rd IC chip the 17, the oneth DAF sheet the 14, the 2nd DAF sheet 16 and an all of bonding line, second plastic-sealed body 20 embeds in the first groove 11, with bare copper frame 1 strong bonded, as shown in Figure 10；Solidify after carrying out by general anti-absciss layer technique after plastic packaging；
Step 9: on equipment for grinding, grinding bare copper frame 1 back side, the thickness that grinding is gone is the 1/3～1/4 of bare copper frame 1 thickness, cleans up, dries；
Step 10: use coating exposure all-in-one, bare copper frame 1 backside coating the second passivation layer 33 after grinding, then expose on litho machine, develop, fixing, second passivation layer 33 etches the 5th groove 34 and the 6th groove 35,5th groove 34 is positioned at the lower section of the first groove 11, all there is the 6th groove 35 lower section of each partition wall 8, as shown in figure 11；
Step 11: etch bare copper frame 1 along the 5th groove 34 and the 6th groove 35, the bare copper frame 1 of the 5th groove 34 correspondence etches the 7th groove 36, the 7th groove 36 is made to communicate with the first groove 11, the bare copper frame 1 of the 6th groove 35 correspondence etches the 8th groove 37, the 8th groove 37 below partition wall 8 is made to communicate with corresponding partition wall 8, the degree of depth of the 8th groove 37 of remaining position is identical with the degree of depth of the 8th groove 37 below partition wall 8, it is pin between adjacent two grooves, as shown in figure 12, remove the second passivation layer 33, expose pin bottom surface；
Step 12: on coating machine, at bare copper frame 1 backside coating the 3rd passivation layer 39,3rd passivation layer 39 should fill up all of 7th groove 36 in bare copper frame 1 back side and all of 8th groove 37, also to cover one layer at all pin back sides, then on relative the 3rd passivation layer 39 of pin and the 3rd passivation layer 39 of position that needs, the 9th groove 40 of accompanying drawing shape is etched, as shown in figure 13；
Step 13: at bare copper frame 1 back side high-frequency sputtering copper metal layer 41, then etches the tenth groove 42 on copper metal layer 41, and the tenth groove 42 communicates with the 3rd passivation layer 39, as shown in figure 14；
Step 14: at copper metal layer 41 surface-coated the 4th passivation layer 43, the 4th passivation layer 43 is filled the tenth groove 42 simultaneously, then etched UBM on the 4th passivation layer 432Window 44, UBM2Window 44 communicates with copper metal layer 41, as shown in figure 15；
Step 15: at UBM2High-frequency sputtering multiple layer metal on window 44, forms UBM2Layer 45, UBM2The structure of layer 45 and UBM1The structure of layer 32 is identical, sees Figure 16；
Step 16: by ball attachment machine, at UBM2Brush solder 6 on layer 45, then soldering ball 5 is placed on solder 6, makes soldering ball 5, solder 6 and UBM by Reflow Soldering2Layer 45 strong bonded, as shown in figure 17, are finally carried out；
Step 17: by automatic plastic-sealing machine and second time plastic package die, carrying out second time plastic packaging on the 4th passivation layer 43 surface, form the first plastic-sealed body 4, all of soldering ball 5 is exposed independent from outside the second plastic-sealed body 4, and the second plastic-sealed body 4 fixedly secures soldering ball 5；Then print, cut separation, test, prepare the tape welding spherical array flat-four-side shown in Fig. 1 without pin IC chip stacked packaging piece.Print, cutting uses the equipment with QFN same processes and technique when separating, and uses the equipment identical with BGA package and technique during test.
IC chip stacked packaging piece production method of the present invention have employed the photoetching (plate-making, gluing, development, post bake) in chip manufacturing, on bare copper frame 1 etched figure；Use coating passivation layer, etching UBM1Window 30, uses high-frequency sputtering multiple layer metal to form UBM1Layer 32 and framework pad 21, use an IC chip 9 of band salient point, uses core and lower filling in the upside-down mounting in packaging technology；Use DAF sheet to stack bonding 2nd IC chip 15 and pressure welding for the first time, use DAF sheet to stack bonding 3rd IC chip 17 and second time pressure welding, for the first time plastic packaging and rear curing process, complete packaging part front and produce.The framework back side uses grinding process, is thinned frame thickness.Continue to use passivation and the etch process of chip production process, by coating the second passivation layer 33, etching the 5th groove 34 and the 6th groove 35, continue etching the 5th groove 34 and the 6th groove 35 forms the first groove the 11, the 7th groove 36 and the 8th groove 37 on bare copper frame 1, and remove the second passivation layer 33 and expose pin bottom surface.Coating the 3rd passivation layer 39 and etch the 9th groove 40, high-frequency sputtering copper metal layer 41 also etches the tenth groove 42, and coating the 4th passivation layer 43 etches UBM2Window 44, the many metal levels of high-frequency sputtering form UBM2Layer 45.Use the printing of encapsulation, plant ball reflow soldering process, make soldered ball, pin bottom surface, UBM2Layer 45 is firmly connected, and finally carries out second time plastic packaging and fixedly secures soldered ball.The method can substitute part BGA and the CPS of substrate production, it is achieved IC chip is flexibly applied to the CSP encapsulation of lead frame, reduces production cost, shortens the R&D cycle.
Embodiment
1
8～the 12 thinning machines of use, use corase grind, thin fine-grinding and polishing warpage preventing technique, and the wafer of band bump chip is thinned to 180 μm, roughly grind speed 6 μm/s, refine speed 1.0 μm/s；Use corase grind, thin fine-grinding and polishing warpage preventing technique, the wafer without bump chip is thinned to 50 μm, roughly grind speed 2 μm/s, refine speed 6.0 μm/min；Employing prevents chip warpage technique；Use A-WD-300TXB scribing machine that the wafer after thinning is carried out scribing, scribing feed velocity≤10mm/s；Uniformly coat one layer of positive photoresist in bare copper frame front, form photoresist layer；Toast 30 minutes at a temperature of 60 DEG C；Then carry out alignment exposure, development, fixing, photoresist layer is formed and on multiple second groove and bare copper frame corresponding to multiple 3rd groove, the second groove and the 3rd groove, demonstrates pattern, post bake 30 minutes at a temperature of 120 DEG C；By spraying downwards acid etching solution, the first groove of the accompanying drawing shape needed is gone out in the bare copper frame front-side etch that the second groove is corresponding, first groove is pin groove, the bare copper frame front-side etch that 3rd groove is corresponding goes out the 4th groove of the accompanying drawing shape needed, form partition wall between adjacent two the 4th grooves, remove photoresist layer；Uniformly coat the first passivation layer in bare copper frame front, the first passivation layer covers the first groove surfaces and the 3rd groove surfaces simultaneously；Then on the first passivation layer of the 4th bottom portion of groove, UBM is etched1Window, etches framework pad openings on first passivation layer on the first bare copper frame surface, groove both sides；At the 4th groove many metal levels of inner surface high-frequency sputtering, form UBM1Layer；The many metal levels of high-frequency sputtering on framework pad openings, form framework pad, by photoetching, etching step, remove unnecessary metal level so that the UBM in adjacent 4th groove1Layer is not attached to, framework pad openings and UBM1Layer is not attached to, the UBM in the 4th groove and the 4th groove1Layer constitutes mounting groove；UBM1The structure of layer is identical with the structure of framework pad, and by three-layer metal layer, this three-layer metal layer is the first metal layer, the second metal level and the 3rd metal level set gradually；The first metal layer Cu layer, the second metal level is Ni layer, and the 3rd metal level is Au layer；The first metal layer is connected with the first passivation layer and the 4th groove floor；Being stained with solder on the chip bump of the IC chip of band salient point, by core in the IC flip-chip of this band salient point on bare copper frame, make chip bump stretch in mounting groove, chip bump top is by solder and the UBM in mounting groove1Layer is connected；The lower filling mould using band vac sorb carries out lower filling to the space between chip bump and mounting groove, makes chip bump be insulated by lower filler with framework；IC chip back at band salient point stacks the 2nd IC chip by a DAF sheet, baking, then make a call to the first bonding line from the 2nd IC chip to the framework pad between the first groove and mounting groove, play fourth bond line from the 2nd IC chip to the framework pad being positioned at outside the first groove；2nd IC chip stacks the 3rd IC chip, 3rd IC chip passes through the 2nd DAF sheet and the 2nd IC die bonding, baking, then makes a call to the second bonding line from the 3rd IC chip to the 2nd IC chip, then plays third bond line from the 3rd IC chip to being positioned at the framework pad outside the first groove bare copper frame；Use full-automatic sealing machine, use low stress (a1≤ 1), low moisture absorption (water absorption rate < 0.25%) meet European Union's Weee, ROHS standard and Sony standard environment-friendly type plastic packaging material carries out plastic packaging for the first time to bare copper frame front, form the second plastic-sealed body, second plastic-sealed body covers all of IC chip, all of DAF sheet and all of bonding line, second plastic-sealed body embeds in the first groove, with lead frame strong bonded；Solidify after carrying out by general anti-absciss layer technique after plastic packaging；On equipment for grinding, the grinding bare copper frame back side, the thickness that grinding is gone is the 1/3 of bare copper frame thickness, cleans up, dries；Bare copper frame backside coating the second passivation layer after grinding, then expose on litho machine, develop, fixing, etching the 5th groove and the 6th groove on the second passivation layer, the 5th groove is positioned at the lower section of the first groove, and all there is the 6th groove lower section of each partition wall；Along the 5th groove and the 6th recess etch bare copper frame, the bare copper frame that 5th groove is corresponding etches the 7th groove, the 7th groove and the first groove is made to communicate, the bare copper frame that 6th groove is corresponding etches the 8th groove, making the 8th groove below partition wall communicate with corresponding partition wall, the degree of depth of the 8th groove of remaining position is identical with the degree of depth of the 8th groove below partition wall, is pin between adjacent two grooves, remove the second passivation layer, expose pin bottom surface；At bare copper frame backside coating the 3rd passivation layer, 3rd passivation layer should fill up all of 7th groove in the bare copper frame back side and all of 8th groove, also to cover one layer at all pin back sides, on the 3rd passivation layer of relative the 3rd passivation layer of pin and the position of needs, then etch the 9th groove of accompanying drawing shape；At bare copper frame back side high-frequency sputtering copper metal layer, etching the tenth groove on copper metal layer, the tenth groove and the 3rd passivation layer communicate；At copper metal layer surface-coated the 4th passivation layer, the 4th passivation layer fills the tenth groove simultaneously, then etches UBM on the 4th passivation layer2Window, UBM2Window communicates with copper metal layer；At UBM2High-frequency sputtering multiple layer metal on window, forms UBM2Layer, UBM2The structure of layer and UBM1The structure of layer is identical；At UBM2Brush solder on Ceng, then soldering ball is placed on solder, make soldering ball, solder and UBM by Reflow Soldering2Layer strong bonded, cleans；Carrying out second time plastic packaging in the 4th passivation layer surface, form the first plastic-sealed body, all of soldering ball is exposed independent from outside the first plastic-sealed body, and the first plastic-sealed body fixedly secures soldering ball；Then print, cut separation, test, prepare tape welding spherical array flat-four-side without pin IC chip stacked packaging piece.Print, cutting uses the equipment with QFN same processes and technique when separating, and uses the equipment identical with BGA package and technique during test.
Embodiment
2
Thinned wafer scribing as described in Example 1, the wafer of band bump chip is thinned to 200 μm, and the wafer without bump chip is thinned to 75 μm；Uniformly coat one layer of positive photoresist in bare copper frame front, form photoresist layer；Toast 20 minutes at a temperature of 70 DEG C；It is then aligned with exposure, development, fixing, photoresist layer is formed and on multiple second groove and bare copper frame corresponding to multiple 3rd groove, the second groove and the 3rd groove, demonstrates pattern, post bake 25 minutes at a temperature of 125 DEG C；By spray alkaline corrosion liquid downwards, the first groove of the accompanying drawing shape needed is gone out in the bare copper frame front-side etch that the second groove is corresponding, the bare copper frame front-side etch that 3rd groove is corresponding goes out the 4th groove of the accompanying drawing shape needed, the bare copper frame front-side etch that 3rd groove is corresponding goes out the 4th groove of the accompanying drawing shape needed, form partition wall between adjacent two the 4th grooves, remove photoresist layer；Uniformly coat the first passivation layer in bare copper frame front, the first passivation layer of the 4th bottom portion of groove etches UBM1Window, etches framework pad openings on first passivation layer on the first bare copper frame surface, groove both sides；At the 4th groove many metal levels of inner surface high-frequency sputtering, form UBM1Layer；The many metal levels of high-frequency sputtering on framework pad openings, form framework pad, by photoetching, etching step, remove unnecessary metal level so that the UBM in adjacent 4th groove1Layer is not attached to, framework pad openings and UBM1Layer is not attached to, the UBM in the 4th groove and the 4th groove1Layer constitutes mounting groove；UBM1The structure of layer is identical with the structure of framework pad, and by three-layer metal layer, this three-layer metal layer is the first metal layer, the second metal level and the 3rd metal level set gradually；The first metal layer is Ni layer, and the second metal level is Cr layer, and the 3rd metal level is Au layer；The first metal layer is connected with the first passivation layer and the 4th groove floor；Preparing tape welding spherical array flat-four-side the most as described in Example 1 without pin IC chip stacked packaging piece, simply when the grinding bare copper frame back side, the thickness that grinding is gone is the 1/4 of bare copper frame thickness.
Embodiment
3
Thinned wafer scribing as described in Example 1, the wafer of band bump chip is thinned to 190 μm, and the wafer without bump chip is thinned to 60 μm；Uniformly coat one layer of positive photoresist in bare copper frame front, form photoresist layer；Toast 25 minutes at a temperature of 65 DEG C；It is then aligned with exposure, development, fixing, photoresist layer is formed and on multiple second groove and bare copper frame corresponding to multiple 3rd groove, the second groove and the 3rd groove, demonstrates pattern, post bake 35 minutes at a temperature of 115 DEG C；By spray alkaline corrosion liquid downwards, the first groove of the accompanying drawing shape needed is gone out in the bare copper frame front-side etch that the second groove is corresponding, the bare copper frame front-side etch that 3rd groove is corresponding goes out the 4th groove of the accompanying drawing shape needed, the bare copper frame front-side etch that 3rd groove is corresponding goes out the 4th groove of the accompanying drawing shape needed, form partition wall between adjacent two the 4th grooves, remove photoresist layer；Uniformly coat the first passivation layer in bare copper frame front, the first passivation layer of the 4th bottom portion of groove etches UBM1Window, etches framework pad openings on first passivation layer on the first bare copper frame surface, groove both sides；At the 4th groove many metal levels of inner surface high-frequency sputtering, form UBM1Layer；The many metal levels of high-frequency sputtering on framework pad openings, form framework pad, by photoetching, etching step, remove unnecessary metal level so that the UBM in adjacent 4th groove1Layer is not attached to, framework pad openings and UBM1Layer is not attached to, the UBM in the 4th groove and the 4th groove1Layer constitutes mounting groove；UBM1The structure of layer is identical with the structure of framework pad, and by two layers of metal level, these two layers of metal levels are the first metal layer, the second metal level and the 3rd metal level set gradually；The first metal layer is Cu layer, and the second metal level is Cr layer, and the 3rd metal level is Au layer；The first metal layer is connected with the first passivation layer and the 4th groove floor；Preparing tape welding spherical array flat-four-side the most as described in Example 1 without pin IC chip stacked packaging piece, simply when the grinding bare copper frame back side, the thickness that grinding is gone is the 7/24 of bare copper frame thickness.
Embodiment
4
Thinned wafer scribing as described in Example 1, the wafer of band bump chip is thinned to 185 μm, and the wafer without bump chip is thinned to 55 μm；Uniformly coat one layer of positive photoresist in bare copper frame front, form photoresist layer；Toast 24 minutes at a temperature of 65 DEG C；It is then aligned with exposure, development, fixing, photoresist layer is formed and on multiple second groove and bare copper frame corresponding to multiple 3rd groove, the second groove and the 3rd groove, demonstrates pattern, post bake 32 minutes at a temperature of 118 DEG C；By spraying downwards acid etching solution, the first groove of the accompanying drawing shape needed is gone out in the bare copper frame front-side etch that the second groove is corresponding, the bare copper frame front-side etch that 3rd groove is corresponding goes out the 4th groove of the accompanying drawing shape needed, the bare copper frame front-side etch that 3rd groove is corresponding goes out the 4th groove of the accompanying drawing shape needed, form partition wall between adjacent two the 4th grooves, remove photoresist layer；Uniformly coat the first passivation layer in bare copper frame front, the first passivation layer of the 4th bottom portion of groove etches UBM1Window, etches framework pad openings on first passivation layer on the first bare copper frame surface, groove both sides；At the 4th groove many metal levels of inner surface high-frequency sputtering, form UBM1Layer；The many metal levels of high-frequency sputtering on framework pad openings, form framework pad, by photoetching, etching step, remove unnecessary metal level so that the UBM in adjacent 4th groove1Layer is not attached to, framework pad openings and UBM1Layer is not attached to, the UBM in the 4th groove and the 4th groove1Layer constitutes mounting groove；UBM1The structure of layer is identical with the structure of framework pad, and by two metal layers, this two metal layers is the first metal layer set gradually and the 3rd metal level；The first metal layer is Ni layer, and the 3rd metal level is Au layer；The first metal layer is connected with the first passivation layer and the 4th groove floor；Prepare tape welding spherical array flat-four-side the most as described in Example 1 without pin IC chip stacked packaging piece.
Embodiment
5
Thinned wafer scribing as described in Example 1, the wafer of band bump chip is thinned to 195 μm, and the wafer without bump chip is thinned to 70 μm；Uniformly coat one layer of positive photoresist in bare copper frame front, form photoresist layer；Toast 22 minutes at a temperature of 68 DEG C；It is then aligned with exposure, development, fixing, photoresist layer is formed and on multiple second groove and bare copper frame corresponding to multiple 3rd groove, the second groove and the 3rd groove, demonstrates pattern, post bake minute at a temperature of 122 DEG C；By spraying downwards acid etching solution, the first groove of the accompanying drawing shape needed is gone out in the bare copper frame front-side etch that the second groove is corresponding, the bare copper frame front-side etch that 3rd groove is corresponding goes out the 4th groove of the accompanying drawing shape needed, the bare copper frame front-side etch that 3rd groove is corresponding goes out the 4th groove of the accompanying drawing shape needed, form partition wall between adjacent two the 4th grooves, remove photoresist layer；Uniformly coat the first passivation layer in bare copper frame front, the first passivation layer of the 4th bottom portion of groove etches UBM1Window, etches framework pad openings on first passivation layer on the first bare copper frame surface, groove both sides；At the 4th groove many metal levels of inner surface high-frequency sputtering, form UBM1Layer；The many metal levels of high-frequency sputtering on framework pad openings, form framework pad, by photoetching, etching step, remove unnecessary metal level so that the UBM in adjacent 4th groove1Layer is not attached to, framework pad openings and UBM1Layer is not attached to, the UBM in the 4th groove and the 4th groove1Layer constitutes mounting groove；UBM1The structure of layer is identical with the structure of framework pad, and by two metal layers, this two metal layers is the first metal layer set gradually and the 3rd metal level；The first metal layer is Cr layer, and the 3rd metal level is Au layer；The first metal layer is connected with the first passivation layer and the 4th groove floor；Prepare tape welding spherical array flat-four-side the most as described in Example 1 without pin IC chip stacked packaging piece.
Although having shown that in conjunction with preferred embodiment and describing the present invention, it will be understood by those skilled in the art that on the premise of the spirit and scope of the present invention defined in the appended claims, can modify and convert.
Claims (4)
1. tape welding spherical array four limit is without pin IC chip stacked packaging piece, including bare copper frame (1), bare copper frame (1) is provided with the first groove (11) and multiple mounting groove, it is provided with partition wall (8) between adjacent two mounting grooves, bare copper frame (1) front upside-down mounting has an IC chip (9) of band salient point, chip bump (7) on this IC chip stretches in mounting groove, space between chip bump (7) and mounting groove is filled with lower filler (10), bare copper frame (1) front plastic packaging has the first plastic-sealed body (20), it is characterized in that, first groove (11) both sides are respectively the first pin (23) and the second pin (24)；First groove (11) bottom is connected with passivation (2), and the first pin (23) is connected with the second pin (24) by passivation (2), and the first pin (23) bottom is provided with the second articulamentum (22)；It is connected with the second pin (24) bottom by the first articulamentum (3) bottom the mounting groove adjacent with the second pin (24), the first articulamentum (3) it is equipped with bottom remaining mounting groove, all of first articulamentum (3) and all of second articulamentum (22) are all not attached to, each first articulamentum (3) bottom and each second articulamentum (22) bottom are equipped with soldering ball (5), all passivation (2) surface and all articulamentum surfaces plastic packaging have the first plastic-sealed body (4), all of soldering ball (5) to be exposed independent from the first plastic-sealed body (4) outward；IC chip with salient point has stacked gradually two-layer IC chip, and the IC chip being positioned at lower section is connected with the second pin (24) by the first bonding line (12), is connected with the first pin (23) by fourth bond line (19) simultaneously；IC chip above is connected with the IC chip being positioned at lower section by the second bonding line (13), and IC chip above is connected with the first pin (23) by third bond line (18).
2. tape welding spherical array four limit described in a claim 1 is without the production method of pin IC chip stacked packaging piece, it is characterised in that this production method specifically sequentially includes the following steps:
Step 1: wafer reduction scribing；
Step 2: uniformly coat photoresist in bare copper frame front, forms photoresist layer (25)；Toast 25 ± 5 minutes at a temperature of 60 DEG C～70 DEG C；It is then aligned with exposure, development, fixing, forms multiple second grooves (26) and multiple 3rd groove (27), post bake 30 ± 5 minutes at a temperature of 120 DEG C ± 5 DEG C photoresist layer (25) is upper；Then the first groove (11) is gone out in bare copper frame (1) front-side etch that the second groove (26) is corresponding, bare copper frame (1) front-side etch that 3rd groove (27) is corresponding goes out the 4th groove (28), form partition wall (8) between adjacent two the 4th grooves (28), remove photoresist layer (25)；
Step 3: the surface etching the first groove (11) and the 4th groove (28) at bare copper frame uniformly coats the first passivation layer (29), and the first passivation layer (29) covers the first groove (11) surface and the 3rd groove (27) surface simultaneously；Then on first passivation layer (29) of the 4th groove (28) bottom, UBM is etched1Window (30), etches framework pad openings (31) on first passivation layer (29) on bare copper frame (1) surface, the first groove (11) both sides；
Step 4: the many metal levels of high-frequency sputtering, in the 4th groove, (28) surface forms UBM1Layer (32)；At the upper framework pad (21) that formed of framework pad openings (31), removal excess metal layer so that the UBM in adjacent 4th groove (28)1Layer (32) is not attached to, framework pad openings (31) and UBM1Layer (32) is not attached to, the UBM in the 4th groove (28) and the 4th groove (28)1Layer (32) constitutes mounting groove；UBM1The structure of layer (32) is identical with the structure of framework pad (21), constituted by three-layer metal layer or two metal layers, when using three-layer metal layer, this three-layer metal layer is the first metal layer (a), the second metal level (b) and the 3rd metal level (c) set gradually；When using two metal layers, this two metal layers is the first metal (a) layer and the 3rd metal level (c) set gradually；The first metal layer (a) is Cu layer, Ni layer or Cr layer, and the second metal level (b) is Ni layer, Cu layer or Cr layer, and the 3rd metal level (c) is Au layer；The first metal layer (a) is connected with the first passivation layer (29) and the 4th groove (28) bottom surface；
Step 5: by core in IC chip (9) upside-down mounting of band salient point on bare copper frame (1), chip bump (7) stretches in mounting groove；Then use the lower filling mould of band vac sorb that the space between chip bump (7) and mounting groove is carried out lower filling, make chip bump (7) be insulated by lower filler (10) with framework；
Step 6: at IC chip (9) back side stacking a 2nd IC chip (15) of band salient point, baking, then making a call to the first bonding line (12) from the 2nd IC chip (15) to the framework pad (21) being positioned between the first groove (11) and mounting groove, the pad from the 2nd IC chip (15) plays fourth bond line (19) to the framework pad (21) being positioned at the first groove (11) outside；
Step 7: at the 2nd IC chip (15) upper stacking the 3rd IC chip (17), baking, then make a call to the second bonding line (13) from the 3rd IC chip (17) to the 2nd IC chip (15), then play third bond line (18) from the 3rd IC chip (17) to the framework pad (21) being positioned at the first groove (11) outside bare copper frame (1) is upper；
Step 8: employing meets European Union's Weee, ROHS standard and Sony standard environment-friendly type plastic packaging material carries out plastic packaging to bare copper frame front, form the second plastic-sealed body (20), second plastic-sealed body (20) covers all IC chips and all of bonding line, second plastic-sealed body (20) embeds in the first groove (11), solidifies after carrying out by general anti-absciss layer technique after plastic packaging；
Step 9: the grinding bare copper frame back side, cleans, dries；
Step 10: the bare copper frame backside coating the second passivation layer (33) after grinding, then expose, develop, fixing, second passivation layer (33) etches the 5th groove (34) and the 6th groove (35), 5th groove (34) is positioned at the first groove (11) lower section, and all there is the 6th groove (35) each partition wall (8) lower section；
Step 11: etch bare copper frame (1) along the 5th groove (34) and the 6th groove (35), the bare copper frame (1) that 5th groove (34) is corresponding etches the 7th groove (36), the 7th groove (36) is made to communicate with the first groove (11), the bare copper frame (1) that 6th groove (35) is corresponding etches the 8th groove (37), the 8th groove (37) making partition wall (8) lower section communicates with corresponding partition wall (8), the degree of depth of the 8th groove (37) of remaining position is identical with the degree of depth of partition wall (8) lower section the 8th groove (37), it is pin between adjacent two grooves, remove the second passivation layer (33), expose pin bottom surface；
Step 12: at bare copper frame (1) backside coating the 3rd passivation layer (39), 3rd passivation layer (39) fills up all of 7th groove (36) in bare copper frame (1) back side and all of 8th groove (37) simultaneously, then etches the 9th groove (40) on relative the 3rd passivation layer (39) of pin and the 3rd passivation layer (39) of position that needs；
Step 13: at bare copper frame (1) back side high-frequency sputtering copper metal layer, then etches the tenth groove (42) on copper metal layer (41), and the tenth groove (42) communicates with the 3rd passivation layer (39)；
Step 14: in copper metal layer (41) surface-coated the 4th passivation layer (43), the 4th passivation layer (43) is filled the tenth groove (42) simultaneously, then etched UBM on the 4th passivation layer2Window (44), UBM2Window (44) communicates with copper metal layer (41)；
Step 15: at UBM2The upper high-frequency sputtering of window (44) forms UBM2Layer (45), UBM2The structure of layer (45) and UBM1The structure of layer (32) is identical；
Step 16: by planting ball, Reflow Soldering at UBM2Layer (45) upper welding soldering ball (5), cleans；
Step 17: carry out second time plastic packaging on the 4th passivation layer (43) surface, form the first plastic-sealed body (4), all of soldering ball (5) is exposed independent from the first plastic-sealed body (4) outward, then prints, cuts separation, test, prepares tape welding spherical array flat-four-side without pin IC chip stacked packaging piece.
The most according to claim 2, tape welding spherical array four limit is without the production method of pin IC chip stacked packaging piece, it is characterized in that, in described step 1: use 8～12 thinning machines, use corase grind, thin fine-grinding and polishing warpage preventing technique, the wafer of band bump chip is thinned to 180 μm～200 μm, corase grind speed 6 μm/s, refines speed 1.0 μm/s；Use corase grind, thin fine-grinding and polishing warpage preventing technique, the wafer without bump chip is thinned to 50 μm～75 μm, roughly grind speed 2 μm/s, refine speed 6.0 μm/min；Employing prevents chip warpage technique；
Use A-WD-300TXB scribing machine that the wafer after thinning is carried out scribing, scribing feed velocity≤10mm/s.
The most according to claim 2, tape welding spherical array four limit is without the production method of pin IC chip stacked packaging piece, it is characterised in that in described step 9, and the thickness that bare copper frame (1) grinding is gone is the 1/3～1/4 of bare copper frame (1) thickness.
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| CN110246764A (en) * | 2019-04-25 | 2019-09-17 | 北京燕东微电子有限公司 | A kind of chip package process and chip-packaging structure |
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| CN102522391A (en) * | 2011-12-31 | 2012-06-27 | 天水华天科技股份有限公司 | e/LQFP (low-profile quad flat package) stacked package with grounded ring and production method of e/LQFP stacked package with grounded ring |
| CN103021994A (en) * | 2012-12-28 | 2013-04-03 | 华天科技（西安）有限公司 | Package using optimized AQFN (advanced quad flat no-lead) secondary plastic packaging and secondary ball placement and manufacturing process thereof |
| CN203674204U (en) * | 2013-12-31 | 2014-06-25 | 天水华天科技股份有限公司 | Area-array quad-no-lead IC chip PiP (Package in Package) part |
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