KR20010061849A - Wafer level package - Google Patents

Wafer level package Download PDF

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Publication number
KR20010061849A
KR20010061849A KR1019990064391A KR19990064391A KR20010061849A KR 20010061849 A KR20010061849 A KR 20010061849A KR 1019990064391 A KR1019990064391 A KR 1019990064391A KR 19990064391 A KR19990064391 A KR 19990064391A KR 20010061849 A KR20010061849 A KR 20010061849A
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South Korea
Prior art keywords
metal wire
wafer
surface
insulating layer
metal
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KR1019990064391A
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Korean (ko)
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박상욱
Original Assignee
박종섭
주식회사 하이닉스반도체
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Priority to KR1019990064391A priority Critical patent/KR20010061849A/en
Publication of KR20010061849A publication Critical patent/KR20010061849A/en

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/94Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/43Manufacturing methods
    • H01L2224/431Pre-treatment of the preform connector
    • H01L2224/4312Applying permanent coating, e.g. in-situ coating
    • H01L2224/43125Plating, e.g. electroplating, electroless plating
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909Post-treatment of the connector or wire bonding area
    • H01L2224/8592Applying permanent coating, e.g. protective coating

Abstract

PURPOSE: A wafer level package is provided to simplify a manufacturing process, by using a metal wire instead of a metal pattern to electrically connect a solder ball with a semiconductor chip. CONSTITUTION: A bonding pad(11) is disposed on the surface of a semiconductor chip. An insulating layer(20) is applied on the surface of the semiconductor chip to expose the bonding pad. A dummy pad(12) is formed on the insulating layer. A metal wire(30) electrically connects the dummy pad with the bonding pad. A metal layer is plated on the metal wire to coat the metal wire. An upper portion of the insulating layer is molded with an encapsulating material(21) to expose a portion of the metal wire.

Description

웨이퍼 레벨 패키지{WAFER LEVEL PACKAGE} The wafer-level package {WAFER LEVEL PACKAGE}

본 발명은 웨이퍼 레벨 패키지에 관한 것으로서, 보다 구체적으로는 웨이퍼상태에서 패키징 공정이 이루어지는 패키지에 관한 것이다. The present invention relates to a wafer-level package, and more particularly to a package made of a packaging process in the wafer state.

기존의 패키지는 웨이퍼를 먼저 스크라이브 라인을 따라 절단하여 개개의 반도체 칩으로 분리한 후, 개개의 반도체 칩별로 여러 가지 패키징 공정을 실시하는 것에 의해 제조되었다. Existing packages then cut along the scribe line of the wafer before separation into individual semiconductor dice, was prepared by performing a number of packaging processes for each individual semiconductor chip.

그러나, 상기된 기존의 패키지는 개개의 반도체 칩별로 많은 단위 공정이 실시되어야 하기 때문에, 하나의 웨이퍼에서 제조되는 반도체 칩들을 고려하게 되면, 공정수가 너무 많다는 문제점을 안고 있다. However, in the above existing package, when because they must be carried many unit processes each of the individual semiconductor chips, to take account of the semiconductor chip to be produced on a single wafer, the number of process faces the problem too much.

그래서, 최근에는 웨이퍼를 먼저 절단하지 않고 웨이퍼 상태에서 상기된 패키징 공정을 우선적으로 실시한 후, 최종적으로 스크라이브 라인을 따라 절단하여 패키지를 제조하는 방안이 제시되었다. So, in recent years, and then subjected to a packaging process in the wafer state, without cutting the wafer first with priority, and finally cut along the scribe line have been proposed as a scheme for producing the package. 이러한 방법으로 제조된 패키지를 웨이퍼 레벨 패키지라 하는데, 이를 제조하는 방법을 개략적으로 설명하면 다음과 같다. A package manufactured in this way in the wafer-level package la, when an overview of the process for preparing them as follows.

웨이퍼 표면에는 실리콘 질화막인 보호막이 도포되어 있다. Wafer surface, there is applied a protective layer of silicon nitride. 웨이퍼 표면에 구성된 반도체 칩의 본딩 패드는 식각에 의해 보호막에 형성된 홈을 통해 노출되어 있다. Bonding pads of the semiconductor chip is configured on the surface of the wafer is exposed through the groove formed in the protection film by etching.

이러한 상태에서, 보호막 전체 표면에 하부 절연층을 도포한다. In this state, the lower insulating layer is coated on the entire surface of the protective film. 본딩 패드 상부에 위치한 하부 절연층을 식각하여 본딩 패드를 외부로 노출시킨다. Etching the lower insulating layer located above the bonding pad to expose the bonding pads to the outside. 그런 다음, 구리나 알루미늄 재질의 금속막을 전체 구조 표면상에 진공 증착한다. Then, a copper or aluminum film having a metal is vacuum-deposited on the entire structure surface. 이때, 금속막은 본딩 패드에도 증착된다. At this time, the metal film is deposited in the bonding pad. 이어서, 금속막을 부분 식각하여, 일단은 본딩 패드에 전기적으로 연결되고 타단은 하부 절연층상에 위치하는 금속 패턴을 형성한다. Then, by etching the metal film portion, one end is electrically connected to the bonding pad and the other end is formed a metal pattern located beneath the insulating layer. 그런 다음, 전체 구조 표면에 상부 절연층을 도포한 후, 금속 패턴의 타단 상부에 위치한 상부 절연층 부분을 식각하여 금속 패턴의 타단을 노출시킨다. Then, after coating an upper insulating layer on the entire structure surface, by etching the upper dielectric layer portion located at the other end the upper portion of the metal pattern to expose the other ends of the metal pattern. 노출된 금속 패턴의 타단이 솔더 볼이 마운트되는 볼 랜드가 된다. The other end of the exposed metal pattern is a ball lands which the solder ball is mounted.

이어서, 볼 랜드에 구형의 솔더 볼을 올려놓은 후, 자외선을 이용한 리플로우 공정을 통해 솔더 볼과 볼 랜드를 접착시키므로써, 반도체 칩의 본딩 패드와 기판에 실장되는 솔더 볼을 전기적으로 연결시킨다. Then, move up a solder ball of a spherical ball lands, through the reflow process using a UV written because bonding the solder ball and the land, thereby electrically connecting the solder ball is mounted to the bonding pad and the substrate of the semiconductor chip. 마지막으로, 웨이퍼에 형성된 스크라이브 라인을 따라 절단하여 개개의 반도체 칩으로 분리하면, 웨이퍼 레벨 패키지가 완성된다. Finally, by cutting along a scribe line formed on the wafer divided into individual semiconductor chips, the wafer-level package is completed.

종래의 웨이퍼 레벨 패키지에서는, 솔더 볼과 반도체 칩의 패드를 전기적으로 연결하기 위해서 전술된 바와 같이, 금속 패턴이 이용된다. In the conventional wafer-level package, as described above in order to electrically connect the pads of the solder balls and the semiconductor chip, the metal pattern is used. 그런데, 금속 패턴을 형성하기 위해서는, 하부 절연층 전체 표면에 금속막을 증착한 후, 이를 패터닝해야만 한다. By the way, then in order to form a metal pattern, depositing a metal film on the entire surface of the lower insulating layer, it must be patterned.

이러한 금속 패턴 형성 공정은 마스크를 이용해서 패터닝을 실시해야 하기 때문에, 공정이 매우 복잡하다는 단점은 예전부터 주지된 사실이다. Since such a metal pattern forming process using the mask to be subjected to patterning, a disadvantage that the process is very complex, is that known in the past. 또한, 패터닝되어 제거된 금속막은 전부 낭비되는 단점도 갖고 있다. In addition, it has the disadvantage that metal film is patterned to remove all waste.

따라서, 본 발명은 금속 패턴을 이용한 웨이퍼 레벨 패키지가 안고 있는 제반 문제점을 해소하기 위해 안출된 것으로서, 솔더 볼과 반도체 칩의 본딩 패드를 전기적으로 연결하는 수단을 간단한 공정으로 형성할 수 있으면서 재료의 낭비도 방지할 수 있는 웨이퍼 레벨 패키지를 제공하는데 목적이 있다. Accordingly, the present invention can form a as the means for electrically connecting the bonding pads of the solder balls and the semiconductor chip conceived to address the overall problem facing the wafer-level package using a metal pattern with a simple process while waste of material It aims to provides a chip scale package that can be prevented.

도 1 내지 도 19는 본 발명의 실시예 1에 따른 웨이퍼 레벨 패키지를 제조 공정 순서대로 나타낸 도면. Figures 1 to 19 is a view illustrating as exemplary wafer-level package production process procedure according to the first embodiment of the present invention.

도 20 내지 도 22는 본 발명의 실시예 2에 따른 웨이퍼 레벨 패키지를 제조 공정 순서대로 나타낸 단면도. 20 to 22 is a cross-sectional view showing a wafer-level package according to a second embodiment of the invention in the manufacturing process sequence.

도 23은 본 발명의 실시예 3에 따른 웨이퍼 레벨 패키지를 나타낸 단면도. Figure 23 is a sectional view of the wafer-level package according to a third embodiment of the invention.

도 24는 본 발명의 실시예 4에 따라 웨이퍼 레벨 패키지가 멀티 타입으로 구현된 상태를 나타낸 단면도. 24 is a wafer-level package is a sectional view showing a state where the multi-type implement according to a fourth embodiment of the present invention.

- 도면의 주요 부분에 대한 부호의 설명 - - of the Related Art Description

10 ; 10; 웨이퍼 11 ; Wafer 11; 본드 패드 Bond pads

12 ; 12; 더미 패드 20 ; Dummy pad 20; 절연층 Insulating layer

21 ; 21; 봉지제 30 ; Bag of claim 30; 금속 와이어 Metal wire

42 ; 42; 솔더 볼 Solder Ball

상기와 같은 목적을 달성하기 위하여, 본 발명에 따른 웨이퍼 레벨 패키지는 다음과 같은 구성으로 이루어진다. In order to achieve the above object, a wafer-level package according to the present invention comprises the following configurations.

반도체 칩의 표면에 본딩 패드가 노출되도록 절연층이 도포된다. An insulating layer is applied so that the bonding pads are exposed on the surface of the semiconductor chip. 절연층상에는 더미 패드가 형성된다. The insulating layer is formed with a dummy pad. 금속 와이어의 양단이 본딩 패드와 더미 패드 각각에 연결된다. Both ends of the metal wires are coupled to respective bonding pads and dummy pads. 금속 와이어는 도금된 금속막에 의해 피복된다. Metal wires are covered with a plated metal film. 금속 와이어의 중간부가 노출되도록, 절연층 상부가 봉지제로 봉지된다. So that the intermediate portion expose the metal wire, the upper insulating layer is sealed bags zero. 노출된 금속 와이어의 중간부에 솔더 볼이 마운트된다. The solder balls are mounted on an intermediate portion of the exposed metal wire.

상기된 본 발명의 구성에 의하면, 금속 패턴 대신에 금속 와이어가 사용되므로써, 간단한 와이어 본딩 공정이 웨이퍼 레벨 패키지에 적용될 수가 있다. According to the configuration of the present invention, the metal wire used in place of the metal pattern doemeurosseo, a simple wire-bonding process can be applied to a wafer-level package. 특히, 금속 와이어를 이용한 와이어 본딩 공정에서는 낭비되는 부분이 거의 없다는 장점도 있다. In particular, the advantage is almost no wasted portion of the wire bonding process using a metal wire.

이하, 본 발명의 바람직한 실시예를 첨부도면에 의거하여 설명한다. It will be described below with the accompanying drawings preferred embodiments of the invention.

[실시예 1] Example 1

도 1 내지 도 19는 본 발명의 실시예 1에 따른 웨이퍼 레벨 패키지를 제조 공정 순서대로 나타낸 도면이다. Figure 1 to Figure 19 is a view showing, as an embodiment of a wafer-level package production process procedure according to the first embodiment of the present invention.

먼저, 도 1에 도시된 바와 같이, 복수개의 반도체 칩이 구성된 웨이퍼(10)를 테이블(1)상에 올려놓고, 도 2와 같이 절연층(20)을 웨이퍼(10) 표면에 도포하면, 도 3과 같이 웨이퍼(10) 표면에 균일한 두께로 절연층(20)이 형성된다. First, there is shown applied to place the plurality of semiconductor chip is a wafer (10) configured on a table (1), the wafer 10 an insulating layer 20 as shown in Figure 2 the surface, as shown in Fig. 1, Fig. 3 the insulating layer 20 with a uniform thickness on the wafer 10 surface is formed as shown.

이어서, 도 4와 같이 웨이퍼(10)를 테이블로부터 분리한 후, 도 5에 도시된 바와 같이, 절연층(20)을 식각하여 본드 패드(11)를 노출시킨다. Next, after removing the wafer 10 as shown in FIG. 4, from the table, to expose the bond pads 11, etching the insulating layer 20 as shown in Fig. 그런 다음, 도 6과 같이 절연층(20)상에 더미 패드(12)를 형성한 후, 금속 와이어(30)의 양단을 본드 패드(11)와 더미 패드(12)에 연결시키면, 도 7과 같이 본드 패드(11)와 더미 패드(12)가 금속 와이어(30)를 매개로 전기적으로 연결된다. Then, after forming the dummy pads 12 on the insulating layer 20 as shown in Figure 6, when connecting the ends of the metal wire 30 to the bonding pad 11 and the dummy pad 12, and Figure 7 as the bond pads 11 and the dummy pad 12 it is electrically connected to the medium a metal wire 30. 이어서, 금 재질의 금속 와이어(30)의 강도 강화를 위해서, 금속 와이어(30)의 외주면을 니켈 재질의 금속막(31)으로 도금한다. Then, in order to enhance the strength of the metal wire 30 of gold material, and plating the outer peripheral surface of the metal wire 30 to the metal film 31 of nickel material.

그런 다음, 절연층(20) 상부 전체를 봉지제(21)로 몰딩하는데, 이러한 몰딩 방법에는 도 10 내지 도 11과 같은 3가지 방법이 있다. Then, in the molding of the entire upper insulating layer 20 to the sealing material 21, such a molding method, there are three methods as shown in FIG. 10 to FIG. 도 10에 도시된 방법은 웨이퍼(10)를 스핀 테이블(2)상에 올려놓은 상태에서 봉지제(21)를 스핀 코팅하는 방법이다. The method shown in Figure 10 is a method for spin coating a sealing material 21 in a state placed the wafer 10 on a spin table (2). 도 11에 도시된 방법은 상하부 다이(3,4) 내부에 웨이퍼(10)를 배치하고, 그 사이로 봉지제(21)를 주입한 상태에서, 상하부 다이(3,4)를 가압하여 봉지제(21)를 웨이퍼(10) 표면에 형성하는 방법이다. The method shown in Figure 11 is in a position the wafer 10 within the upper and lower dies (3,4), and injecting a sealing material 21 between the state, by pressing the upper and lower dies (3, 4) sealing material ( 21) the method of forming the wafer 10 surface. 도 12에 도시된 방법은 디스펜서를 이용해서 봉지제(21)를 웨이퍼(10) 표면에 도포하는 방식이다. The method shown in FIG. 12 is a method of using a dispenser is applied to sealing material 21 to the wafer 10 surface.

상기된 3가지 방법중 한 가지 방법을 채용하여, 봉지제(21)를 웨이퍼(10) 표면에 형성하면, 도 13과 같이 봉지제(21) 표면은 평탄하지 않고 굴곡진 형상이면서 금속 와이어(30)의 중간부가 노출되지 않은 상태이다. The adoption of one of the three methods above, the sealing material 21, the wafer 10 be formed on the surface, even sealing material 21, such as 13 surface, yet without the flat contoured shaped metal wire (30 ) is the intermediate portion of the non-exposed state. 그러므로, 봉지제(21) 표면을 평탄화하면서 금속 와이어(30)의 중간부를 노출시키기 위해, 봉지제(21) 표면을 식각하면, 도 14와 같이 금속 와이어(30)의 중간부가 노출된다. Therefore, in order to expose the middle of the metal wire 30 and flattening the sealing material 21 surface, if etching the sealing material (21) surface, and an intermediate exposed portion of the metallic wire 30 as shown in Fig. 이어서, 노출된 금속 와이어(30)의 중간부 및 이 영역을 세정하기 위해, 도 15와 같이 분사기(5)를 통해 고압수를 분사한다. Then, the high-pressure injection through the injector 5, as shown in FIG. 15 to clean the intermediate portion and the area of ​​exposed metal wire 30. 그런 다음, 도 16과 같이 블레이드(6)를 이용해서 스크라이브 라인을 따라 웨이퍼(10)를 절단하여, 도 17과 같이 개개의 반도체 칩으로 분리한다. Then, using the blade 6 as shown in Figure 16 by cutting the wafer 10 along the scribe line, and separated into individual semiconductor chips 17 as shown in Fig.

도 18은 최종적으로 완성된 웨이퍼 레벨 패키지의 일부 절개 사시도로서, 도시된 바와 같이, 더미 패드(12)와 본드 패드(11)가 금속 와이어(30)에 의해 전기적으로 연결되고, 금속 와이어(30)의 중간부가 봉지제(21)로부터 노출된다. 18 is a part of the final wafer level package, complete with cut-away perspective view, the dummy pads 12 and bond pads 11 are electrically connected by the metal wire 30, the metal wire 30 as shown the middle portion is exposed from the sealing material 21. 금속 와일어(30)의 노출 부분이 도 19와 같이 솔더(8)를 매개로 직접 보드(7)에 실장된다. The exposed portions of metal and up 30 is mounted on the board solder (7) directly to (8) as a parameter as shown in Fig.

[실시예 2] Example 2

도 20 내지 도 22는 본 발명의 실시예 2에 따른 웨이퍼 레벨 패키지를 제조 공정 순서대로 나타낸 단면도이다. 20 to 22 is a cross-sectional view of the second embodiment, as the wafer-level package production process sequence in accordance with the present invention. 실시예 1에서는 노출된 금속 와이어(30) 부분이 솔더(8)를 매개로 보드(7)에 직접 실장되었지만, 본 실시예 2에서는 솔더 볼(42)이 보드에 실장된다. In Example 1, the exposed metal wire 30, but this portion directly mounted on the board (7) as a medium of the solder 8, and is the second embodiment mounted on the solder ball 42 is board.

이를 위해, 도 20과 같이 노출된 금속 와이어(30) 부분에 코이닝(40:coining)을 형성한 후, 도 21과 같이 접합 보조층(41)을 코이닝(40)상에 형성한다. To this end, coining the metal wire 30 portion exposed as shown in Fig. 20: to form a bonding auxiliary layer 41 on the coining (40), such as after forming the (40 coining), Fig. 이어서, 솔더 볼(42)을 접합 보조층(41)상에 마운트한다. Then, mounting the solder balls 42 on the bonding auxiliary layer 41.

[실시예 3] Example 3

도 23은 본 발명의 실시예 3에 따른 웨이퍼 레벨 패키지를 나타낸 단면도이다. 23 is a cross-sectional view showing a wafer-level package according to a third embodiment of the invention. 도시된 바와 같이, 실시예 1과는 달리 절연층이 사용되지 않는다. As it illustrated in Example 1, and does the insulating layer is not used otherwise. 대신에, 더미 패드(12)를 갖는 절연 테이프(13)가 직접 웨이퍼(10) 표면에 접착되어서, 봉지제(21)로 와이어 본딩 부분 전체가 몰딩된다. Instead, be adhered to the insulating tape 13. The wafer 10 directly to the surface having the dummy pad 12, the entire wire-bonding portion is molded with sealing material (21).

[실시예 4] Example 4

도 24는 본 발명의 실시예 4에 따라 웨이퍼 레벨 패키키가 멀티 타입으로 구현된 것을 나타낸 단면도이다. 24 is a sectional view showing that a wafer level L Kiki is implemented as a multi-type in accordance with a fourth embodiment of the present invention. 도시된 바와 같이, 기판(51) 표면에 상기된 본 발명에 따른 웨이퍼 레벨 패키지가 실장되고, 상부에는 세라믹 캡슐(50)이 접착제(52)를 매개로 씌워진다. As shown, the substrate 51 is a wafer-level package according to the invention wherein the surface is mounted, the upper ceramic at the capsule 50 is covered by the medium of an adhesive 52. 기판(51) 밑면에는 보드 실장을 위한 솔더 볼(53)이 형성된다. Substrate 51 underneath, the solder balls 53 for the board mounted is formed.

이상에서 설명한 바와 같이 본 발명에 의하면, 금속 패턴 대신에 와이어 본딩 공정에 의한 금속 와이어가 사용되므로써, 공정이 매우 간단해지고 낭비되는 부분이 없어지게 된다. According to the present invention as described above, it doemeurosseo the metal wire by a wire bonding process used in place of the metal pattern, then you are not a part of the process is greatly simplified and waste.

이상에서는 본 발명의 바람직한 실시예에 대하여 도시하고 또한 설명하였으나, 본 발명은 상기한 실시예에 한정되지 않고, 이하 청구범위에서 청구하는 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 분야에서 통상의 지식을 가진자라면 누구든지 다양한 변경 실시가 가능할 것이다. Although in the above and shown with respect to a preferred embodiment of the present invention also describes, the present invention is conventional in the art to which this invention pertains without departing from the subject matter of the present invention is not limited to the embodiment described above, it claimed in the following claims those with knowledge anyone will be a variety of changes implemented.

Claims (3)

  1. 표면에 본드 패드가 배치된 반도체 칩; The semiconductor chip has bonding pads disposed on a surface;
    상기 반도체 칩의 표면에, 상기 본딩 패드가 노출되도록 도포된 절연층; An insulating layer applied to the bonding pad is exposed on the surface of the semiconductor chip;
    상기 절연층상에 형성된 더미 패드; Dummy pad formed on the insulating layer;
    상기 더미 패드와 본드 패드를 전기적으로 연결하는 금속 와이어; A metal wire electrically connecting the dummy pad and the bond pad;
    상기 금속 와이어에 도금되어 금속 와이어를 피복하는 금속막; A metal film which is coated on the metal wire covered with a metal wire; And
    상기 금속 와이어의 일부분이 노출되도록, 상기 절연층 상부를 몰딩하는 봉지제를 포함하는 것을 특징으로 하는 웨이퍼 레벨 패키지. Such that the exposed portion of the metal wire, a wafer-level package comprises a sealing material for molding the upper insulating layer.
  2. 제 1 항에 있어서, 상기 노출된 금속 와이어 부분에 접합 보조층이 형성되고, 상기 접합 보조층상에 솔더 볼이 마운트된 것을 특징으로 하는 웨이퍼 레벨 패키지. The method of claim 1 wherein the secondary layer is bonded to the exposed metal wire part is formed, and a wafer, characterized in that the bonding auxiliary layer a solder ball is mounted level package.
  3. 표면에 본드 패드가 배치된 반도체 칩; The semiconductor chip has bonding pads disposed on a surface;
    상기 반도체 칩 표면에 접착되고, 표면에는 더미 패드가 형성된 접착제; Is bonded to the semiconductor chip surface, the surface of the adhesive pad formed piles;
    상기 더미 패드와 본드 패드를 전기적으로 연결하는 금속 와이어; A metal wire electrically connecting the dummy pad and the bond pad;
    상기 금속 와이어에 도금되어, 상기 금속 와이어를 피복하는 금속막; Is coated on the metal wire, the metal film covering the metal wire; And
    상기 금속 와이어의 일부분이 노출되도록, 상기 절연층 상부를 몰딩하는 봉지제를 포함하는 것을 특징으로 하는 웨이퍼 레벨 패키지. Such that the exposed portion of the metal wire, a wafer-level package comprises a sealing material for molding the upper insulating layer.
KR1019990064391A 1999-12-29 1999-12-29 Wafer level package KR20010061849A (en)

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