CN101131982A - Non-pin packaging structure of semiconductor element and packaging technology thereof - Google Patents
Non-pin packaging structure of semiconductor element and packaging technology thereof Download PDFInfo
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- CN101131982A CN101131982A CNA2007101321796A CN200710132179A CN101131982A CN 101131982 A CN101131982 A CN 101131982A CN A2007101321796 A CNA2007101321796 A CN A2007101321796A CN 200710132179 A CN200710132179 A CN 200710132179A CN 101131982 A CN101131982 A CN 101131982A
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- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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Abstract
The present invention relates to a semiconductor non-pin-packaging structure and its packaging process. The said structure includes chip substrate (1), wire-bonded pins substrate (2), chip (3), metal wire (4) and plastic package (5). Bottoms of the said chip substrate (1) and wire-bonded pins substrate (2) protrude bottom of the plastic package (5). The chip substrate is consisted of two parts, of which one is set in the plastic package, and the other is set outside the plastic package. The part in plastic package is consisted of several independent metal protrusions (1.1) which extend to outside of the plastic package, and all connect onto a complete metal sheet (1.2). The outer metal sheet (1.2) shows a pallet pattern to support the several independent metal protrusions (1.1) in the plastic package, and protrudes from the bottom of the plastic package (5), thus it consists another part of the chip substrate; the said chip is set on the metal protrusions of chip substrate. The present invention will not lead to layered and unattaching of the chip substrate, can be applied in high power, high heat-distributed productions.
Description
Technical field
The present invention relates to a kind of non-pin packaging structure of semiconductor element and packaging technology thereof and belong to the semiconductor packaging field.
Background technology
Traditional exposed non-pin packaging structure of semiconductor device chip carrying base adopts full wafer/single piece of metal sheet as chip bearing base (as Fig. 1) when design
This chip bearing understructure has the following disadvantages:
1, easily produce in the encapsulating products a large amount of stress-retained and then influence that product reliability---the interior material of packaging body can be divided into three major types: metal (copper, iron, nickel etc.), chip (silicon material) and plastic packaging material.From the thermal coefficient of expansion angle of material, chip is close with the plastic packaging material coefficient of thermal expansion, and the coefficient of thermal expansion of metal then is higher than chip and plastic packaging material far away.This species diversity can be aggravated stress-retained in the plastic-sealed body under hot environment.And the shared ratio of metal is high more, and required deformation quantity is just big more, and large stretch of metal derby can't produce bigger deformation and then accumulate more stress because of being limited by plastic-sealed body, and the suffered stress of chip surface is also just big more, finally causes product layering or disabler.The chip bearing base that large stretch of metal constitutes has then increased the metal ratio in the packaging body just.
2, the chip bearing base comes off easily, and then causes product failure---this full wafer and the metal structure and the faying face between the plastic packaging material of bulk are limited, thereby structural strength is lower; Product is carrying out the surface when mounting repeatedly, and the chip bearing base of monoblock is easy to cause the chip bearing base to come off because of the stressed plastic-sealed body that is pulled out.
3, the flexibility of chip bearing base is lower, be difficult to be applicable to the demand of the big or small chip of multiple difference---the chip bearing base fixed size of this bulk, the design that runs into relatively long, broad or just must change framework during near the chip of chip bearing base size cooperates, and expends cost and time.
Summary of the invention
The objective of the invention is to overcome above-mentioned deficiency, provide a kind of encapsulating products can not produce non-pin packaging structure of semiconductor element and packaging technology thereof that layering, chip bearing base can not come off, go for high-power, high heat radiation product demand.
The object of the present invention is achieved like this: a kind of non-pin packaging structure of semiconductor element, comprise chip bearing base, routing pin carrying base, chip, metal wire and plastic-sealed body, described chip bearing base, routing pin carrying base, chip and metal wire are coated by plastic-sealed body, and the bottom that makes chip bearing base and routing pin carrying base protrudes from the bottom of plastic-sealed body, it is characterized in that:
Described chip bearing base is made up of two parts, a part places in the plastic-sealed body, another part places outside the plastic-sealed body, place the part in the plastic-sealed body to constitute by a plurality of independently metal couplings, a plurality of independently metal couplings then are connected on the complete sheet metal of a slice when extending to the plastic-sealed body outside jointly, the sheet metal that exposes is the hypocrateriform carrying lives a plurality of independently metal couplings in the plastic-sealed body and protrudes from the plastic-sealed body bottom, constitutes another part of chip bearing base;
Described chip places on the metal coupling of chip bearing base.
Non-pin packaging structure of semiconductor element of the present invention, the surface of the described chip bearing base that protrudes from plastic-sealed body bottom and the surface of routing pin carrying base are all coated by metal level I.
Non-pin packaging structure of semiconductor element of the present invention, the front of described routing pin carrying base is covered with metal level II.
Non-pin packaging structure of semiconductor element of the present invention, in a plurality of independently metal couplings of described chip bearing base, partly or entirely the top of metal coupling is covered with metal level III.
Semiconductor device non-pin packing technology of the present invention may further comprise the steps:
---get a slice metal substrate,
---metal substrate just, the back of the body two sides stick mask,
---the part mask in metal substrate front is got rid of,
---the zone of removing mask in the last process is etched partially,, begins to take shape the routing pin carrying base of convex dot shape and a plurality of independently metal couplings of chip bearing base simultaneously relatively at the positive partially etching area that forms depression of metal substrate,
---remove the positive remaining mask of metal substrate and the mask at the metal substrate back side,
---be covered with mask at the metal substrate all surface of removing mask,
---remove the mask at the part or all of metal coupling top of routing pin carrying base top and chip bearing base, carry out the zone of metal cladding in order to expose follow-up need,
---in last process, remove the part metal cladding of mask,
---remove all remaining on metal substrate masks,
---on a plurality of independently metal couplings of chip bearing base, carry out the implantation of chip,
---the semi-finished product of finishing chip implantation operation are played the metal wire operation,
---will be the routing semi-finished product front of finishing seal the plastic-sealed body operation, and carry out curing operation after the plastic encapsulation,
---stick mask once more at the metal substrate back side,
---remove the part mask at the metal substrate back side, keep the mask of chip bearing base back surface and routing pin carrying base back surface, exposing the required zone of subsequent etch,
---at the metal substrate back side etching is carried out in the zone that is not covered by mask, thereby made the chip bearing base back surface become the full wafer metal to protrude from the plastic-sealed body bottom, routing pin carrying base back surface also protrudes from the plastic-sealed body bottom simultaneously,
---the mask of removing metal substrate back side remainder is beneficial to follow-up process operation,
---the surface at chip bearing base that protrudes the plastic-sealed body outside and routing pin carrying base plates metal level,
---glued membrane is sticked in the plastic-sealed body front,
---the semi-finished product that stick glued membrane are carried out cutting operation, make script independent with more than of the chips that array formula aggregate mode connects together.
Semiconductor device of the present invention does not have the pin packaging body to be compared with traditional exposed non-pin packaging structure of semiconductor device chip carrying base, and the present invention has following advantage:
1, discharge the stress in the packaging body better, improve reliability of products---the chip bearing base portion in the packaging body is a plurality of independently metal couplings, with respect to the big metal derby of traditional monoblock, be to have reduced the metal proportion on the one hand, the required deformation quantity of single on the other hand little metal derby is little, greatly reduce the restriction of plastic packaging material to its trickle deformation, this trickle deformation of single little metal derby then can better discharge packaging body internal cause unlike material and the stress that produces, reduce the suffered stress of chip surface, when guaranteeing properties of product, also avoided the risk of layering.
2, a plurality of independently metal couplings of the chip bearing base in the packaging body and the bonded area between the plastic packaging material increase greatly, and adhesion also promotes thereupon, can not produce the problem that the chip bearing base drops out.
3, the flexibility height of chip bearing base, even in the face of larger-size chip, the full wafer metal of chip bearing base exterior also can be brought into play the problem that elargol exposes in the pallet effect mode potting process, and then has increased the property applied flexibly of framework, has saved development cost.
4, to have increased metallic surface long-pending for the chip bearing base that constitutes of this a plurality of independent metal derby, and then improved the area of dissipation of product, can satisfy the demand of high-power, high heat radiation product.
Description of drawings
Fig. 1 is traditional exposed non-pin packaging structure mode one schematic diagram of semiconductor device chip carrying base.
Fig. 2 is a non-pin packaging structure of semiconductor element sectional schematic diagram of the present invention.
Fig. 3～21 do not have pin encapsulation carving before plating process chart for semiconductor device of the present invention.
Fig. 5-1～10-1 does not afterwards carve the part process chart for semiconductor device of the present invention has first plating of pin encapsulation.
Among the figure: chip bearing base 1, routing pin carrying base 2, chip 3, metal wire 4 and plastic-sealed body 5, metal level I6, metal level II7, metal level III8, metal substrate 9, mask 10, mask 11, mask 12.
Embodiment
Referring to Fig. 2, the present invention relates to a kind of non-pin packaging structure of semiconductor element, it mainly is made up of chip bearing base 1, routing pin carrying base 2, chip 3, metal wire 4 and plastic-sealed body 5.Described routing pin carrying base 2 places chip bearing base 1 periphery, chip 3 places chip bearing base 1 top, metal wire 4 is connected between chip 3 and chip bearing base 1 and the routing pin carrying base 2, or metal wire 4 is connected between chip 3 and the routing pin carrying base 2, plastic-sealed body 5 is coated on outside chip bearing base 1, the carrying of routing pin base 2, chip 3 and the metal wire 4, and makes chip bearing base 1 and routing pin carrying base 2 bottoms protrude from plastic-sealed body 5 bottoms.
Described chip bearing base 1 is made up of two parts, a part places in the plastic-sealed body 5, another part places outside the plastic-sealed body 5, place the part in the plastic-sealed body 5 to constitute by a plurality of independently metal couplings 1.1, a plurality of independently metal couplings 1.1 then are connected on the complete sheet metal of a slice 1.2 when extending to plastic-sealed body 5 outsides jointly, the sheet metal 1.2 that exposes is the hypocrateriform carrying lives a plurality of independently metal couplings 1.1 in the plastic-sealed body and protrudes from plastic-sealed body 5 bottoms, constitutes another part of chip bearing base 1.
Described chip 3 places on the metal coupling 1.1 of chip bearing base.
The surface of the surface of the chip bearing base 1 of described protrusion plastic-sealed body 5 bottoms and routing pin carrying base 2 is all coated by metal level I6.
Non-pin packaging structure of semiconductor element of the present invention, the front of described routing pin carrying base 2 is covered with metal level II7.
Non-pin packaging structure of semiconductor element of the present invention, in a plurality of independently metal couplings 1.1 of described chip bearing base, partly or entirely the top of metal coupling 1.1 is covered with metal level III8.
Process implementing example 1: carving before plating
Semiconductor device of the present invention does not have the packaging technology of pin encapsulation, may further comprise the steps:
---get a slice metal substrate 9, as Fig. 3;
---metal substrate 9 just, the back of the body two sides stick mask 10 to protect follow-up etch process operation, as Fig. 4;
---the part mask 10 in metal substrate 9 fronts is got rid of, and purpose is to expose the zone that preparation etches partially on the metal substrate, as Fig. 5;
---the zone of removing mask in the last process is etched partially, at the metal substrate 9 positive partially etching areas 9.1 that form depression, begin to take shape simultaneously the routing pin carrying base 2 of convex dot shape and a plurality of independently metal couplings 1.1 of chip bearing base relatively, as Fig. 6;
---remove the positive remaining mask 10 of metal substrate and the mask 10 at the metal substrate back side, as Fig. 7;
---be covered with mask 11 at the metal substrate all surface of removing mask, as Fig. 8;
---remove the mask 11 at top of the part or all of metal coupling 1.1 of routing pin carrying base 2 tops and chip bearing base, carry out the zone of metal cladding in order to expose follow-up need, as Fig. 9;
---in last process, remove the part metal cladding II7 and the metal level III8 of mask 11, as Figure 10;
---remove all remaining on metal substrate masks 11, as Figure 11;
---behind some glue on a plurality of independently metal couplings 1.1 of chip bearing base, carry out the implantation of chip 3, as Figure 12,13;
---implant the semi-finished product of operation and play metal wire 4 operations finishing chip, make between chip and the routing pin carrying base 2 or chip and routing pin carry the more than 1 individual independently interconnected between the metal coupling 1.1 of base 2 and chip bearing base, as Figure 14;
---will be the routing semi-finished product front of finishing seal plastic-sealed body 5 operations, and carry out curing operation after the plastic encapsulation according to the characteristic of plastic packaging material, with protection metal wire, chip and in the safety of pin, as Figure 15;
---stick mask 12 once more at the metal substrate back side, as Figure 16;
---remove the part mask at the metal substrate back side, keep the mask of chip bearing base back surface and routing pin carrying base back surface, to expose the required zone of subsequent etch, as Figure 17;
---at the metal substrate back side etching is carried out in the zone that is not covered by mask, thereby made the chip bearing base back surface become the full wafer metal to protrude from the plastic-sealed body bottom, routing pin carrying base back surface also protrudes from the plastic-sealed body bottom simultaneously, as Figure 18;
---the mask of removing metal substrate back side remainder is beneficial to follow-up process operation, as Figure 19;
---the surface at chip bearing base that protrudes the plastic-sealed body outside and routing pin carrying base plates metal level I6, as Figure 20;
---glued membrane is sticked in the plastic-sealed body front, prepares to carry out follow-up plastic-sealed body cutting operation,
---the semi-finished product that stick glued membrane are carried out cutting operation, make script independent, as Figure 21 with more than of the chips that array formula aggregate mode connects together;
---the product utilization that will finish cutting picks and places conversion equipment is not had pin packaging body sucking-off glued membrane one by one with single semiconductor device.
Process implementing example 2: plate afterwards earlier and carve
The elder generation that semiconductor device of the present invention does not have a pin encapsulation plates and afterwards carves packaging technology, may further comprise the steps:
---get a slice metal substrate 9, as Fig. 3;
---metal substrate 9 just, the back of the body two sides stick mask 10 to protect follow-up etch process operation, as Fig. 4;
---the part mask 10 in metal substrate 9 fronts is got rid of, and purpose is to expose the zone of preparing to carry out metal cladding on the metal substrate, as Fig. 5-1;
---the metal cladding operation is carried out in the zone of removing mask in the last process, formed metal level II7 and metal level III8 respectively in metal substrate 9 fronts, as Fig. 6-1;
---remove the positive remaining mask 10 of metal substrate and the mask 10 at the metal substrate back side, as Fig. 7-1;
---be covered with mask 11 at the metal substrate of removing mask and all surface of metal substrate front metal layer, as Fig. 8-1;
---remove metal substrate front portion mask and be beneficial to the subsequent technique operation; As Fig. 9-1;
---the zone of removing mask in the last process is etched partially, at the metal substrate 9 positive partially etching areas 9.1 that form depression, begin to take shape simultaneously the routing pin carrying base 2 of convex dot shape and a plurality of independently metal couplings 1.1 of chip bearing base relatively, and the top that makes metal level II7 and metal level III8 place the routing pin to carry base 2 and chip bearing base metal coupling 1.1 respectively is as Figure 10-1;
Remaining part gets final product with process implementing example 1.
Claims (7)
1. non-pin packaging structure of semiconductor element, comprise chip bearing base (1), routing pin carrying base (2), chip (3), metal wire (4) and plastic-sealed body (5), described chip bearing base (1), routing pin carrying base (2), chip (3) and metal wire (4) are coated by plastic-sealed body (5), and the bottom that makes chip bearing base (1) and routing pin carrying base (2) protrudes from the bottom of plastic-sealed body (5), it is characterized in that:
Described chip bearing base (1) is made up of two parts, a part places in the plastic-sealed body (5), another part places outside the plastic-sealed body (5), place the part in the plastic-sealed body (5) to constitute by a plurality of independently metal couplings (1.1), a plurality of independently metal couplings (1.1) then are connected on the complete sheet metal of a slice (1.2) when extending to plastic-sealed body (5) outside jointly, the sheet metal that exposes (1.2) is the hypocrateriform carrying lives a plurality of independently metal couplings (1.1) in the plastic-sealed body and protrudes from plastic-sealed body (5) bottom, constitutes another part of chip bearing base (1);
Described chip (3) places on the metal coupling (1.1) of chip bearing base.
2. a kind of non-pin packaging structure of semiconductor element according to claim 1 is characterized in that: the surface of the described chip bearing base (1) that protrudes from plastic-sealed body (5) bottom and the surface of routing pin carrying base (2) are all coated by metal level I (6).
3. a kind of non-pin packaging structure of semiconductor element according to claim 1 and 2 is characterized in that: the front of described routing pin carrying base (2) is covered with metal level II (7).
4. a kind of non-pin packaging structure of semiconductor element according to claim 1 and 2 is characterized in that: in a plurality of independently metal couplings (1.1) of described chip bearing base, partly or entirely the top of metal coupling (1.1) is covered with metal level III (8).
5. a kind of non-pin packaging structure of semiconductor element according to claim 3 is characterized in that: in a plurality of independently metal couplings (1.1) of described chip bearing base, partly or entirely the top of metal coupling (1.1) is covered with metal level III (8).
6. semiconductor device non-pin packing technology as claimed in claim 1, it is characterized in that: described technology may further comprise the steps:
---get a slice metal substrate,
---metal substrate just, the back of the body two sides stick mask,
---the part mask in metal substrate front is got rid of,
---the zone of removing mask in the last process is etched partially,, begins to take shape the routing pin carrying base of convex dot shape and a plurality of independently metal couplings of chip bearing base simultaneously relatively at the positive partially etching area that forms depression of metal substrate,
---remove the positive remaining mask of metal substrate and the mask at the metal substrate back side,
---be covered with mask at the metal substrate all surface of removing mask,
---remove the mask at the part or all of metal coupling top of routing pin carrying base top and chip bearing base, carry out the zone of metal cladding in order to expose follow-up need,
---in last process, remove the part metal cladding of mask,
---remove all remaining on metal substrate masks,
---on a plurality of independently metal couplings of chip bearing base, carry out the implantation of chip,
---the semi-finished product of finishing chip implantation operation are played the metal wire operation,
---will be the routing semi-finished product front of finishing seal the plastic-sealed body operation, and carry out curing operation after the plastic encapsulation,
---stick mask once more at the metal substrate back side,
---remove the part mask at the metal substrate back side, keep the mask of chip bearing base back surface and routing pin carrying base back surface, exposing the required zone of subsequent etch,
---at the metal substrate back side etching is carried out in the zone that is not covered by mask, thereby made the chip bearing base back surface become the full wafer metal to protrude from the plastic-sealed body bottom, routing pin carrying base back surface also protrudes from the plastic-sealed body bottom simultaneously,
---the mask of removing metal substrate back side remainder is beneficial to follow-up process operation,
---the surface at chip bearing base that protrudes the plastic-sealed body outside and routing pin carrying base plates metal level,
---glued membrane is sticked in the plastic-sealed body front,
---the semi-finished product that stick glued membrane are carried out cutting operation, make script independent with more than of the chips that array formula aggregate mode connects together.
7. semiconductor device non-pin packing technology as claimed in claim 1, it is characterized in that: described technology may further comprise the steps:
---get a slice metal substrate,
---metal substrate just, the back of the body two sides stick mask,
---the part mask in metal substrate front is got rid of,
---the metal cladding operation is carried out in the zone of removing mask in the last process, is formed metal level II and metal level III in the metal substrate front respectively,
---remove the positive remaining mask of metal substrate and the mask at the metal substrate back side,
---be covered with mask at the metal substrate of removing mask and all surface of metal substrate front metal layer,
---remove metal substrate front portion mask and be beneficial to the subsequent technique operation,
---the zone of removing mask in the last process is etched partially, at the positive partially etching area that forms depression of metal substrate, begin to take shape simultaneously the routing pin carrying base of convex dot shape and a plurality of independently metal couplings of chip bearing base relatively, and make metal level II and metal level III place the top of routing pin carrying base and chip bearing base metal coupling respectively
---remove all remaining on metal substrate masks,
---in last process, remove the part metal cladding of mask,
---remove all remaining on metal substrate masks,
---on a plurality of independently metal couplings of chip bearing base, carry out the implantation of chip,
---the semi-finished product of finishing chip implantation operation are played the metal wire operation,
---will be the routing semi-finished product front of finishing seal the plastic-sealed body operation, and carry out curing operation after the plastic encapsulation,
---stick mask once more at the metal substrate back side,
---remove the part mask at the metal substrate back side, keep the mask of chip bearing base back surface and routing pin carrying base back surface, exposing the required zone of subsequent etch,
---at the metal substrate back side etching is carried out in the zone that is not covered by mask, thereby made the chip bearing base back surface become the full wafer metal to protrude from the plastic-sealed body bottom, routing pin carrying base back surface also protrudes from the plastic-sealed body bottom simultaneously,
---the mask of removing metal substrate back side remainder is beneficial to follow-up process operation,
---the surface at chip bearing base that protrudes the plastic-sealed body outside and routing pin carrying base plates metal level,
---glued membrane is sticked in the plastic-sealed body front,
---the semi-finished product that stick glued membrane are carried out cutting operation, make script independent with more than of the chips that array formula aggregate mode connects together.
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