CN106531647B - A kind of encapsulating structure being fanned out to cake core and its packaging method - Google Patents
A kind of encapsulating structure being fanned out to cake core and its packaging method Download PDFInfo
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- CN106531647B CN106531647B CN201611248036.7A CN201611248036A CN106531647B CN 106531647 B CN106531647 B CN 106531647B CN 201611248036 A CN201611248036 A CN 201611248036A CN 106531647 B CN106531647 B CN 106531647B
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 182
- 238000000034 method Methods 0.000 title claims abstract description 42
- 239000004033 plastic Substances 0.000 claims abstract description 141
- 239000000758 substrate Substances 0.000 claims abstract description 72
- 239000000463 material Substances 0.000 claims abstract description 23
- 238000005538 encapsulation Methods 0.000 claims abstract description 8
- 239000012528 membrane Substances 0.000 claims description 19
- 238000007789 sealing Methods 0.000 claims 1
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- 238000005516 engineering process Methods 0.000 abstract description 2
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- 229910052759 nickel Inorganic materials 0.000 description 2
- 239000011368 organic material Substances 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
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- 238000000151 deposition Methods 0.000 description 1
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- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Packaging Frangible Articles (AREA)
- Packages (AREA)
Abstract
The embodiment of the invention discloses a kind of encapsulating structure for being fanned out to cake core and its packaging methods, are related to chip encapsulation technology field, wherein the packaging method for being fanned out to cake core includes: to provide a carrier substrate, and attach chip on the carrier substrate；Plastic packaging layer is formed far from the side of the carrier substrate in the chip, the plastic packaging layer coats the chip, and the plastic packaging layer includes at least two bulge-structures.By adopting the above technical scheme, it include at least two bulge-structures on plastic packaging layer, the bulge-structure is used to form that partial region is thicker, partial region is relatively thin, the different plastic packaging layer of thickness distribution, guarantee to reduce the volume of plastic packaging layer, and then reduce the deflection of plastic packaging layer, mitigate between plastic packaging layer and chip due to thermal expansion coefficient it is different caused by warpage issues, the use of encapsulating material is reduced simultaneously, saves packaging cost.
Description
Technical field
The present embodiments relate to chip encapsulation technology field more particularly to a kind of encapsulating structure for being fanned out to cake core and its
Packaging method.
Background technique
Fan-out-type wafer-level packaging (Fan-Out Wafer Level Packaging, FOWLP) is a kind of wafer level processing
Embedded encapsulation and one of the main Advanced Packaging that I/O number is more, integrated flexibility is good, be presently considered to be most suitable for height
It is required that movement/wireless market, and to it is other concern high-performance and small size markets, it may have very strong attraction.
In the prior art, the general encapsulation for completing to be fanned out to cake core using plastic package process, but the fan of current plastic package process
Out type be encapsulated in warpage control aspect be it is very difficult, this is because the thermal expansion of the thermal expansion coefficient and chip of capsulation material
Coefficient difference is larger, causes plastic packaging layer and the thermal expansion coefficient of chip layer to mismatch and generate local thermal stress, so that packaging part
Generate warpage.Such warpage not only increases plastic packaging follow-up process difficulty, but also it is tight to be easy to produce chip and encapsulation crackle etc.
The component failure problem of weight.
Summary of the invention
In view of this, the embodiment of the present invention provides a kind of encapsulating structure for being fanned out to cake core and its packaging method, to solve
Packaging part is easy the technical issues of warpage in the prior art.
In a first aspect, the embodiment of the invention provides a kind of packaging methods for being fanned out to cake core, comprising:
One carrier substrate is provided, and attaches chip on the carrier substrate；
Plastic packaging layer is formed far from the side of the carrier substrate in the chip, the plastic packaging layer coats the chip, and
The plastic packaging layer includes at least two bulge-structures.
Optionally, the thickness of the chip and the vertical range of the chip upper surface to the bulge-structure upper surface
Ratio range is 0.2-5.
Optionally, after the chip forms plastic packaging layer far from the side of the carrier substrate, further includes:
Side on the plastic packaging layer far from the carrier substrate forms connection circuit, and the connection circuit passes through described
Opening on plastic packaging layer is electrically connected with the chip；
It removes the carrier substrate and obtains chip-packaging structure, and cut the chip-packaging structure and obtain single chip envelope
Assembling structure.
Optionally, the connection circuit is attached most importance to wiring layer, far from the side shape of the carrier substrate on the plastic packaging layer
Before connection circuit, further includes:
The bulge-structure for removing the plastic packaging layer obtains the smooth plastic packaging layer in upper surface.
Optionally, plastic packaging layer is formed far from the side of the carrier substrate in the chip, comprising:
Plastic packaging layer is formed far from the side of the carrier substrate in the chip using plastic packaging membrane cavity.
Optionally, plastic packaging layer is formed far from the side of the carrier substrate in the chip using plastic packaging membrane cavity, comprising:
Capsulation material is injected into the plastic packaging membrane cavity and forms plastic packaging layer, includes at least two grooves in the plastic packaging membrane cavity
Structure, the capsulation material are correspondingly formed the bulge-structure of the plastic packaging layer in the groove structure.
Optionally, at least two bulge-structures are arranged in a crossed manner.
Optionally, when the plastic packaging layer includes a plurality of bulge-structure, the shape of the bulge-structure is " well " shape.
Optionally, each chip is correspondingly arranged at least one bulge-structure.
Second aspect, the embodiment of the invention also provides a kind of encapsulating structures for being fanned out to cake core, using first aspect institute
The packaging method for being fanned out to cake core stated encapsulates to obtain.
The encapsulating structure provided in an embodiment of the present invention for being fanned out to cake core and its packaging method, by providing a carrier base
Plate, and chip is attached on carrier substrate, plastic packaging layer is formed far from the side of carrier substrate in chip, plastic packaging layer coats the core
Piece, and plastic packaging layer includes at least two bulge-structures.It by adopting the above technical scheme, include at least two protrusion knots on plastic packaging layer
Structure, the bulge-structure are used to form that partial region is thicker, partial region is relatively thin, and the different plastic packaging layer of thickness distribution guarantees to subtract
The volume of small plastic packaging layer, and then reduce the deflection of plastic packaging layer, mitigate between plastic packaging layer and chip since thermal expansion coefficient is different
Caused warpage issues, the use of encapsulating material can also be reduced by being formed simultaneously the different plastic packaging layer of thickness distribution, save encapsulation
Cost.
Detailed description of the invention
In order to more clearly illustrate the technical scheme of the exemplary embodiment of the present invention, below to required in description embodiment
The attached drawing to be used does a simple introduction.Obviously, the attached drawing introduced is present invention a part of the embodiment to be described
Attached drawing, rather than whole attached drawings without creative efforts, may be used also for those of ordinary skill in the art
To obtain other attached drawings according to these attached drawings.
Fig. 1 is a kind of flow diagram for packaging method for being fanned out to cake core that the embodiment of the present invention one provides；
Fig. 2 a is a kind of schematic top plan view attached after chip on carrier substrate that the embodiment of the present invention one provides；
Fig. 2 b is a kind of the schematic diagram of the section structure attached after chip on carrier substrate that the embodiment of the present invention one provides；
Fig. 3 a is the schematic top plan view after a kind of formation plastic packaging layer that the embodiment of the present invention one provides；
Fig. 3 b is the schematic diagram of the section structure after a kind of formation plastic packaging layer that the embodiment of the present invention one provides；
Fig. 4 is a kind of flow diagram of packaging method for being fanned out to cake core provided by Embodiment 2 of the present invention；
A kind of Fig. 5 a removal bulge-structure provided by Embodiment 2 of the present invention forms the vertical view of the smooth plastic packaging layer in upper surface
Schematic diagram；
A kind of Fig. 5 b removal bulge-structure provided by Embodiment 2 of the present invention forms the section of the smooth plastic packaging layer in upper surface
Structural schematic diagram；
A kind of Fig. 6 the schematic diagram of the section structure that connection circuit is formed on plastic packaging layer provided by Embodiment 2 of the present invention；
A kind of Fig. 7 the schematic diagram of the section structure that connection soldered ball is formed on connection circuit provided by Embodiment 2 of the present invention；
A kind of Fig. 8 removing carrier substrate provided by Embodiment 2 of the present invention, obtains the schematic diagram of encapsulating structure；
A kind of Fig. 9 schematic diagram for obtaining single encapsulating structure provided by Embodiment 2 of the present invention.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, below with reference to attached in the embodiment of the present invention
Figure, by specific embodiment, is fully described by technical solution of the present invention.Obviously, described embodiment is of the invention
A part of the embodiment, instead of all the embodiments, based on the embodiment of the present invention, those of ordinary skill in the art are not doing
The every other embodiment obtained under the premise of creative work out, falls within the scope of protection of the present invention.
Embodiment one
Fig. 1 is a kind of flow diagram for packaging method for being fanned out to cake core that the embodiment of the present invention one provides, the present invention
Embodiment provides a kind of packaging method for being fanned out to cake core.Referring to Fig. 1, the embodiment of the present invention one provide be fanned out to cake core
Packaging method may comprise steps of:
S110, a carrier substrate is provided, and attaches chip on the carrier substrate.
Illustratively, Fig. 2 a is that a kind of vertical view on carrier substrate after attaching chip that the embodiment of the present invention one provides is shown
It is intended to, as shown in Figure 2 a, several chips 20 is formed on carrier substrate 10, chip 20 can be arranged in the form of matrix arrangement
On carrier substrate 10.
Optionally, carrier substrate 10 can be full wafer wafer substrate, such as sapphire substrate or silicon substrate substrate, may be used also
Think glass substrate or other substrates, the embodiment of the present invention is not defined the concrete type of carrier substrate 10.Optionally,
The shape of carrier substrate 10 can for circle, can also be other shapes, such as carrier substrate 10 shape can also for rectangle,
Triangle or other shapes are not defined the shape of carrier substrate 10 equally in the embodiment of the present invention, are only carried with circle
It is explained for structure base board.
Fig. 2 b is a kind of the schematic diagram of the section structure attached after chip on carrier substrate that the embodiment of the present invention one provides,
With reference to Fig. 2 b, chip 20 may include front and with the back side that is correspondingly arranged of front, the front of chip 20 could be formed with electricity
Pole structure (not shown), the electrode structure is for connecting chip 20 and other external circuits.Chip 20 is attached to load
When structure base board 10, towards the direction of carrier substrate 10, front is directed away from the direction of carrier substrate 10 at the back side of chip 20, exposes
The front of chip 20 and the electrode structure on front.
Optionally, it can be to adopt and chip 20 be attached on carrier substrate 10 in the method for paste, so just need carrying
One layer of adhesive layer (not shown) is coated on structure base board 10 in advance, chip 20 is pasted by carrier substrate by the adhesive layer
On 10.Optionally, adhesive layer coating can be used spin coating, spraying, rolling, printing, non-rotating coating, hot pressing, vacuum pressing-combining with
And modes, the adhesive layer such as pressure fitting can be organic material or composite material.
S120, plastic packaging layer is formed far from the side of the carrier substrate in the chip, the plastic packaging layer coats the core
Piece, and the plastic packaging layer includes at least two bulge-structures.
Illustratively, after the attaching that chip 20 is completed on carrier substrate 10, in chip 20 far from carrier substrate 10
It includes at least two bulge-structures 301 that side, which forms plastic packaging layer 30,30 coating chip 20 of plastic packaging layer, and plastic packaging layer 30,.Such as figure
Shown in 3a and Fig. 3 b, Fig. 3 a and Fig. 3 b are the schematic top plan view after a kind of formation plastic packaging layer that the embodiment of the present invention one provides respectively
And the schematic diagram of the section structure, as shown in Figure 3a, plastic packaging layer 30 includes a plurality of bulge-structure 301, is handed between a plurality of bulge-structure 301
, there is the position to intersect in fork setting, can guarantee to mould during plastic packaging in this way between bulge-structure 301 and bulge-structure 301
The proper flow of closure material will not be blocked and not circulated by a certain item or a few bulge-structures 301, avoid the generation in gap.
With continued reference to Fig. 3 a, optionally, a plurality of bulge-structure 301 can form the arrangement mode of " well " shape, guarantee capsulation material
Normal circulation.It is understood that bulge-structure 301 can be linear type, it can also be shaped form as shown in Figure 3a, also,
The terminal of every bulge-structure 301 can be in the marginal position of plastic packaging layer, can also be in any position of plastic packaging layer, a plurality of protrusion
Structure 301 can be arranged in " well " shape, can also be other arrangement modes, the embodiment of the present invention is not to bulge-structure 301
Shape, forming position, terminal location and arrangement mode be defined, Fig. 3 a only in one way for illustrate
It is bright.
As shown in Figure 3b, the thickness H1 of chip 20 can be vertical with 20 upper surface of chip to 301 upper surface of bulge-structure
Ratio range between distance H2 can be 0.2-5.Specifically, due to needing to form 30 pairs of chip 20 of plastic packaging layer on chip 20
It is protected, but since the thermal expansion coefficient of capsulation material and the thermal expansion coefficient of chip material are different, for example, capsulation material
Thermal expansion coefficient be 7.2 or so, and the thermal expansion coefficient of chip material is only 2.3 or so, the thermal expansion coefficient of capsulation material
Thermal expansion coefficient mismatch problem with chip material is than more serious, therefore when temperature changes, the deformation of plastic packaging layer 30
Amount or change in displacement with the deformation quantity of chip 20 or thermal stress differ larger, cause plastic packaging layer 30 that mistake occurs with chip 20
The phenomenon that position, warpage.Inventor simulates by a large amount of experimental data, and discovery is as the thickness H1 of chip 20 and on chip 20
For ratio range between the thickness H2 of the plastic packaging layer 30 of side in a certain range, warpage is smaller, for example, the thickness H1 of chip 20 can
The ratio range between thickness H2 to be located at the plastic packaging layer 30 of 20 top of chip can be 0.2-5, therefore core can be set
The ratio range of the thickness H2 of the thickness H1 and plastic packaging layer 30 above chip of piece 20 can be 0.2-5.Further, work as setting
When ratio range between the thickness H2 of the flood plastic packaging layer 30 of 20 top thickness H1 and chip of chip 20 is all 0.2-5, core
The volume of the plastic packaging layer 30 of 20 top of piece is larger, equally can cause plastic packaging layer 30 that biggish deformation quantity occurs when temperature changes
And the 20 biggish residual stress in top of chip, therefore, it includes multiple bulge-structures 301 that plastic packaging layer 30, which can be set, is set simultaneously
The thickness H1 for setting chip 20 can ratio model between the vertical range H2 of 20 upper surface of chip to 301 upper surface of bulge-structure
Enclosing can be 0.2-5, it is to be appreciated that the vertical range H2 and chip 20 of 20 upper surface of chip to 301 upper surface of bulge-structure
The thickness H2 meaning of the plastic packaging layer 30 of top is identical.The setting of bulge-structure 301 substantially reduces the plastic packaging layer of 20 top of chip
30 volume, in this way, can both guarantee that the thickness H1 of chip 20 is identical as the thickness H2 of plastic packaging layer 30 for being located at 20 top of chip,
It is also ensured that the small volume of the plastic packaging layer 30 of 20 top of chip, the deformation quantity of plastic packaging layer 30 is smaller when temperature changes,
Reduce the residual stress between plastic packaging layer 30 and chip 20.Optionally, the thickness of chip 20 can be 0.1-0.7mm, protrusion knot
The height of structure 301 can be 0.05-0.65mm.
Can with, with continued reference to Fig. 3 a and Fig. 3 b, each chip 20 corresponding at least one bulge-structure 301 can be set
It sets.Since chip 20 can be arranged in arrays on carrier substrate 10, a full line chip of arrangement in a row can at least
One bulge-structure 301 is correspondingly arranged, and a permutation chip 20 of same arrayed in columns can be right at least one bulge-structure 301
It should be arranged, therefore a chip 20 can at least correspond to a bulge-structure 301 in the row direction, and/or, in a column direction extremely
A bulge-structure 301 is corresponded to less, as shown in Figure 2 b.
To sum up, the packaging method provided in an embodiment of the present invention for being fanned out to cake core, in side of the chip far from carrier substrate
Plastic packaging layer is formed, plastic packaging layer coating chip and plastic packaging layer include at least two bulge-structures, and being arranged includes at least two on plastic packaging layer
Bulge-structure, bulge-structure are used to form that partial region is thicker, partial region is relatively thin, and the different plastic packaging layer of thickness distribution is protected
Card reduces the volume of plastic packaging layer, and then reduces the deflection of plastic packaging layer, reduces between plastic packaging layer and chip due to thermal expansion coefficient
Warpage issues caused by difference, being formed simultaneously the different plastic packaging layer of thickness distribution can also be reduced using encapsulating material, save envelope
Dress up this.Further, it is simulated by lot of experimental data, on the thickness and chip upper surface to bulge-structure for rationally controlling chip
Ratio range between the vertical range on surface is 0.2-5, can utmostly reduce warpage, promotes chip package matter
Amount promotes product yield.
Optionally, forming plastic packaging layer 30 far from the side of carrier substrate 10 in chip 20 can be using plastic packaging membrane cavity in core
Piece 20 forms plastic packaging layer 30 far from the side of carrier substrate 10.
Illustratively, after the attaching that chip 20 is completed on carrier substrate 10, the carrier substrate of chip 20 will be pasted with
10 are placed in plastic packaging membrane cavity, and capsulation material is injected into plastic packaging membrane cavity, and capsulation material can be organic material, such as ABF, FR-
4, BT resin or polypropylene.It include at least two groove structures in the plastic packaging membrane cavity, the capsulation material is in the groove
The bulge-structure 301 of plastic packaging layer 30 is correspondingly formed in structure.It is understood that groove structure and plastic packaging layer in plastic packaging membrane cavity
Bulge-structure 301 it is corresponding, capsulation material, which is packed into groove structure, forms bulge-structure 301.Optionally, in plastic packaging membrane cavity
It can also include multiple membrane cavity protrusions, the part of not formed membrane cavity protrusion can be with the protrusion of plastic packaging layer 30 in such plastic packaging membrane cavity
Structure 301 is corresponding, and the part that capsulation material is packed into not formed membrane cavity protrusion in plastic packaging membrane cavity forms bulge-structure 301.
Embodiment two
Fig. 4 is a kind of flow diagram of packaging method for being fanned out to cake core provided by Embodiment 2 of the present invention, the present invention
Embodiment provides a kind of packaging method for being fanned out to cake core, and the embodiment of the present invention is using above-described embodiment as substrate, in above-mentioned implementation
It is optimized on the basis of example, referring to Fig. 4, the packaging method provided by Embodiment 2 of the present invention for being fanned out to cake core may include
Following steps:
S210, a carrier substrate is provided, and attaches chip on the carrier substrate.
S220, plastic packaging layer is formed far from the side of the carrier substrate in the chip, the plastic packaging layer coats the core
Piece, and the plastic packaging layer includes at least two bulge-structures.
The bulge-structure of S230, the removal plastic packaging layer, obtain the smooth plastic packaging layer in upper surface.
Illustratively, Fig. 5 a and Fig. 5 b is a kind of removal bulge-structure provided by Embodiment 2 of the present invention respectively, in formation
The top view and the schematic diagram of the section structure of the smooth plastic packaging layer in surface remove convex on plastic packaging layer 30 as shown in figure 5 a and 5b
Structure 301 is played, obtain the smooth not raised plastic packaging layer 30 in upper surface optionally can remove plastic packaging by way of milling
The bulge-structure 301 of layer 30 can also etch removal bulge-structure 301 by way of etching, and the embodiment of the present invention is not to such as
What, which removes bulge-structure 301, is defined, and need to only obtain the smooth plastic packaging layer 30 in upper surface.
S240, the side on the plastic packaging layer far from the carrier substrate form connection circuit, and the connection circuit is logical
The opening crossed on the plastic packaging layer is electrically connected with the chip.
Illustratively, Fig. 6 a kind of cross-section structure that connection circuit is formed on plastic packaging layer provided by Embodiment 2 of the present invention
Schematic diagram, as shown in fig. 6, forming connection circuit 40 on the smooth plastic packaging layer 30 in upper surface, connection circuit 40 can be weight cloth
Line layer, connection circuit 40 are electrically connected by the opening on plastic packaging layer 30 with chip 20, specifically with the electrode structure on chip 20
Electrical connection.Optionally, the side on plastic packaging layer 30 far from carrier substrate 10 forms connection circuit 40, and process includes a series of
The production of the techniques such as film deposition, plating, photoetching, development and etching, which is not described herein again.Connect the terminal warp on 40 one side of circuit
Opening on plastic packaging layer 30 is connected with the electrode structure on chip 20.Connect circuit 40 material can be metal material, as Al,
Au, Cr, Ni, Cu, Mo, Ti, Ta, Ni-Cr, W etc. and its alloy.
Further, the side on the plastic packaging layer far from the carrier substrate is formed after connection circuit, can be with
Include:
Connection soldered ball is formed far from the side of the plastic packaging layer in the connection circuit.
Illustratively, Fig. 7 a kind of section knot that connection soldered ball is formed on connection circuit provided by Embodiment 2 of the present invention
Structure schematic diagram, as shown in fig. 7, connection circuit 40 far from plastic packaging layer 30 side formed connection soldered ball 50, can by plating,
It prints, plant ball, put the techniques such as ball, then carry out reflux technique, reflux can be realized by heat transfer, convection current, radiation etc..Connection
The material of soldered ball 50 is mainly solder metal.Such as, Sn, Ag, Cu, Pb, Au, Ni, Zn, Mo, Ta, Bi, In, etc. and its alloy.
S250, the removing carrier substrate obtain chip-packaging structure, and cut the chip-packaging structure and obtain single
Chip-packaging structure.
Illustratively, Fig. 8 a kind of removing carrier substrate provided by Embodiment 2 of the present invention, obtains the signal of encapsulating structure
Figure, with reference to Fig. 8, removing carrier substrate 10 can be removed by the modes such as machinery, heating, chemistry, laser.Preferably, due to can
Chip 20 to be pasted on carrier substrate 10 by adhesive layer, therefore the mode that ultraviolet light heating or laser can be used is shone
Adhesive layer is penetrated, makes adhesive layer that aging, adhesive property decline, so as to relatively easily shell carrier substrate 10 occur
From.
Removing carrier substrate 10 obtains the encapsulating structure comprising multiple chips 20 later, to the encapsulation comprising multiple chips 20
Structure is cut, and obtains single chip encapsulating structure, as shown in Figure 9.Optionally, cutting tool can be used to comprising multiple
The encapsulating structure of chip 20 is cut, and obtains multiple single chip encapsulating structures, glass cutter can be used for example to packet
Encapsulating structure containing multiple chips 20 is cut, and single chip encapsulating structure is obtained, and the method for laser cutting also can be used
Encapsulating structure comprising multiple chips 20 is cut, single chip encapsulating structure is obtained, it is preferred that laser can be used and cut
The method cut obtains single chip encapsulating structure, is cut using laser to the encapsulating structure comprising multiple chips 20, can be with
Guarantee cutting precision.
The packaging method provided by Embodiment 2 of the present invention for being fanned out to cake core, forms during plastic packaging and contains at least two
The plastic packaging layer of bulge-structure removes bulge-structure before carrier substrate is removed, obtains the plastic packaging layer above chip than relatively thin core
Chip package, in carrier substrate removing, since the plastic packaging layer above chip is than relatively thin, even if can be generated in stripping process
Biggish temperature change, but since plastic packaging layer is than relatively thin, small volume, and then can reduce plastic packaging layer because temperature change generates
Deformation quantity, reduce as plastic packaging layer it is different from chip CTE caused by residual stress, avoid warping phenomenon from generating.
Optionally, the embodiment of the present invention also provides a kind of encapsulating structure for being fanned out to cake core, with continued reference to Fig. 9, the present invention
The encapsulating structure for being fanned out to cake core that embodiment provides may include: chip 20, plastic packaging layer 30, connection circuit 40 and connection weldering
Ball 50, the encapsulating structure provided in an embodiment of the present invention for being fanned out to cake core can be fanned out to using what any embodiment of the present invention provided
The packaging method of cake core encapsulates to obtain, the encapsulating structure provided in an embodiment of the present invention for being fanned out to cake core, and warping phenomenon is small.
Note that the above is only a better embodiment of the present invention and the applied technical principle.It will be appreciated by those skilled in the art that
The invention is not limited to the specific embodiments described herein, be able to carry out for a person skilled in the art it is various it is apparent variation,
It readjusts and substitutes without departing from protection scope of the present invention.Therefore, although being carried out by above embodiments to the present invention
It is described in further detail, but the present invention is not limited to the above embodiments only, without departing from the inventive concept, also
It may include more other equivalent embodiments, and the scope of the invention is determined by the scope of the appended claims.
Claims (10)
1. a kind of packaging method for being fanned out to cake core characterized by comprising
One carrier substrate is provided, and attaches chip on the carrier substrate；
Plastic packaging layer is formed far from the side of the carrier substrate in the chip, the plastic packaging layer coats the chip, and described
Plastic packaging layer includes at least two bulge-structures；
Side on the plastic packaging layer far from the carrier substrate forms connection circuit, and the connection circuit passes through the plastic packaging
Opening on layer is electrically connected with the chip.
2. packaging method according to claim 1, which is characterized in that the thickness of the chip and the chip upper surface are extremely
The ratio range of the vertical range of the bulge-structure upper surface is 0.2-5.
3. packaging method according to claim 1, which is characterized in that far from the carrier substrate on the plastic packaging layer
Side forms connection circuit and also wraps after the connection circuit is electrically connected by the opening on the plastic packaging layer with the chip
It includes:
It removes the carrier substrate and obtains chip-packaging structure, and cut the chip-packaging structure and obtain single chip encapsulation knot
Structure.
4. packaging method according to claim 1, which is characterized in that the connection circuit is attached most importance to wiring layer, in the modeling
Side on sealing far from the carrier substrate is formed before connection circuit, further includes:
The bulge-structure for removing the plastic packaging layer obtains the smooth plastic packaging layer in upper surface.
5. packaging method according to claim 1, which is characterized in that in side of the chip far from the carrier substrate
Form plastic packaging layer, comprising:
Plastic packaging layer is formed far from the side of the carrier substrate in the chip using plastic packaging membrane cavity.
6. packaging method according to claim 5, which is characterized in that using plastic packaging membrane cavity in the chip far from the load
The side of structure base board forms plastic packaging layer, comprising:
Capsulation material is injected into the plastic packaging membrane cavity and forms plastic packaging layer, includes at least two groove knots in the plastic packaging membrane cavity
Structure, the capsulation material are correspondingly formed the bulge-structure of the plastic packaging layer in the groove structure.
7. packaging method according to claim 1, which is characterized in that at least two bulge-structures are arranged in a crossed manner.
8. packaging method according to claim 1, which is characterized in that when the plastic packaging layer includes a plurality of bulge-structure,
The shape of the bulge-structure is " well " shape.
9. packaging method according to claim 8, which is characterized in that each chip and at least one bulge-structure pair
It should be arranged.
10. a kind of encapsulating structure for being fanned out to cake core, which is characterized in that wanted using any one of claim 1-3 or right
Packaging method described in any one of 5-9 is asked to encapsulate to obtain.
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| CN111354671A (en) * | 2018-12-21 | 2020-06-30 | 深南电路股份有限公司 | Chip packaging method and chip packaging body |
| US11342256B2 (en) | 2019-01-24 | 2022-05-24 | Applied Materials, Inc. | Method of fine redistribution interconnect formation for advanced packaging applications |
| CN109994462B (en) * | 2019-03-29 | 2021-09-17 | 上海天马微电子有限公司 | Chip packaging structure and packaging method thereof |
| IT201900006736A1 (en) | 2019-05-10 | 2020-11-10 | Applied Materials Inc | PACKAGE MANUFACTURING PROCEDURES |
| IT201900006740A1 (en) | 2019-05-10 | 2020-11-10 | Applied Materials Inc | SUBSTRATE STRUCTURING PROCEDURES |
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| US11676832B2 (en) | 2020-07-24 | 2023-06-13 | Applied Materials, Inc. | Laser ablation system for package fabrication |
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| US11404318B2 (en) | 2020-11-20 | 2022-08-02 | Applied Materials, Inc. | Methods of forming through-silicon vias in substrates for advanced packaging |
| US11705365B2 (en) | 2021-05-18 | 2023-07-18 | Applied Materials, Inc. | Methods of micro-via formation for advanced packaging |
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Application publication date: 20170322 Assignee: Huajin semiconductor (Jiashan) Co.,Ltd. Assignor: National Center for Advanced Packaging Co.,Ltd. Contract record no.: X2021980017402 Denomination of invention: A packaging structure of fan out chip and its packaging method Granted publication date: 20190809 License type: Exclusive License Record date: 20220111 |
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