CN111354671A - Chip packaging method and chip packaging body - Google Patents
Chip packaging method and chip packaging body Download PDFInfo
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- CN111354671A CN111354671A CN201811572122.2A CN201811572122A CN111354671A CN 111354671 A CN111354671 A CN 111354671A CN 201811572122 A CN201811572122 A CN 201811572122A CN 111354671 A CN111354671 A CN 111354671A
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- chip
- adhesive layer
- groove
- carrier
- package body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
Abstract
The application discloses a chip packaging method and a chip packaging body, wherein the method comprises the following steps: providing a carrier provided with a through groove, and arranging an adhesive layer on one side of the carrier so that the adhesive layer covers one end of the through groove; arranging a chip on one side, close to the adhesive layer, in the through groove, so that the chip is fixed in the through groove through the adhesive layer; and forming a first plastic package body on one side of the chip, which is far away from the adhesive layer, and removing the adhesive layer. By the mode, the whole thickness of the chip packaging body can be reduced, the light and thin requirements of the chip packaging body are met, and technical support is further provided for light and thin of electronic products.
Description
Technical Field
The present disclosure relates to the field of chip packaging technologies, and in particular, to a chip packaging method and a chip package.
Background
Packaging, is the process of assembling integrated circuits into chip end products. In the prior art, when a chip is packaged, a produced integrated circuit bare chip is usually fixed on a substrate which plays a bearing role through gluing, pins are led out, the chip is subjected to plastic package, and the chip is fixedly packaged into a whole.
However, the inventor of the present application finds, in a long-term research and development process, that in the chip packaging method in the prior art, after the chip packaging is completed, the formed adhesive layer and the substrate still remain, so that the thickness of the chip package body is greatly increased, and the requirement of light and thin of the current electronic product is not facilitated.
Disclosure of Invention
The present application mainly solves the technical problem of providing a chip packaging method and a chip package, which can reduce the overall thickness of the chip package to meet the light and thin requirements of the chip package, and further provide technical support for the light and thin of electronic products.
In order to solve the technical problem, the application adopts a technical scheme that: a chip packaging method is provided, which comprises the following steps: providing a carrier provided with a through groove, and arranging an adhesive layer on one side of the carrier so that the adhesive layer covers one end of the through groove; arranging a chip on one side, close to the adhesive layer, in the through groove, so that the chip is fixed in the through groove through the adhesive layer; and forming a first plastic package body on one side of the chip, which is far away from the adhesive layer, and removing the adhesive layer.
In order to solve the above technical problem, another technical solution adopted by the present application is: provided is a chip package, including: the carrier is provided with a through groove penetrating through the carrier; the chip is arranged in the through groove; the plastic package body is arranged around the periphery of the chip and used for packaging the chip, and a blind hole is formed in the plastic package body along the opening direction of the through groove so as to communicate the chip with the outside; and the pin is arranged in the blind hole, extends out of the blind hole and is used for connecting the chip with an external device.
The beneficial effect of this application is: different from the prior art, the chip packaging method comprises the following steps: providing a carrier provided with a through groove, and arranging an adhesive layer on one side of the carrier so that the adhesive layer covers one end of the through groove; arranging a chip on one side, close to the adhesive layer, in the through groove so that the chip is fixed in the through groove through the adhesive layer; and forming a first plastic package body on one side of the chip far away from the adhesive layer, and removing the adhesive layer. In this way, chip packaging method in this application is when encapsulating the chip, through set up the viscose layer that covers logical groove one end in order to fix the chip and the plastic envelope in one side at the carrier, and after forming first plastic envelope body, further get rid of the viscose layer, make the chip package body that finally obtains not include the viscose layer, thereby can reduce the whole thickness of chip package body, in order to satisfy chip package body's frivolousization demand, and further provide technical support for electronic product's frivolousness.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts. Wherein:
FIG. 1 is a schematic flow chart diagram illustrating an embodiment of a chip packaging method according to the present application;
FIG. 2 is a schematic flow chart diagram illustrating another embodiment of a chip packaging method according to the present application;
FIG. 3 is a schematic flow chart diagram illustrating a chip packaging method according to another embodiment of the present application;
FIG. 4 is a schematic flow chart of step S35 in FIG. 3;
FIG. 5 is a schematic flow chart diagram illustrating a chip packaging method according to another embodiment of the present application;
fig. 6 is a schematic top view of a carrier according to an embodiment of the chip packaging method of the present application;
fig. 7 to 15 are schematic structural diagrams of the chip packaging process of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1 and fig. 6 to 10 together, fig. 1 is a schematic flow chart of an embodiment of a chip packaging method according to the present application, the method including:
step S11: providing a carrier 11 provided with a through groove 111, and providing an adhesive layer 12 on one side of the carrier 11, so that the adhesive layer 12 covers one end of the through groove 111, as shown in fig. 7;
the carrier 11 in the present embodiment refers to the carrier 11 of the chip 13, and encapsulates the chip 13. The material of the carrier 11 may be plastic, ceramic, or the like.
Specifically, the carrier 11 is provided with a through groove 111, and the through groove 111 penetrates through both ends of the carrier 11. The number of the through grooves 111 may be one or multiple, and when the number of the through grooves 111 is multiple, the multiple through grooves 111 may be arranged on the carrier 11 in an array, as shown in fig. 6, and of course, may also be arranged in other manners according to actual use requirements, which is not specifically limited herein.
Further, the cross section of the through groove 111 may be square, or other shapes, such as circle, triangle, etc.
In this embodiment, the adhesive layer 12 is provided on one side of the carrier 11 so that the adhesive layer 12 covers one end of the through-groove 111.
The adhesive layer 12 may be any adhesive layer 12 capable of adhering to the chip 13. For example, the adhesive layer 12 may be formed by a common single-sided adhesive tape or double-sided adhesive tape, or by directly coating an adhesive, or a film-like adhesive, such as an EVA adhesive film, a PVB adhesive film, or the like, which is not limited herein.
In one application scenario, the adhesive layer 12 is a debonding adhesive layer. Adopt and separate bonding glue, have stronger viscidity when using to fixed chip 13 that can be firm, when using and need removing, can adopt modes such as toasting or laser irradiation for separate bonding glue loses viscidity, thereby peels off from carrier 11 and chip 13 easily, and is simple, convenient, no residue.
When the adhesive layers 12 are disposed, one end of the plurality of through grooves 111 of the carrier 11 can be uniformly covered by one adhesive layer 12, and of course, the corresponding adhesive layers 12 can be disposed at the corresponding positions of each through groove 111, or the adhesive layers 12 are disposed only on the respective through grooves 111, as required, which is not limited specifically herein.
Step S12: arranging the chip 13 in the through groove 111 at a side close to the adhesive layer 12, so that the chip 13 is fixed in the through groove 111 through the adhesive layer 12, as shown in fig. 8;
wherein, the adhesive layer 12 has an adhesive property at least at a side facing the through groove 111. In this embodiment, the chip 13 is disposed on the side of the adhesive layer 12 close to the through groove 111 by passing through the through groove 111, so that the chip 13 is adhered to the adhesive layer 12 and further fixed in the through groove 111 through the adhesive layer 12.
In the present embodiment, the size of the periphery of the chip 13 is smaller than the size of the inside of the through-groove 111, so that the chip 13 can be completely accommodated inside the through-groove 111. Specifically, the height of the chip 13 is smaller than the height of the through-groove 111.
Step S13: a first molding body 14 is formed on the side of the chip 13 away from the adhesive layer 12, and the adhesive layer 12 is removed, as shown in fig. 9 and 10.
When the first plastic package body 14 is formed, a prepreg may be pressed into the through groove 111 by using a press molding method or the like, so as to form the first plastic package body 14. The material of the first plastic package 14 may be the same as that of the carrier 11, and may be, for example, plastic, resin, etc., which is not limited herein.
By forming the first plastic package body 14, the chip 13 can be packaged in the first plastic package body 14 and the carrier 11 without being fixed by the adhesive layer 12, and therefore, in this embodiment, after the first plastic package body 14 is formed, the adhesive layer 12 is further removed, and a specific method for removing the adhesive layer 12 is related to the type of the adhesive layer 12 used, as described in step S11, if the adhesive layer 12 is a debonding adhesive, the adhesive layer 12 can be removed simply and cleanly by baking or laser irradiation or the like, so that the adhesive layer 12 can be removed simply and cleanly.
In the process of forming the first plastic package body 14, the height of the formed first plastic package body 14 can be controlled by controlling the height of the mold, for example, the height of the first plastic package body 14 is controlled to be higher than the chip 13, or the height of the first plastic package body 14 is controlled to be equivalent to the height of the through groove 111 of the carrier 11, and the like.
It should be noted that in the present embodiment, the height of the chip 13 is smaller than the height of the through groove 111, so that the carrier 11 can play a supporting role during the compression molding process for forming the first molding compound 14, thereby avoiding the chip 13 from bearing the pressure caused by the compression molding alone, and thus protecting the chip 13 to some extent.
In the present embodiment, the first molding compound 14 may be molded only on the side of the chip 13 located on the adhesive layer 13, or may be formed by a technical means so as to completely surround the outer periphery of the chip 13, which is not limited in detail herein.
When the chip 13 is packaged by the chip packaging method in this embodiment, the adhesive layer 12 covering one end of the through groove 111 is arranged on one side of the carrier 11 to fix and plastically package the chip 13, and after the first plastic package body 14 is formed, the adhesive layer 12 is further removed, so that the finally obtained chip package body does not include the adhesive layer 12, thereby reducing the overall thickness of the chip package body, meeting the light and thin requirements of the chip package body, and further providing technical support for the light and thin of an electronic product.
Further, referring to fig. 2, fig. 6 to fig. 11, fig. 2 is a schematic flow chart of another embodiment of the chip packaging method of the present application, where the method includes:
step S21: providing a carrier 11 provided with a through groove, and providing an adhesive layer 12 on one side of the carrier 11, so that the adhesive layer 12 covers one end of the through groove 111, as shown in fig. 7;
step S22: arranging the chip 13 in the through groove 111 at a side close to the adhesive layer 12, so that the chip 13 is fixed in the through groove 111 through the adhesive layer 12, as shown in fig. 8;
step S23: forming a first molding body 14 on the side of the chip 13 away from the adhesive layer 12, and removing the adhesive layer 12, as shown in fig. 9 and 10;
step S21, step S22, and step S23 are the same as step S11, step S12, and step S13, respectively, and for details, please refer to the above embodiments, which is not repeated herein.
Step S24: a second plastic package body 15 is formed on the side of the chip 13 remote from the side where the first plastic package body 14 is formed, as shown in fig. 11.
In this embodiment, after the adhesive layer 12 is removed, since the side of the chip 13 on the adhesive layer 12 is exposed, the side can be further subjected to plastic molding to form the second plastic molded body 15.
The second plastic package body 15 can be formed in the same manner as the first plastic package body 14, and please refer to the above embodiment for related details.
In this embodiment, when encapsulating the chip 13, firstly, the adhesive layer 12 is utilized to fix the chip 13, and further, the first plastic package body 14 is formed on the side, away from the adhesive layer 12, of the chip 13, so that the chip 13 is preliminarily fixed in the through groove 111 of the carrier 11, and then the adhesive layer 12 is further removed, and then the second plastic package body 14 is formed on the side, originally provided with the adhesive layer 12, of the chip 13, thereby realizing the encapsulation of the chip 13. It should be noted that, in the present embodiment, the adhesive layer 12 is removed in the packaging process of the chip 13, so that the occupation of the adhesive layer 12 on the thickness of the formed chip package is reduced, which is beneficial to the thinning of the chip package.
Referring to fig. 3 and fig. 6 to 12, fig. 3 is a schematic flow chart diagram illustrating a chip packaging method according to another embodiment of the present application, the method including:
step S31: providing a carrier 11 provided with a through groove 111, and providing an adhesive layer 12 on one side of the carrier 11, so that the adhesive layer 12 covers one end of the through groove 111, as shown in fig. 7;
step S32: arranging the chip 13 in the through groove 111 at a side close to the adhesive layer 12, so that the chip 13 is fixed in the through groove 111 through the adhesive layer 12, as shown in fig. 8;
step S33: forming a first molding body 14 on the side of the chip 13 away from the adhesive layer 12, and removing the adhesive layer 12, as shown in fig. 9 and 10;
step S34: forming a second plastic package body 15 on the side of the chip 13 away from the side where the first plastic package body 14 is formed, as shown in fig. 11;
step S35: the leads 16 of the chip are arranged so that the chip 16 is connected to an external device, as shown in fig. 12.
Step S31, step S32, step S33 and step S34 are the same as step S21, step S22, step S23 and step S24, respectively, and the detailed description thereof is omitted herein for reference to the above-mentioned embodiments.
Note that, in this embodiment, after the first plastic package body 14 and the second plastic package body 15 are formed, the pins 16 of the chip are further provided, so that the chip 13 can be connected to an external device to realize a corresponding function.
In the present embodiment, the manner of providing the leads 16 of the chip 13 is not limited. Specifically, in an application scenario, referring to fig. 4, step S35 includes:
step S351: a plurality of blind holes 17 are respectively arranged on the first plastic package body 14 and the second plastic package body 15, and the blind holes 17 are positioned on two sides of the chip 13 so as to communicate the chip 13 with the outside through the blind holes 17;
since the chip 13 is encapsulated in the carrier 11 and the first and second plastic-sealed bodies 14 and 15 after the first and second plastic-sealed bodies 14 and 15 are formed, in this embodiment, the first and second plastic-sealed bodies 14 and 15 are further perforated to form the blind hole 17, so that the chip 13 can communicate with the outside.
Specifically, the first and second plastic packages 14 and 15 may be drilled at corresponding positions using etching or laser drilling techniques to form blind holes 17, thereby exposing the chip 13. The number of the blind holes 17 can be set according to the requirement, and is not limited herein.
It should be noted that, in other embodiments, when the first plastic package body 14 and the second plastic package body 15 are formed, by selecting a suitable mold, the first plastic package body 14 and the second plastic package body 15 themselves have the blind hole 17 capable of communicating the chip 13 with the outside, so that after the first plastic package body 14 and the second plastic package body 15 are formed, no additional blind hole 15 needs to be formed by drilling.
Step S352: through the predetermined mode, fill metal in blind hole 17 to extend from blind hole 17, form a plurality of pins 16 of chip 13, so that chip 13 is connected with external device.
In this embodiment, the blind holes may be filled with metal by metal injection, printing process, electroplating method, ball drop method, etc., and the filled metal may extend out of the blind holes 17 to form the leads 16.
It should be pointed out that, in the prior art, the gold thread is taken through the routing mode and the chip 13 is led out, however, this mode often needs to occupy a certain height, thereby increasing the thickness of the first plastic-sealed body 14 and the second plastic-sealed body 15, and further increasing the thickness of the chip-sealed body, and in this application, the blind hole 17 is drilled on the first plastic-sealed body 14 and the second plastic-sealed body 15, and the chip 13 is led out to be communicated with the outside in the mode of filling metal in the blind hole 17, and the height of the first plastic-sealed body 14 and the second plastic-sealed body 15 does not need to be additionally occupied, thereby further being favorable for the lightness and thinness of the chip-sealed body.
Referring to fig. 5 to 7 and fig. 10 to 15, fig. 5 is a schematic flow chart diagram illustrating another embodiment of a chip packaging method according to the present application, the method including:
step S41: providing a carrier 11 provided with a through groove 111, and providing an adhesive layer 12 on one side of the carrier 11, so that the adhesive layer 12 covers one end of the through groove 111, as shown in fig. 7;
step S42: arranging a substrate 18 on the side of the adhesive layer 12 away from the chip 13 to connect the substrate 18 with the carrier 11 through the adhesive layer 12, as shown in fig. 13;
step S43: arranging the chip 13 in the through groove 111 at a side close to the adhesive layer 12, so that the chip 13 is fixed in the through groove 111 through the adhesive layer 12, as shown in fig. 14;
step S44: forming a first plastic package body 14 on the side of the chip 13 away from the adhesive layer 12, and removing the adhesive layer 12 and the substrate 18, as shown in fig. 15 and 10;
step S45: forming a second plastic package body 15 on the side of the chip 13 away from the side where the first plastic package body 14 is formed, as shown in fig. 11;
step S46: the leads 16 of the chip are arranged so that the chip 16 is connected to an external device, as shown in fig. 12.
In this embodiment, step S31, step S33, and step S35 are the same as step S21, step S22, and step S24, respectively, and the related details refer to the above embodiments and are not described herein again.
In the present embodiment, both surfaces of the adhesive layer 12 provided on one side of the carrier 11 have adhesiveness, and further, after the adhesive layer 12 is provided, the substrate 18 is provided on the side of the adhesive layer 12 away from the chip 13 so that the substrate 18 covers one end of the through-groove 111.
Specifically, the substrate 18 in this embodiment may be made of the same material as or different from the carrier 11, and has higher strength than the adhesive layer 12. In this embodiment, the substrate 18 can enhance the supporting force for the chip 13, so that when the first plastic package body 14 is formed by plastic package, more force can be borne, and the pressure on the chip 13 in the plastic package process can be reduced.
Further, after the first molded body 14 is formed, the substrate 18 is removed before the adhesive layer 12 is removed, or the adhesive layer 12 and the substrate 18 are removed at the same time, to further form the second molded body 15.
Referring to fig. 12, fig. 12 is a schematic structural diagram of a chip package according to an embodiment of the present application. The chip package in this embodiment includes: carrier 11, chip 13, plastic package body 19 and pins 16.
The carrier 11 is provided with through grooves 111 penetrating through the carrier 11, and the chips 13 are disposed in the corresponding through grooves 111, wherein the height of the chip 13 is less than that of the through grooves 111.
The plastic package 19 is disposed around the chip 13 for encapsulating the chip 13. The plastic package body 19 in this embodiment may be formed by pressing, injection molding, or the like, specifically, the complete plastic package body 19 may be formed at one time during packaging, or may be formed separately by multiple times, specifically, as shown in fig. 2, the first plastic package 14 and the second plastic package body 15 are formed separately to completely encapsulate the chip 13.
Further, the plastic package body 19 is provided with a blind hole 17 along the opening direction of the through groove 111 to communicate the chip 13 with the outside. Further, the leads 16 are disposed in the blind holes 17 and extend from the blind holes 17 for connecting the chip 13 with an external device.
The shapes, structures, and forming manners of the carrier 11, the through groove 111, the plastic package body 19, the chip 13, the pins 16, etc. are the same as those in the embodiment of the chip packaging method of the present application, and related details refer to the above embodiment, which is not described herein again.
It should be noted that the chip package of the present embodiment does not include the adhesive layer 12, which can reduce the overall thickness of the chip package compared with the prior art; further, in the embodiment, the blind holes 17 are formed in the plastic package body 19 encapsulating the chip 13, and the pins 16 are formed in the blind holes 17, so that the chip 13 is connected with an external device, and compared with a mode that the chip 13 is led out by a gold wire in the prior art, the height of the plastic package body 19 is not required to be additionally occupied, so that the overall thickness of the chip package body can be further reduced, the chip package body is light and thin, and technical support is provided for development of light and thin electronic devices and electronic equipment.
The above description is only for the purpose of illustrating embodiments of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings of the present application or are directly or indirectly applied to other related technical fields, are also included in the scope of the present application.
Claims (10)
1. A method of chip packaging, the method comprising:
providing a carrier provided with a through groove, and arranging an adhesive layer on one side of the carrier so that the adhesive layer covers one end of the through groove;
arranging a chip on one side, close to the adhesive layer, in the through groove, so that the chip is fixed in the through groove through the adhesive layer;
and forming a first plastic package body on one side of the chip, which is far away from the adhesive layer, and removing the adhesive layer.
2. The method of claim 1, wherein after forming the first molding compound on the side of the chip away from the adhesive layer and removing the adhesive layer, the method further comprises:
and forming a second plastic package body on one side of the chip far away from the side where the first plastic package body is formed.
3. The method of claim 1,
the chip packaging body is provided with a plurality of through grooves which are arranged on the carrier in an array mode.
4. The method of claim 1, wherein providing an adhesive layer on one side of the carrier such that the adhesive layer covers one end of the through slot comprises:
and arranging a debonding adhesive layer on one side of the carrier, so that the bonding adhesive layer covers one end of the through groove.
5. The method of claim 1,
the height of the chip is smaller than that of the through groove.
6. The method of claim 1, wherein after providing an adhesive layer on one side of the carrier such that the adhesive layer covers one end of the through slot, the method further comprises:
arranging a substrate on one side of the adhesive layer, which is far away from the chip, so that the substrate is connected with the carrier through the adhesive layer;
the chip is kept away from adhesive layer one side forms first plastic-sealed body, and gets rid of the adhesive layer, further includes:
and forming a first plastic package body on one side of the chip far away from the adhesive layer, and removing the adhesive layer and the substrate.
7. The method of claim 2, further comprising:
the pins of the chip are arranged so that the chip is connected to an external device.
8. The method of claim 7, wherein the disposing the pins of the chip to connect the chip with an external device further comprises:
respectively arranging a plurality of blind holes positioned at two sides of the chip on the first plastic package body and the second plastic package body so as to communicate the chip with the outside through the blind holes;
and filling metal in the blind holes in a preset mode, extending out of the blind holes to form a plurality of pins of the chip, so that the chip is connected with an external device.
9. A chip package, comprising:
the carrier is provided with a through groove penetrating through the carrier;
the chip is arranged in the through groove;
the plastic package body is arranged around the periphery of the chip and used for packaging the chip, and a blind hole is formed in the plastic package body along the opening direction of the through groove so as to communicate the chip with the outside;
and the pin is arranged in the blind hole, extends out of the blind hole and is used for connecting the chip with an external device.
10. The chip package of claim 9, wherein a height of the chip is less than a height of the through slots.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811572122.2A CN111354671A (en) | 2018-12-21 | 2018-12-21 | Chip packaging method and chip packaging body |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811572122.2A CN111354671A (en) | 2018-12-21 | 2018-12-21 | Chip packaging method and chip packaging body |
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| CN111354671A true CN111354671A (en) | 2020-06-30 |
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| CN201811572122.2A Pending CN111354671A (en) | 2018-12-21 | 2018-12-21 | Chip packaging method and chip packaging body |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103887251A (en) * | 2014-04-02 | 2014-06-25 | 华进半导体封装先导技术研发中心有限公司 | Fan-out-type wafer-level packaging structure and manufacturing process |
| CN204927271U (en) * | 2015-09-17 | 2015-12-30 | 中芯长电半导体（江阴）有限公司 | Packaging structure |
| JP2017045867A (en) * | 2015-08-27 | 2017-03-02 | 古河電気工業株式会社 | Manufacturing method of component built-in wiring board, component built-in wiring board, and electronic component fixing tape |
| CN106531647A (en) * | 2016-12-29 | 2017-03-22 | 华进半导体封装先导技术研发中心有限公司 | Fan-out chip packaging structure and packaging method thereof |
-
2018
- 2018-12-21 CN CN201811572122.2A patent/CN111354671A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103887251A (en) * | 2014-04-02 | 2014-06-25 | 华进半导体封装先导技术研发中心有限公司 | Fan-out-type wafer-level packaging structure and manufacturing process |
| JP2017045867A (en) * | 2015-08-27 | 2017-03-02 | 古河電気工業株式会社 | Manufacturing method of component built-in wiring board, component built-in wiring board, and electronic component fixing tape |
| CN204927271U (en) * | 2015-09-17 | 2015-12-30 | 中芯长电半导体（江阴）有限公司 | Packaging structure |
| CN106531647A (en) * | 2016-12-29 | 2017-03-22 | 华进半导体封装先导技术研发中心有限公司 | Fan-out chip packaging structure and packaging method thereof |
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Application publication date: 20200630 |