KR20160017412A - Stack type semiconductor package structure by use of cavity substrate and method thereof - Google Patents

Stack type semiconductor package structure by use of cavity substrate and method thereof Download PDF

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KR20160017412A
KR20160017412A KR1020140100807A KR20140100807A KR20160017412A KR 20160017412 A KR20160017412 A KR 20160017412A KR 1020140100807 A KR1020140100807 A KR 1020140100807A KR 20140100807 A KR20140100807 A KR 20140100807A KR 20160017412 A KR20160017412 A KR 20160017412A
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substrate
semiconductor die
semiconductor
cavity
electrically connected
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KR1020140100807A
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Korean (ko)
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오세만
김병진
남궁윤기
이재웅
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앰코 테크놀로지 코리아 주식회사
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Priority to KR1020140100807A priority Critical patent/KR20160017412A/en
Publication of KR20160017412A publication Critical patent/KR20160017412A/en

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Abstract

According to the present invention, a stack type semiconductor package using a cavity substrate generates a cavity space, in which a predetermined number of semiconductor dies are laminated, by using a substrate which bonds a first substrate to a second substrate having a cavity and forms a semiconductor package, in which a plurality of semiconductor dies are laminated, by embedding the semiconductor dies in the cavity space, thereby making the semiconductor package small compared to a general substrate which does not use a cavity. In addition, a TMV process can be omitted to simplify processes and a step between an upper semiconductor die and a substrate can be reduced to realize a micro pitch.

Description

캐버티 기판을 이용한 적층형 반도체 패키지 구조 및 방법{STACK TYPE SEMICONDUCTOR PACKAGE STRUCTURE BY USE OF CAVITY SUBSTRATE AND METHOD THEREOF} TECHNICAL FIELD [0001] The present invention relates to a stacked semiconductor package structure using a cavity substrate, and more particularly to a stacked semiconductor package structure and a stacked semiconductor package structure using a cavity substrate.

본 발명은 반도체 패키지 구조 방법에 관한 것으로, 특히 반도체 패키지에 있어서, 제1 기판과 캐버티를 가지는 제2 기판을 접착한 기판을 이용하여 일정 수의 반도체 다이가 적층될 수 있는 캐버티 공간을 생성한 후, 캐버티 공간에 반도체 다이가 내장되도록 하여 다수개의 반도체 다이가 적층되는 반도체 패키지를 형성함으로써 캐버티를 이용하지 않는 일반적인 기판과 비교하여 반도체 패키지를 소형화할 수 있고, TMV(through mold via) 공정을 생략할 수 있어 공정을 간략화할 수 있으며, 기판의 상부에 반도체 다이를 순착적으로 수직 적층시키는 종래의 패키지 구조와 비교하여 상부 반도체 다이와 기판간 단차를 줄일 수 있어 미세피치(fine pitch)로의 구현이 가능한 캐버티 기판을 이용한 적층형 반도체 패키지 구조 및 방법에 관한 것이다.
The present invention relates to a semiconductor package construction method, and more particularly, to a semiconductor package, in which a cavity substrate, in which a predetermined number of semiconductor dies can be stacked, is formed by using a substrate on which a first substrate and a second substrate having a cavity are adhered The semiconductor package can be miniaturized as compared with a general substrate that does not use a cavity, and a through mold via (TMV) The process can be omitted and the process can be simplified and the step difference between the upper semiconductor die and the substrate can be reduced as compared with the conventional package structure in which the semiconductor die is vertically laminated on the upper portion of the substrate in order to achieve a fine pitch And more particularly, to a stacked semiconductor package structure and method using a cavity substrate that can be implemented.

근래에 들어, 반도체 패키지 기술에 있어서, 회로기판(인쇄회로기판, 회로필름 등)에 대한 실장 밀도를 높일 수 있는 구조의 볼 그리드 어레이(ball grid array) 패키지, 베어 칩(bare chip)의 특성을 이용하여 패키지 크기가 크게 줄어든 칩 크기 패키지(csp : chip scale package) 등이 출시되고 있고, 용량과 실장밀도의 증가를 위하여 여러 개의 반도체 다이를 적층한 칩 적층형 패키지가 제안되고 있다.In recent years, in the semiconductor package technology, a ball grid array package and a bare chip having a structure capable of increasing the mounting density with respect to a circuit board (printed circuit board, circuit film, etc.) (Csp: chip scale package) in which the package size is largely reduced, and a chip stacked package in which a plurality of semiconductor dies are stacked is proposed to increase the capacity and the mounting density.

이러한 적층형 반도체 패키지는 일반적으로, 인쇄회로기판(printed circuit board), 써킷테이프(circuit tape), 써킷필름(circuit film) 또는 리드프레임(lead frame)과 같은 서브스트레이트(substrate)에 다수의 반도체 다이를 수직방향으로 적층한 후, 상기 적층된 반도체 다이끼리 또는 반도체 다이와 서브스트레이트를 도전성 본딩 와이어(conductive bonding wire)와 같은 전기적 접속수단으로 본딩(bonding)한 것을 지칭한다.Such a stacked semiconductor package generally includes a plurality of semiconductor dies on a substrate such as a printed circuit board, a circuit tape, a circuit film, or a lead frame. And the semiconductor die and the substrate are bonded to each other with an electrical connection means such as a conductive bonding wire.

이러한 적층형 반도체 패키지는 봉지재로 형성된 몸체 내측에 다수의 반도체 다이를 탑재함으로써 고용량, 고기능화된 성능을 구현할 수 있을 뿐만 아니라, 마더보드(mother board)에서의 실장밀도를 높일 수 있기 때문에 최근 대량으로 제조되고 있는 추세이다.Such a stacked semiconductor package can realize a high capacity and high performance by mounting a plurality of semiconductor dies inside a body formed of an encapsulating material and can increase a mounting density on a mother board, .

도 1은 종래 플립칩 방식을 이용한 반도체 다이의 적층 구조의 단면 모식도를 도시한 것이다.1 is a schematic cross-sectional view of a stacked structure of a semiconductor die using a conventional flip chip method.

먼저 도 1의 (a)에서와 같은 구조에서는 기판(100)의 상부에 상부 반도체 다이(die)(102)와 하부 반도체 다이(104)를 서로 대향하도록 위치시켜 플립칩(filp chip) 방식으로 전기적으로 연결시킨 후, 상부 반도체 다이(102)를 하부의 기판(100)상 패드에 플립칩 방식으로 연결하도록 한다.1 (a), an upper semiconductor die 102 and a lower semiconductor die 104 are placed on the upper side of the substrate 100 so as to be opposed to each other and are electrically connected to each other by a flip chip method And then the upper semiconductor die 102 is flip-chip connected to the pads on the lower substrate 100.

그러나, 위와 같은 종래 도 1의 (a)의 구조에서는 기판(100)의 상부에 두 개의 반도체 다이(102, 104)가 수직으로 적층됨으로서 패키지의 두께가 두꺼워지며, 상부 반도체 다이(104)와 기판(100)간 이격거리가 증가하여 SOP(solder on pad)(106)가 커지게 되는 등 미세피치(fine pitch) 형성이 어려운 문제점이 있다.1 (a), the two semiconductor dies 102 and 104 are vertically stacked on the upper side of the substrate 100 to increase the thickness of the package, and the upper semiconductor die 104, There is a problem that it is difficult to form a fine pitch such that the SOP (solder on pad) 106 is enlarged due to an increase in the distance between the electrodes 100.

다음으로 도 1의 (b)에서와 같은 구조에서는 기판(150)상 제1 반도체 다이(152)와 제2 반도체 다이(154)를 적층시키고, 반도체 다이(152, 154)간 TMV(156)를 형성하여 전기적으로 연결되도록 하여 반도체 다이(152, 154)와 기판(150)간 미세피치로의 연결이 가능하도록 한다.1B, a first semiconductor die 152 and a second semiconductor die 154 are stacked on a substrate 150 and a TMV 156 between the semiconductor dies 152 and 154 is formed So that connection to the fine pitches between the semiconductor dies 152 and 154 and the substrate 150 is made possible.

그러나, 위와 같은 종래 도 1의 (b)의 구조에서는 반도체 다이(152, 154)간 TMV를 형성해야함에 따라 공정이 복잡하며 비용이 비싸다. 또한 여전히 패키지의 두께가 적층되는 반도체 다이의 수만큼 두꺼워지는 문제점이 있다.
However, in the conventional structure of FIG. 1 (b), TMV must be formed between the semiconductor dies 152 and 154, which complicates the process and is expensive. And the thickness of the package is still thicker than the number of semiconductor dies stacked.

대한민국 등록특허번호 10-0632476호(등록일자 2006년 09월 28일)Korean Registered Patent No. 10-0632476 (Registered Date: September 28, 2006)

따라서, 본 발명에서는 반도체 패키지에 있어서, 제1 기판과 캐버티를 가지는 제2 기판을 접착한 기판을 이용하여 일정 수의 반도체 다이가 적층될 수 있는 캐버티 공간을 생성한 후, 캐버티 공간에 반도체 다이가 내장되도록 하여 다수개의 반도체 다이가 적층되는 반도체 패키지를 형성함으로써 캐버티를 이용하지 않는 일반적인 기판과 비교하여 반도체 패키지를 소형화할 수 있고, TMV 공정을 생략할 수 있어 공정을 간략화할 수 있으며, 기판의 상부에 반도체 다이를 순착적으로 수직 적층시키는 종래의 패키지 구조와 비교하여 상부 반도체 다이와 기판간 단차를 줄일 수 있어 미세피치로의 구현이 가능한 캐버티 기판을 이용한 적층형 반도체 패키지 구조 및 방법을 제공하고자 한다.
Therefore, in the semiconductor package of the present invention, after a cavity space is formed in which a predetermined number of semiconductor dies can be stacked by using a substrate to which a first substrate and a second substrate having a cavity are bonded, The semiconductor package can be miniaturized as compared with a general substrate that does not use a cavity by forming a semiconductor package in which a plurality of semiconductor dies are stacked so that the semiconductor die is built in. Thus, the TMV process can be omitted, A stacked semiconductor package structure and method using a cavity substrate which can reduce the step between the upper semiconductor die and the substrate and can realize a fine pitch compared with a conventional package structure in which a semiconductor die is vertically laminated on the upper portion of the substrate .

상술한 본 발명은 캐버티 기판을 이용한 적층형 반도체 패키지 구조로서, 제1 기판과, 상기 제1 기판의 상부에 접착되며 캐버티가 형성된 제2 기판과, 상기 캐버티 내에 안착되어 상기 제1 기판과 연결되는 제1 반도체 다이와, 상기 제1 반도체 다이의 상부에 적층되는 제2 반도체 다이와, 상기 제2 기판의 상부면에 도포되어 상기 캐버티의 내부와 상기 제1 반도체 다이와 제2 반도체 다이를 몰딩시키는 몰드를 포함한다.According to the present invention, there is provided a stacked semiconductor package structure using a cavity substrate, comprising: a first substrate; a second substrate bonded to an upper portion of the first substrate and having a cavity; A second semiconductor die stacked on top of the first semiconductor die; and a second semiconductor die, wherein the second semiconductor die is coated on the upper surface of the second substrate to mold the interior of the cavity and the first semiconductor die and the second semiconductor die Mold.

또한, 상기 캐버티는, 상기 제1 반도체 다이의 개수에 대응되게 형성되는 것을 특징으로 한다.Further, the cavity is formed to correspond to the number of the first semiconductor dies.

또한, 상기 제2 반도체 다이는, 상기 제1 반도체 다이보다 면적이 넓으며, 상기 제2 반도체 다이의 하부의 기설정된 중앙 영역은 상기 제1 반도체 다이와 연결되고, 상기 하부의 외곽 영역은 상기 제2 기판과 전기적으로 연결되는 것을 특징으로 한다.The second semiconductor die may have a larger area than the first semiconductor die, a predetermined central region of the lower portion of the second semiconductor die may be connected to the first semiconductor die, And is electrically connected to the substrate.

또한, 상기 제2 반도체 다이는, 상기 제2 기판에 형성된 배선과 플립칩 방식을 통해 전기적으로 연결되는 것을 특징으로 한다.The second semiconductor die is electrically connected to a wiring formed on the second substrate through a flip chip method.

또한, 상기 제1 반도체 다이는, 상기 제1 기판 또는 제2 반도체 다이와 플립칩 방식을 통해 전기적으로 연결되는 것을 특징으로 한다.The first semiconductor die may be electrically connected to the first substrate or the second semiconductor die through a flip chip method.

또한, 상기 제1 반도체 다이는, 상기 제1 기판에 플립칩 방식을 통해 전기적으로 연결되는 경우 상기 제2 반도체 다이와 접착필름을 통해 접착되며, 또는 상기 제2 반도체 다이에 플립칩 방식을 통해 전기적으로 연결되는 경우 상기 제1 기판과 접착필름을 통해 접착되는 것을 특징으로 한다.The first semiconductor die may be bonded to the second semiconductor die through an adhesive film when the first semiconductor die is electrically connected to the first substrate through a flip chip method or may be electrically connected to the second semiconductor die through a flip- And the second substrate is bonded to the first substrate through an adhesive film.

또한, 상기 제1 반도체 다이는, 하나의 반도체 다이로 형성되거나, 상기 캐버티의 깊이에 대응되게 선택적으로 다수의 적층된 반도체 다이로 형성되는 것을 특징으로 한다.The first semiconductor die may be formed of one semiconductor die or may be formed of a plurality of stacked semiconductor dies selectively corresponding to the depth of the cavity.

또한, 본 발명은 캐버티 기판을 이용한 적층형 반도체 패키지 제조 방법으로서, 제1 기판의 상부에 캐버티가 형성된 제2 기판을 접착시키는 단계와, 상기 캐버티 내에 제1 반도체 다이를 안착시키고 상기 제1 기판과 연결시키는 단계와, 상기 제1 반도체 다이의 상부에 제2 반도체 다이를 적층시키는 단계와, 상기 제2 기판의 상부면에 몰드 컴파운드를 도포하여 상기 캐버티의 내부와 상기 제1 반도체 다이와 제2 반도체 다이를 몰딩시키는 단계를 포함한다.According to another aspect of the present invention, there is provided a method of manufacturing a stacked semiconductor package using a cavity substrate, the method comprising the steps of: adhering a second substrate having a cavity formed thereon to a first substrate; placing a first semiconductor die in the cavity; A method of manufacturing a semiconductor device, comprising the steps of: stacking a first semiconductor die on a first semiconductor die and a second semiconductor die on the first semiconductor die; 2 < / RTI > semiconductor die.

또한, 상기 캐버티는, 상기 제1 반도체 다이의 개수에 대응되게 형성되는 것을 특징으로 한다.Further, the cavity is formed to correspond to the number of the first semiconductor dies.

또한, 상기 제2 반도체 다이는, 상기 제1 반도체 다이보다 면적이 넓으며, 상기 제2 반도체 다이의 하부의 기설정된 중앙 영역은 상기 제1 반도체 다이와 연결되고, 상기 하부의 외곽 영역은 상기 제2 기판과 전기적으로 연결되는 것을 특징으로 한다.The second semiconductor die may have a larger area than the first semiconductor die, a predetermined central region of the lower portion of the second semiconductor die may be connected to the first semiconductor die, And is electrically connected to the substrate.

또한, 상기 제1 반도체 다이는, 상기 제1 기판에 플립칩 방식을 통해 전기적으로 연결되는 경우 상기 제2 반도체 다이와 접착필름을 통해 접착되며, 또는 상기 제2 반도체 다이에 플립칩 방식을 통해 전기적으로 연결되는 경우 상기 제1 기판과 접착필름을 통해 접착되는 것을 특징으로 한다.
The first semiconductor die may be bonded to the second semiconductor die through an adhesive film when the first semiconductor die is electrically connected to the first substrate through a flip chip method or may be electrically connected to the second semiconductor die through a flip- And the second substrate is bonded to the first substrate through an adhesive film.

본 발명에 따르면, 캐버티 기판을 이용한 적층형 반도체 패키지에 있어서, 제1 기판과 캐버티를 가지는 제2 기판을 접착한 기판을 이용하여 일정 수의 반도체 다이가 적층될 수 있는 캐버티 공간을 생성한 후, 캐버티 공간에 반도체 다이가 내장되도록 하여 다수개의 반도체 다이가 적층되는 반도체 패키지를 형성함으로써 캐버티를 이용하지 않는 일반적인 기판과 비교하여 반도체 패키지를 소형화할 수 있다. 또한, TMV 공정을 생략할 수 있어 공정을 간략화할 수 있으며, 기판의 상부에 반도체 다이를 순착적으로 수직 적층시키는 종래의 패키지 구조와 비교하여 상부 반도체 다이와 기판간 단차를 줄일 수 있어 미세피치로의 구현이 가능하다.
According to the present invention, in a stacked semiconductor package using a cavity substrate, a cavity space in which a predetermined number of semiconductor dies can be stacked is created by using a substrate to which a first substrate and a second substrate having a cavity are adhered A semiconductor package is formed by stacking a plurality of semiconductor dies such that a semiconductor die is embedded in a cavity space, thereby making it possible to miniaturize the semiconductor package as compared with a general substrate that does not use a cavity. In addition, since the TMV process can be omitted, the process can be simplified, and the step between the upper semiconductor die and the substrate can be reduced as compared with the conventional package structure in which the semiconductor die is stacked vertically and vertically on the substrate, Implementation is possible.

도 1은 플립칩 방식을 이용한 반도체 다이의 적층 구조의 단면 모식도,
도 2a 내지 도 2d는 본 발명의 실시예에 따른 캐버티 기판을 이용한 적층형 반도체 패키지의 공정 단면도,
도 3은 본 발명의 다른 실시예에 따른 캐버티 기판을 이용한 적층형 반도체 패키지 단면 모식도,
도 4a 내지 도 4d는 본 발명의 다른 실시예에 따른 캐버티 기판을 이용한 적층형 반도체 패키지의 공정 단면도.1 is a schematic sectional view of a laminated structure of a semiconductor die using a flip chip method,
FIGS. 2A to 2D are process cross-sectional views of a stacked semiconductor package using a cavity substrate according to an embodiment of the present invention,
3 is a cross-sectional schematic diagram of a stacked semiconductor package using a cavity substrate according to another embodiment of the present invention,
4A to 4D are process sectional views of a stacked semiconductor package using a cavity substrate according to another embodiment of the present invention.

이하, 첨부된 도면을 참조하여 본 발명의 동작 원리를 상세히 설명한다. 하기에서 본 발명을 설명함에 있어서 공지 기능 또는 구성에 대한 구체적인 설명이 본 발명의 요지를 불필요하게 흐릴 수 있다고 판단되는 경우에는 그 상세한 설명을 생략할 것이다. 그리고 후술되는 용어들은 본 발명에서의 기능을 고려하여 정의된 용어들로서 이는 사용자, 운용자의 의도 또는 관례 등에 따라 달라질 수 있다. 그러므로 그 정의는 본 명세서 전반에 걸친 내용을 토대로 내려져야 할 것이다.Hereinafter, the operation principle of the present invention will be described in detail with reference to the accompanying drawings. In the following description of the present invention, detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. The following terms are defined in consideration of the functions of the present invention, and these may be changed according to the intention of the user, the operator, or the like. Therefore, the definition should be based on the contents throughout this specification.

도 2a 내지 도 2d는 본 발명의 실시예에 따른 캐버티 기판을 이용한 적층형 반도체 패키지의 공정 단면도를 도시한 것이다. 이하, 도 2a 내지 도 2d를 참조하여 본 발명의 반도체 패키지 제조 방법에 대해 상세히 설명하기로 한다.FIGS. 2A to 2D are process cross-sectional views of a stacked semiconductor package using a cavity substrate according to an embodiment of the present invention. Hereinafter, a method of manufacturing a semiconductor package of the present invention will be described in detail with reference to FIGS. 2A to 2D.

먼저, 도 2a에서 보여지는 바와 같이 제1 기판(200)의 상부에 캐버티(cavity)(252)가 형성된 제2 기판(250)을 접착시킨다. 이때, 제1 기판(200)의 상면 중앙부에는 제1 반도체 다이를 예를 들어 플립칩(filp chip) 방식으로 부착시키기 위한 다수의 내부 전도성 패드(202)가 형성될 수 있고, 외곽부에는 제2 기판(250)과의 전기적 연결을 위한 다수의 외부 전도성 패드(204) 등이 형성될 수 있다. 또한, 제2 기판(250)은 중앙부에 반도체 다이가 안착될 수 있는 캐버티(252)가 형성될 수 있으며, 외곽부에는 제1 기판(200)과의 전기적 연결을 비아콘텍(via contact)(204)과 제2 반도체 다이를 예를 들어 플립칩 방식으로 부착시키기 위한 다수의 전도성 패드(256)가 형성될 수 있다.First, as shown in FIG. 2A, a second substrate 250 having a cavity 252 formed thereon is bonded to an upper portion of the first substrate 200. At this time, a plurality of internal conductive pads 202 for attaching the first semiconductor die by, for example, a flip chip method may be formed at the center of the upper surface of the first substrate 200, A plurality of external conductive pads 204 and the like for electrical connection with the substrate 250 may be formed. The second substrate 250 may have a cavity 252 on which a semiconductor die may be mounted. In the outer portion of the second substrate 250, an electrical connection with the first substrate 200 may be a via contact 204 and a plurality of conductive pads 256 for attaching the second semiconductor die in a flip chip manner, for example.

이어, 도 2b에서 보여지는 같이 제1 기판(200)과 제2 기판(250)이 접착되어 형성된 캐버티(252) 공간 상 하부의 제1 기판(200)에 제1 반도체 다이(270)를 전기적 신호 교환 가능하게 부착시키게 된다. 이때 제1 반도체 다이(270)의 저면에 형성된 본딩 패드(bonding pad)와 내부 전도성 패드간은 예를 들어 플립칩 방식으로 연결될 수 있다.Next, as shown in FIG. 2B, the first semiconductor die 270 is electrically connected to the first substrate 200 on the lower part of the cavity 252 formed by adhering the first substrate 200 and the second substrate 250, So that signals can be exchanged. At this time, a bonding pad formed on the bottom surface of the first semiconductor die 270 and the internal conductive pad may be connected by, for example, a flip chip method.

다음으로, 도 2c에서 보여지는 바와 같이 제2 반도체 다이(280)를 제2 기판(250)의 전도성 패드(256)에 전기적으로 연결시키고, 제2 반도체 다이(280)와 제1 반도체 다이(270)는 접착 필름(282) 등을 통해 접착시킨다.Next, the second semiconductor die 280 is electrically connected to the conductive pads 256 of the second substrate 250 and the second semiconductor die 280 and the first semiconductor die 270 Is adhered through the adhesive film 282 or the like.

이어, 도 2d에서 보여지는 바와 같이 제2 반도체 다이(280)가 접착된 반도체 패키지의 상부에 몰드 컴파운드(mold compound) 등을 채우는 몰딩 공정을 수행하여 제1 반도체 다이(270)가 위치한 캐버티(252)내 빈공간과 제1 반도체 다이(270), 제2 반도체 다이(280)를 감싸도록 몰드(mold)(290)를 형성시켜 반도체 패키지를 완성시킬 수 있다.Then, as shown in FIG. 2D, a molding process for filling a mold compound or the like on the upper portion of the semiconductor package to which the second semiconductor die 280 is bonded is performed to form a cavity A mold 290 may be formed to surround the first semiconductor die 270 and the second semiconductor die 280 to complete the semiconductor package.

이에 따라 기판 내부에 형성된 캐버티 공간에 반도체 다이가 내장되도록 하여 다수개의 반도체 다이를 수직 적층시키는 반도체 패키지를 형성함으로써 종래 기판의 상부에 수직으로 적층시키는 반도체 패키지와 비교하여 패키지를 소형화시킬 수 있으며 반도체 다이와 기판간 배선 공정도 간략화할 수 있고 전기적 특성도 개선시킬 수 있게 된다.Accordingly, by forming a semiconductor package in which a plurality of semiconductor dies are stacked vertically by embedding a semiconductor die in a cavity space formed in a substrate, the package can be miniaturized as compared with a semiconductor package stacked vertically on a conventional substrate, The wiring process between the die and the substrate can be simplified and the electrical characteristics can be improved.

도 3은 본 발명의 다른 실시예에 따른 캐버티 기판을 이용한 적층 플립칩 반도체 패키지의 공정 단면도이다.3 is a process sectional view of a laminated flip chip semiconductor package using a cavity substrate according to another embodiment of the present invention.

도 3에 도시된 반도체 패키지는 도 2c에서 도시된 구조와는 달리 제1 반도체 다이(270)와 제2 반도체 다이(280)를 먼저 플립칩 방식 등을 통해 전기적으로 연결시킨 후, 제1 반도체 다이(270)를 캐버티(252)내 하부의 제1 기판(200)과 접착 필름(282) 등을 통해 접착시키도록 한다.3, the first semiconductor die 270 and the second semiconductor die 280 are electrically connected to each other first through a flip chip method or the like, The second substrate 270 is bonded to the first substrate 200 in the cavity 252 through the adhesive film 282 or the like.

이러한 도 3의 구조에서도 도 2c의 반도체 패키지 구조와 마찬가지로 제1 반도체 다이(270)와 제2 반도체 다이(280) 및 제1 기판(200), 제2 기판(250) 사이의 전기적 연결 공정이 간단하여 종래와 비교하여 반도체 다이와 기판간 배선 공정 등이 간략화될 수 있고, 캐버티(252) 공간에 제1 반도체 다이(270)가 안착되므로 반도체 패키지의 소형화가 가능하게 된다.3, the electrical connection process between the first semiconductor die 270 and the second semiconductor die 280 and between the first substrate 200 and the second substrate 250 is simple, like the semiconductor package structure of FIG. 2C The wiring process between the semiconductor die and the substrate can be simplified and the first semiconductor die 270 is placed in the space of the cavity 252. This makes it possible to miniaturize the semiconductor package.

도 4a 내지 도 4d는 본 발명의 다른 실시예에 따른 캐버티 기판을 이용한 적층형 반도체 패키지의 공정 단면도를 도시한 것이다. 이하, 도 4a 내지 도 4d를 참조하여 본 발명의 반도체 패키지 제조 방법에 대해 상세히 설명하기로 한다.4A to 4D are cross-sectional views illustrating a process for fabricating a stacked semiconductor package using a cavity substrate according to another embodiment of the present invention. Hereinafter, a method of manufacturing a semiconductor package of the present invention will be described in detail with reference to FIGS. 4A to 4D.

먼저, 도 4a에서 보여지는 바와 같이 제1 기판(400)의 상부에 캐버티(452)가 형성된 제2 기판(450)을 접착시킨다. 이때, 제1 기판(400)의 상면 중앙부에는 제1 반도체 다이를 예를 들어 플립칩(filp chip) 방식으로 부착시키기 위한 다수의 내부 전도성 패드(402)가 형성될 수 있고, 외곽부에는 제2 기판(450)과의 전기적 연결을 위한 다수의 외부 전도성 패드(404) 등이 형성될 수 있다. 또한, 제2 기판(450)은 중앙부에 반도체 다이가 안착될 수 있는 캐버티(452)가 형성될 수 있으며, 외곽부에는 제1 기판(400)과의 전기적 연결을 비아콘텍(454)과 제2 반도체 다이를 예를 들어 플립칩 방식으로 부착시키기 위한 다수의 전도성 패드(456)가 형성될 수 있다.First, as shown in FIG. 4A, a second substrate 450 having a cavity 452 formed thereon is bonded to an upper portion of the first substrate 400. At this time, a plurality of internal conductive pads 402 for attaching the first semiconductor die by, for example, a flip chip method may be formed at the center of the upper surface of the first substrate 400, A plurality of external conductive pads 404 for electrical connection with the substrate 450, and the like. The second substrate 450 may have a cavity 452 on which a semiconductor die may be mounted. In the outer portion of the second substrate 450, an electrical connection with the first substrate 400 may be formed through the via- A plurality of conductive pads 456 may be formed for attaching two semiconductor dice in a flip chip manner, for example.

이어, 도 4b에서 보여지는 같이 제1 기판(400)과 제2 기판(450)이 접착되어 형성된 캐버티(452) 공간 상 하부의 제1 기판(400)에 제1 반도체 다이(470)를 전기적 신호 교환 가능하게 부착시키게 된다. 이때 제1 반도체 다이(470)의 저면에 형성된 본딩 패드(bonding pad)와 내부 전도성 패드(402)간은 예를 들어 플립칩 방식으로 연결될 수 있다.Next, as shown in FIG. 4B, the first semiconductor die 470 is electrically connected to the first substrate 400 on the lower part of the cavity 452 formed by bonding the first substrate 400 and the second substrate 450 to each other So that signals can be exchanged. At this time, a bonding pad formed on the bottom surface of the first semiconductor die 470 and the internal conductive pad 402 may be connected by, for example, a flip chip method.

다음으로, 도 4c에서 보여지는 바와 같이 제2 반도체 다이(480)와 제3 반도체 다이(490)를 먼저 플립칩 방식 등을 통해 전기적으로 연결시킨 후, 제2 반도체 다이(480)를 캐버티(452)내 하부의 제1 기판(400)에 연결된 제1 반도체 다이(470)와 접착 필름(492) 등을 통해 접착시킨다.Next, as shown in FIG. 4C, after the second semiconductor die 480 and the third semiconductor die 490 are first electrically connected through a flip-chip method or the like, the second semiconductor die 480 is connected to the cavity 452 to the first semiconductor die 470 connected to the first substrate 400 through the adhesive film 492 or the like.

이어, 도 4d에서 보여지는 바와 같이 제2 반도체 다이(480)가 접착된 반도체 패키지의 상부에 몰드 컴파운드(mold compound) 등을 채우는 몰딩 공정을 수행하여 제1 반도체 다이(470)와 제2 반도체 다이(480)가 위치한 캐버티(452)내 빈공간과 제1 반도체 다이(470), 제2 반도체 다이(480), 제3 반도체 다이(490)를 감싸도록 몰드(494)를 형성시켜 반도체 패키지를 완성시킬 수 있다.4D, a molding process is performed to fill a top surface of the semiconductor package to which the second semiconductor die 480 is adhered, such as a mold compound, to form a first semiconductor die 470 and a second semiconductor die 470. [ A mold 494 is formed to enclose the empty space in the cavity 452 where the first semiconductor die 480 is located and the first semiconductor die 470, the second semiconductor die 480 and the third semiconductor die 490, Can be completed.

이에 따라 기판 내부에 형성된 캐버티 공간에 캐버티의 깊이에 대응되게 필요에 따라 다수의 반도체 다이가 내장되도록 하여 다수개의 반도체 다이를 수직 적층시키는 반도체 패키지를 형성함으로써 종래 기판의 상부에 수직으로 적층시키는 반도체 패키지와 비교하여 패키지를 소형화시킬 수 있으며 반도체 다이와 기판간 배선 공정도 간략화할 수 있고 전기적 특성도 개선시킬 수 있게 된다.Accordingly, a plurality of semiconductor dies are embedded in the cavity space formed in the substrate in correspondence with the depth of the cavities, if necessary, thereby vertically stacking a plurality of semiconductor dies vertically on the substrate. The package can be miniaturized as compared with the semiconductor package, the wiring process between the semiconductor die and the substrate can be simplified, and the electrical characteristics can be improved.

상기한 바와 같이, 본 발명에 따르면, 캐버티 기판을 이용한 적층형 반도체 패키지에 있어서, 제1 기판과 캐버티를 가지는 제2 기판을 접착한 기판을 이용하여 일정 수의 반도체 다이가 적층될 수 있는 캐버티 공간을 생성한 후, 캐버티 공간에 반도체 다이가 내장되도록 하여 다수개의 반도체 다이가 적층되는 반도체 패키지를 형성함으로써 캐버티를 이용하지 않는 일반적인 기판과 비교하여 반도체 패키지를 소형화할 수 있다. 또한, TMV 공정을 생략할 수 있어 공정을 간략화할 수 있으며, 상부 반도체 다이와 기판간 단차를 줄일 수 있어 미세피치로의 구현이 가능하도록 한다.As described above, according to the present invention, in a stacked semiconductor package using a cavity substrate, it is possible to use a substrate on which a first substrate and a second substrate having a cavity are bonded, The semiconductor package can be miniaturized as compared with a general substrate that does not use a cavity by forming a semiconductor package in which a plurality of semiconductor dies are stacked by allowing a semiconductor die to be embedded in the cavity space. In addition, since the TMV process can be omitted, the process can be simplified, the step between the upper semiconductor die and the substrate can be reduced, and a micro pitch can be realized.

한편 상술한 본 발명의 설명에서는 구체적인 실시예에 관해 설명하였으나, 여러 가지 변형이 본 발명의 범위에서 벗어나지 않고 실시될 수 있다. 따라서 발명의 범위는 설명된 실시 예에 의하여 정할 것이 아니고 특허청구범위에 의해 정하여져야 한다.
While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention. Accordingly, the scope of the invention should not be limited by the described embodiments but should be defined by the appended claims.

200 : 제1 기판 202 : 내부 전도성 패드
204 : 외부 전도성 패드 250 : 제2 기판
252 : 캐버티 254 : 비아콘텍
256 : 전도성 패드200: first substrate 202: internal conductive pad
204: external conductive pad 250: second substrate
252: Cavity 254: Via Contec
256: Conductive pad

Claims (11)

제1 기판과,
상기 제1 기판의 상부에 접착되며 캐버티가 형성된 제2 기판과,
상기 캐버티 내에 안착되어 상기 제1 기판과 연결되는 제1 반도체 다이와,
상기 제1 반도체 다이의 상부에 적층되는 제2 반도체 다이와,
상기 제2 기판의 상부면에 도포되어 상기 캐버티의 내부와 상기 제1 반도체 다이와 제2 반도체 다이를 몰딩시키는 몰드
를 포함하는 캐버티 기판을 이용한 적층형 반도체 패키지 구조.
A first substrate,
A second substrate bonded to an upper portion of the first substrate and having a cavity;
A first semiconductor die mounted in the cavity and connected to the first substrate,
A second semiconductor die stacked on top of the first semiconductor die,
A second semiconductor die and a second semiconductor die, wherein the first semiconductor die and the second semiconductor die are coated on the upper surface of the second substrate,
A semiconductor substrate, and a semiconductor substrate.
제 1 항에 있어서,
상기 캐버티는,
상기 제1 반도체 다이의 개수에 대응되게 형성되는 것을 특징으로 하는 캐버티 기판을 이용한 적층형 반도체 패키지 구조.
The method according to claim 1,
The cavity
Wherein the first semiconductor die is formed to correspond to the number of the first semiconductor dies.
제 1 항에 있어서,
상기 제2 반도체 다이는,
상기 제1 반도체 다이보다 면적이 넓으며, 상기 제2 반도체 다이의 하부의 기설정된 중앙 영역은 상기 제1 반도체 다이와 연결되고, 상기 하부의 외곽 영역은 상기 제2 기판과 전기적으로 연결되는 것을 특징으로 하는 캐버티 기판을 이용한 적층형 반도체 패키지 구조.
The method according to claim 1,
Wherein the second semiconductor die comprises:
Wherein a predetermined central region of the lower portion of the second semiconductor die is connected to the first semiconductor die and an outer region of the lower portion of the second semiconductor die is electrically connected to the second substrate. A stacked semiconductor package structure using a cavity substrate.
제 3 항에 있어서,
상기 제2 반도체 다이는,
상기 제2 기판에 형성된 배선과 플립칩 방식을 통해 전기적으로 연결되는 것을 특징으로 하는 캐버티 기판을 이용한 적층형 반도체 패키지 구조.
The method of claim 3,
Wherein the second semiconductor die comprises:
Wherein the second substrate is electrically connected to a wiring formed on the second substrate through a flip chip method.
제 1 항에 있어서,
상기 제1 반도체 다이는,
상기 제1 기판 또는 제2 반도체 다이와 플립칩 방식을 통해 전기적으로 연결되는 것을 특징으로 하는 캐버티 기판을 이용한 적층형 반도체 패키지 구조.
The method according to claim 1,
Wherein the first semiconductor die comprises:
Wherein the first substrate or the second semiconductor die is electrically connected to the first substrate or the second semiconductor die through a flip chip method.
제 5 항에 있어서,
상기 제1 반도체 다이는,
상기 제1 기판에 플립칩 방식을 통해 전기적으로 연결되는 경우 상기 제2 반도체 다이와 접착필름을 통해 접착되며, 또는 상기 제2 반도체 다이에 플립칩 방식을 통해 전기적으로 연결되는 경우 상기 제1 기판과 접착필름을 통해 접착되는 것을 특징으로 하는 캐버티 기판을 이용한 적층형 반도체 패키지 구조.
6. The method of claim 5,
Wherein the first semiconductor die comprises:
The second semiconductor die is bonded to the first substrate through the adhesive film when electrically connected to the first substrate through the flip-chip method, or when the second semiconductor die is electrically connected to the second semiconductor die through the flip chip method, Wherein the semiconductor substrate is bonded through a film.
제 1 항에 있어서,
상기 제1 반도체 다이는,
하나의 반도체 다이로 형성되거나, 상기 캐버티의 깊이에 대응되게 선택적으로 다수의 적층된 반도체 다이로 형성되는 것을 특징으로 하는 캐버티 기판을 이용한 적층형 반도체 패키지 구조.
The method according to claim 1,
Wherein the first semiconductor die comprises:
Wherein the semiconductor die is formed of one semiconductor die or alternatively is formed of a plurality of stacked semiconductor dies selectively corresponding to the depth of the cavity.
제1 기판의 상부에 캐버티가 형성된 제2 기판을 접착시키는 단계와,
상기 캐버티 내에 제1 반도체 다이를 안착시키고 상기 제1 기판과 연결시키는 단계와,
상기 제1 반도체 다이의 상부에 제2 반도체 다이를 적층시키는 단계와,
상기 제2 기판의 상부면에 몰드 컴파운드를 도포하여 상기 캐버티의 내부와 상기 제1 반도체 다이와 제2 반도체 다이를 몰딩시키는 단계
를 포함하는 반도체 패키지 제조방법.
Bonding a second substrate having a cavity on an upper portion of the first substrate,
Placing a first semiconductor die in the cavity and connecting the first semiconductor die to the first substrate,
Stacking a second semiconductor die on top of the first semiconductor die,
Applying a mold compound to an upper surface of the second substrate to mold the cavity and the first semiconductor die and the second semiconductor die
≪ / RTI >
제 8 항에 있어서,
상기 캐버티는,
상기 제1 반도체 다이의 개수에 대응되게 형성되는 것을 특징으로 하는 반도체 패키지 제조방법.
9. The method of claim 8,
The cavity
Wherein the second semiconductor die is formed to correspond to the number of the first semiconductor dies.
제 8 항에 있어서,
상기 제2 반도체 다이는,
상기 제1 반도체 다이보다 면적이 넓으며, 상기 제2 반도체 다이의 하부의 기설정된 중앙 영역은 상기 제1 반도체 다이와 연결되고, 상기 하부의 외곽 영역은 상기 제2 기판과 전기적으로 연결되는 것을 특징으로 하는 반도체 패키지 제조방법.
9. The method of claim 8,
Wherein the second semiconductor die comprises:
Wherein a predetermined central region of the lower portion of the second semiconductor die is connected to the first semiconductor die and an outer region of the lower portion of the second semiconductor die is electrically connected to the second substrate. Of the semiconductor package.
제 8 항에 있어서,
상기 제1 반도체 다이는,
상기 제1 기판에 플립칩 방식을 통해 전기적으로 연결되는 경우 상기 제2 반도체 다이와 접착필름을 통해 접착되며, 또는 상기 제2 반도체 다이에 플립칩 방식을 통해 전기적으로 연결되는 경우 상기 제1 기판과 접착필름을 통해 접착되는 것을 특징으로 하는 반도체 패키지 제조방법.
9. The method of claim 8,
Wherein the first semiconductor die comprises:
The second semiconductor die is bonded to the first substrate through the adhesive film when electrically connected to the first substrate through the flip-chip method, or when the second semiconductor die is electrically connected to the second semiconductor die through the flip chip method, Wherein the adhesive is adhered via a film.
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Publication number Priority date Publication date Assignee Title
CN108417556A (en) * 2018-05-23 2018-08-17 奥肯思（北京）科技有限公司 Multichip stacking encapsulation structure
CN111613585A (en) * 2020-05-28 2020-09-01 华进半导体封装先导技术研发中心有限公司 Chip packaging structure and method

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Publication number Priority date Publication date Assignee Title
KR100632476B1 (en) 2004-01-13 2006-10-09 삼성전자주식회사 Multichip Packages and Semiconductor Chips Used in the Package

Patent Citations (1)

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Publication number Priority date Publication date Assignee Title
KR100632476B1 (en) 2004-01-13 2006-10-09 삼성전자주식회사 Multichip Packages and Semiconductor Chips Used in the Package

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108417556A (en) * 2018-05-23 2018-08-17 奥肯思（北京）科技有限公司 Multichip stacking encapsulation structure
CN111613585A (en) * 2020-05-28 2020-09-01 华进半导体封装先导技术研发中心有限公司 Chip packaging structure and method

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