CN106531647A - Fan-out chip packaging structure and packaging method thereof - Google Patents
Fan-out chip packaging structure and packaging method thereof Download PDFInfo
- Publication number
- CN106531647A CN106531647A CN201611248036.7A CN201611248036A CN106531647A CN 106531647 A CN106531647 A CN 106531647A CN 201611248036 A CN201611248036 A CN 201611248036A CN 106531647 A CN106531647 A CN 106531647A
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- chip
- plastic packaging
- packaging layer
- carrier substrate
- bulge
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
Abstract
The embodiment of the invention discloses a fan-out chip packaging structure and a packaging method thereof, belonging to the chip packaging technology field. The packaging method comprises: providing a carrier substrate, and patching a chip on the carrier substrate; and forming a plastic package layer at one side, far away from the carrier substrate, of the chip, wherein the plastic package layer coats the chip, and the plastic package layer includes at least two projection structures. According to the technical scheme, the plastic package layer comprises at least two projection structures configured to form plastic package layer with different thickness distribution having the thick partial region and thin partial region to ensure the reduction of the size of the plastic package layer so as to reduce the deflection of the plastic package layer, mitigate the warping problem caused by different coefficients of thermal expansion between the plastic package layer and the chip, reduce the usage of the packaging materials and save the packaging cost.
Description
Technical field
The present embodiments relate to chip encapsulation technology field, more particularly to a kind of encapsulating structure for being fanned out to cake core and its
Method for packing.
Background technology
Fan-out-type wafer-level packaging (Fan-Out Wafer Level Packaging, FOWLP) is a kind of wafer level processing
Embedded encapsulation, and one of the main Advanced Packaging that I/O numbers are more, integrated motility is good is presently considered to be best suitable for height
Movement/the wireless market of requirement, and to other concern high-performance and undersized market, it may have very strong captivation.
In prior art, typically complete to be fanned out to the encapsulation of cake core using plastic package process, but now with the fan of plastic package process
It is extremely difficult for go out type being encapsulated in warpage control aspect, this is because the thermal expansion of the thermal coefficient of expansion of capsulation material and chip
Coefficient difference is larger, causes plastic packaging layer and the thermal coefficient of expansion of chip layer to mismatch and produce local thermal stress so that packaging part
Produce warpage.Such warpage not only increases plastic packaging successive process difficulty, and it is tight easily to produce chip and encapsulation crackle etc.
The component failure problem of weight.
The content of the invention
In view of this, the embodiment of the present invention provides a kind of encapsulating structure and its method for packing for being fanned out to cake core, to solve
The technical problem of the easy warpage of packaging part in prior art.
In a first aspect, a kind of method for packing for being fanned out to cake core is embodiments provided, including：
One carrier substrate is provided, and chip is attached on the carrier substrate；
Plastic packaging layer is formed away from the side of the carrier substrate in the chip, the plastic packaging layer coats the chip, and
The plastic packaging layer includes at least two bulge-structures.
Optionally, the thickness of the chip and the vertical dimension of the chip upper surface to the bulge-structure upper surface
Ratio range is 0.2-5.
Optionally, after the side formation plastic packaging layer in the chip away from the carrier substrate, also include：
Side away from the carrier substrate on the plastic packaging layer forms connection circuit, and the connection circuit is by described
Opening on plastic packaging layer is electrically connected with the chip；
Peel off the carrier substrate and obtain chip-packaging structure, and cut the chip-packaging structure and obtain single chip envelope
Assembling structure.
Optionally, the connection circuit is attached most importance to wiring layer, the side shape on the plastic packaging layer away from the carrier substrate
Into before connection circuit, also include：
The bulge-structure of the plastic packaging layer is removed, the smooth plastic packaging layer of upper surface is obtained.
Optionally, plastic packaging layer is formed away from the side of the carrier substrate in the chip, including：
Plastic packaging layer is formed away from the side of the carrier substrate in the chip using plastic packaging membrane cavity.
Optionally, plastic packaging layer is formed away from the side of the carrier substrate in the chip using plastic packaging membrane cavity, including：
Capsulation material is injected in the plastic packaging membrane cavity and forms plastic packaging layer, the plastic packaging membrane cavity includes at least two grooves
Structure, the capsulation material are correspondingly formed the bulge-structure of the plastic packaging layer in the groove structure.
Optionally, at least two bulge-structures are arranged in a crossed manner.
Optionally, when the plastic packaging layer includes a plurality of bulge-structure, the bulge-structure is shaped as " well " shape.
Optionally, each described chip is correspondingly arranged with least one bulge-structure.
Second aspect, the embodiment of the present invention additionally provide a kind of encapsulating structure for being fanned out to cake core, using first aspect institute
The method for packing encapsulation for being fanned out to cake core stated is obtained.
The encapsulating structure and its method for packing for being fanned out to cake core provided in an embodiment of the present invention, by providing a carrier base
Plate, and chip is attached on carrier substrate, plastic packaging layer being formed away from the side of carrier substrate in chip, plastic packaging layer coats the core
Piece, and plastic packaging layer includes at least two bulge-structures.Using above-mentioned technical proposal, including at least two raised knots on plastic packaging layer
Structure, the bulge-structure are used for that forming part region to be thicker, subregion is relatively thin, the different plastic packaging layer of thickness distribution, it is ensured that subtract
The volume of little plastic packaging layer, and then reduce the deflection of plastic packaging layer, mitigate between plastic packaging layer and chip as thermal coefficient of expansion is different
The warpage issues for causing, while forming the use that the different plastic packaging layer of thickness distribution can also reduce encapsulating material, save encapsulation
Cost.
Description of the drawings
In order to clearly illustrate the technical scheme of exemplary embodiment of the present, below to describing needed for embodiment
Accompanying drawing to be used does a simple introduction.Obviously, the accompanying drawing introduced is the present invention a part of embodiment to be described
Accompanying drawing, rather than the accompanying drawing of whole, for those of ordinary skill in the art, on the premise of not paying creative work, may be used also
To obtain other accompanying drawings according to these accompanying drawings.
Fig. 1 is a kind of schematic flow sheet of method for packing for being fanned out to cake core that the embodiment of the present invention one is provided；
Fig. 2 a are a kind of schematic top plan views on carrier substrate after attaching chip that the embodiment of the present invention one is provided；
Fig. 2 b are a kind of cross-sectional views on carrier substrate after attaching chip that the embodiment of the present invention one is provided；
Fig. 3 a are the schematic top plan views after a kind of formation plastic packaging layer that the embodiment of the present invention one is provided；
Fig. 3 b are the cross-sectional views after a kind of formation plastic packaging layer that the embodiment of the present invention one is provided；
Fig. 4 is a kind of schematic flow sheet of method for packing for being fanned out to cake core that the embodiment of the present invention two is provided；
A kind of vertical view for removing bulge-structure, forming the smooth plastic packaging layer of upper surface that Fig. 5 a embodiment of the present invention two is provided
Schematic diagram；
A kind of section for removing bulge-structure, forming the smooth plastic packaging layer of upper surface that Fig. 5 b embodiment of the present invention two is provided
Structural representation；
A kind of cross-sectional view that connection circuit is formed on plastic packaging layer that Fig. 6 embodiment of the present invention two is provided；
A kind of cross-sectional view that connection soldered ball is formed on connection circuit that Fig. 7 embodiment of the present invention two is provided；
A kind of stripping carrier substrate that Fig. 8 embodiment of the present invention two is provided, obtains the schematic diagram of encapsulating structure；
A kind of schematic diagram for obtaining single encapsulating structure that Fig. 9 embodiment of the present invention two is provided.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, below with reference to the embodiment of the present invention in it is attached
Figure, by specific embodiment, is fully described by technical scheme.Obviously, described embodiment is of the invention
A part of embodiment, rather than the embodiment of whole, based on embodiments of the invention, those of ordinary skill in the art are not doing
The every other embodiment obtained on the premise of going out creative work, each falls within protection scope of the present invention.
Embodiment one
Fig. 1 is a kind of schematic flow sheet of method for packing for being fanned out to cake core that the embodiment of the present invention one is provided, of the invention
Embodiment provides a kind of method for packing for being fanned out to cake core.Fig. 1 is referred to, what the embodiment of the present invention one was provided is fanned out to cake core
Method for packing may comprise steps of：
S110, one carrier substrate of offer, and chip is attached on the carrier substrate.
Exemplary, Fig. 2 a are that a kind of vertical view on carrier substrate after attaching chip that the embodiment of the present invention one is provided is shown
It is intended to, as shown in Figure 2 a, on carrier substrate 10, is formed with several chips 20, chip 20 can be arranged in the form of matrix arrangement
On carrier substrate 10.
Optionally, carrier substrate 10 can be full wafer wafer substrate, and such as sapphire substrate or silicon substrate substrate may be used also
Think glass substrate or other substrates, the embodiment of the present invention is not defined to the particular type of carrier substrate 10.Optionally,
The shape of carrier substrate 10 can for circle, can also be other shapes, for example the shape of carrier substrate 10 can also for rectangle,
Triangle or other shapes, are not equally defined to the shape of carrier substrate 10 in the embodiment of the present invention, only with circular load
Explain as a example by structure base board.
Fig. 2 b are a kind of cross-sectional views on carrier substrate after attaching chip that the embodiment of the present invention one is provided,
With reference to Fig. 2 b, chip 20 can include front and the back side being correspondingly arranged with front, and the front of chip 20 could be formed with electricity
Pole structure (not shown), the electrode structure are used to connect chip 20 and other external circuits.Chip 20 is attached to into load
During structure base board 10, the direction of the back side of chip 20 towards carrier substrate 10, front is directed away from the direction of carrier substrate 10, exposes
Electrode structure on the front and front of chip 20.
Optionally, can adopt in the method for paste chip 20 is attached on carrier substrate 10, so just need carrying
Coat one layer of tack coat (not shown) on structure base board 10 in advance, chip 20 is pasted onto by carrier substrate by the tack coat
On 10.Optionally, the coating of tack coat can using spin coating, spraying, rolling, printing, non-rotating coating, hot pressing, vacuum pressing-combining with
And the mode such as pressure laminating, tack coat can be organic material or composite.
S120, plastic packaging layer is formed away from the side of the carrier substrate in the chip, the plastic packaging layer coats the core
Piece, and the plastic packaging layer includes at least two bulge-structures.
Exemplary, after the attaching of chip 20 is completed on carrier substrate 10, in chip 20 away from carrier substrate 10
Side forms plastic packaging layer 30,30 coating chip 20 of plastic packaging layer, and plastic packaging layer 30 includes at least two bulge-structures 301.As schemed
Shown in 3a and Fig. 3 b, Fig. 3 a and Fig. 3 b is the schematic top plan view after a kind of formation plastic packaging layer that the embodiment of the present invention one is provided respectively
And cross-sectional view, as shown in Figure 3 a, plastic packaging layer 30 includes a plurality of bulge-structure 301, hands between a plurality of bulge-structure 301
Fork is arranged, and there is the position for intersecting between bulge-structure 301 and bulge-structure 301, is moulded during so can ensure that plastic packaging
The proper flow of closure material, will not be blocked and not circulated by a certain bar or a few bulge-structures 301, it is to avoid the generation in space.
With continued reference to Fig. 3 a, optionally, a plurality of bulge-structure 301 can form the arrangement mode of " well " shape, it is ensured that capsulation material
It is normal to circulate.It is understood that bulge-structure 301 can be linear type, as shown in Figure 3 a, can also be shaped form, also,
The terminal of every bulge-structure 301 can be in the marginal position of plastic packaging layer, can be with the optional position of plastic packaging layer, a plurality of projection
Structure 301 can be arranged in " well " shape, can also be other arrangement modes, and the embodiment of the present invention is not to bulge-structure 301
Shape, forming position, terminal location and arrangement mode be defined, Fig. 3 a only in one way as a example by carry out illustrating
It is bright.
As shown in Figure 3 b, the thickness H1 of chip 20 can be vertical with 20 upper surface of chip to 301 upper surface of bulge-structure
Ratio range between H2 can be 0.2-5.Specifically, due to needing plastic packaging 30 pairs of chip 20 of layer are formed on chip 20
Protected, but the thermal coefficient of expansion due to capsulation material is different from the thermal coefficient of expansion of chip material, for example, capsulation material
Thermal coefficient of expansion be 7.2 or so, and the thermal coefficient of expansion of chip material be only 2.3 or so, the thermal coefficient of expansion of capsulation material
With the thermal coefficient of expansion mismatch problem of chip material than more serious, therefore when temperature changes, the deformation of plastic packaging layer 30
Amount or change in displacement differ larger with the deformation quantity or thermal stress of chip 20, cause plastic packaging layer 30 that mistake occurs with chip 20
Position, the phenomenon of warpage.Inventor is simulated through substantial amounts of experimental data, is found as the thickness H1 of chip 20 and on chip 20
, in certain limit, warpage is less, and for example, the thickness H1 of chip 20 can for ratio range between the thickness H2 of the plastic packaging layer 30 of side
Core as 0.2-5, therefore can be arranged with the ratio range between the thickness H2 of the plastic packaging layer 30 above chip 20
The ratio range of the thickness H2 of the plastic packaging layer 30 above the thickness H1 and chip of piece 20 can be 0.2-5.Further, work as setting
When ratio range between the thickness H2 of the flood plastic packaging layer 30 above the thickness H1 and chip 20 of chip 20 is all 0.2-5, core
The volume of the plastic packaging layer 30 above piece 20 is larger, can equally cause plastic packaging layer 30 that larger deformation quantity occurs when temperature changes
And larger residual stress above chip 20, therefore, it can to arrange plastic packaging layer 30 includes multiple bulge-structures 301, while setting
The thickness H1 for putting chip 20 can be with the ratio model between vertical dimension H2 of 20 upper surface of chip to 301 upper surface of bulge-structure
It can be 0.2-5 to enclose, it is to be appreciated that vertical dimension H2 of 20 upper surface of chip to 301 upper surface of bulge-structure and chip 20
The thickness H2 indications of the plastic packaging layer 30 of top are identical.The setting of bulge-structure 301 substantially reduces the plastic packaging layer above chip 20
30 volume, so, both can ensure that the thickness H1 of chip 20 was identical with the thickness H2 of the plastic packaging layer 30 above chip 20,
It is also ensured that the small volume of the plastic packaging layer 30 above chip 20, when temperature changes, the deformation quantity of plastic packaging layer 30 is less,
Reduce the residual stress between plastic packaging layer 30 and chip 20.Optionally, the thickness of chip 20 can be 0.1-0.7mm, raised to tie
The height of structure 301 can be 0.05-0.65mm.
Can with, with continued reference to Fig. 3 a and Fig. 3 b, each chip 20 corresponding with least one bulge-structure 301 can set
Put.Due to chip 20 on carrier substrate 10 can with arranged in arrays, therefore a full line chip of arrangement in a row can with least
One bulge-structure 301 is correspondingly arranged, and a permutation chip 20 of same arrayed in columns can be with least one bulge-structure 301 pairs
Should arrange, therefore a chip 20 can at least correspond to a bulge-structure 301 in the row direction, and/or, in a column direction extremely
A bulge-structure 301 is corresponded to less, as shown in Figure 2 b.
To sum up, the method for packing for being fanned out to cake core provided in an embodiment of the present invention, chip away from carrier substrate side
Formation plastic packaging layer, plastic packaging layer coating chip and plastic packaging layer include at least two bulge-structures, include at least two on setting plastic packaging layer
Bar bulge-structure, bulge-structure are used for that forming part region to be thicker, subregion is relatively thin, the different plastic packaging layer of thickness distribution, protect
Card reduces the volume of plastic packaging layer, and then the deflection of reduction plastic packaging layer, reduces between plastic packaging layer and chip due to thermal coefficient of expansion
The warpage issues that difference causes, use encapsulating material while forming the different plastic packaging layer of thickness distribution and can also reduce, save envelope
Dress up this.Further, simulated by lot of experimental data, the thickness and chip upper surface of reasonable control chip is to bulge-structure
Ratio range between the vertical dimension on surface is 0.2-5, can at utmost reduce warpage generation, lift chip package matter
Amount, improving product yield.
Optionally, it can be in core using plastic packaging membrane cavity to form plastic packaging layer 30 away from the side of carrier substrate 10 in chip 20
Piece 20 forms plastic packaging layer 30 away from the side of carrier substrate 10.
Exemplary, after the attaching of chip 20 is completed on carrier substrate 10, the carrier substrate of chip 20 will be pasted with
10 are placed in plastic packaging membrane cavity, inject capsulation material in plastic packaging membrane cavity, and capsulation material can be organic material, such as ABF, FR-
4th, BT resins or polypropylene.The plastic packaging membrane cavity includes at least two groove structures, and the capsulation material is in the groove
The bulge-structure 301 of plastic packaging layer 30 is correspondingly formed in structure.It is understood that the groove structure and plastic packaging layer in plastic packaging membrane cavity
301 correspondence of bulge-structure, capsulation material forms bulge-structure 301 in being packed into groove structure.Optionally, in plastic packaging membrane cavity
Can also include that multiple membrane cavities are raised, the raised part of membrane cavity is not formed in such plastic packaging membrane cavity can be with the projection of plastic packaging layer 30
301 correspondence of structure, capsulation material do not form the raised part of membrane cavity and form bulge-structure 301 in being packed into plastic packaging membrane cavity.
Embodiment two
Fig. 4 is a kind of schematic flow sheet of method for packing for being fanned out to cake core that the embodiment of the present invention two is provided, of the invention
Embodiment provides a kind of method for packing for being fanned out to cake core, the embodiment of the present invention with above-described embodiment as substrate, in above-mentioned enforcement
It is optimized on the basis of example, refers to Fig. 4, the method for packing for being fanned out to cake core that the embodiment of the present invention two is provided can includes
Following steps：
S210, one carrier substrate of offer, and chip is attached on the carrier substrate.
S220, plastic packaging layer is formed away from the side of the carrier substrate in the chip, the plastic packaging layer coats the core
Piece, and the plastic packaging layer includes at least two bulge-structures.
S230, the bulge-structure for removing the plastic packaging layer, obtain the smooth plastic packaging layer of upper surface.
Exemplary, Fig. 5 a and Fig. 5 b is a kind of removal bulge-structure that the embodiment of the present invention two is provided respectively, in formation
The top view and cross-sectional view of the smooth plastic packaging layer in surface, as shown in figure 5 a and 5b, removes convex on plastic packaging layer 30
Structure 301 is played, the smooth plastic packaging layer 30 for not having projection of upper surface is obtained, optionally, plastic packaging can be removed by way of milling
The bulge-structure 301 of layer 30, can also etch removal bulge-structure 301 by way of etching, and the embodiment of the present invention is not to such as
What removes bulge-structure 301 is defined, and only need to obtain the smooth plastic packaging layer 30 of upper surface.
S240, the side away from the carrier substrate on the plastic packaging layer form connection circuit, and the connection circuit leads to
The opening crossed on the plastic packaging layer is electrically connected with the chip.
Exemplary, a kind of cross-section structure that connection circuit is formed on plastic packaging layer that Fig. 6 embodiment of the present invention two is provided
Schematic diagram, as shown in fig. 6, connection circuit 40 is formed on the smooth plastic packaging layer 30 of upper surface, connection circuit 40 can be weight cloth
Line layer, is connected circuit 40 and is electrically connected with chip 20 by the opening on plastic packaging layer 30, specifically with chip 20 on electrode structure
Electrical connection.Optionally, the side away from carrier substrate 10 on plastic packaging layer 30 forms connection circuit 40, and process is comprising a series of
The techniques such as thin film deposition, plating, photoetching, development and etching make, and repeat no more here.Terminal Jing on 40 one side of connection circuit
Opening on plastic packaging layer 30 is connected with the electrode structure on chip 20.Connection circuit 40 material can be metal material, such as Al,
Au, Cr, Ni, Cu, Mo, Ti, Ta, Ni-Cr, W etc. and its alloy.
Further, on the plastic packaging layer away from the carrier substrate side form connection circuit after, can be with
Including：
Connection soldered ball is formed away from the side of the plastic packaging layer in the connection circuit.
Exemplary, a kind of section knot that connection soldered ball is formed on connection circuit that Fig. 7 embodiment of the present invention two is provided
Structure schematic diagram, as shown in fig. 7, connection circuit 40 away from plastic packaging layer 30 side formed connection soldered ball 50, can by plating,
Print, plant ball, put the techniques such as ball, then carry out reflux technique, backflow can be realized by conduction of heat, convection current, radiation etc..Connection
The material of soldered ball 50 is mainly solder metal.Such as, Sn, Ag, Cu, Pb, Au, Ni, Zn, Mo, Ta, Bi, In, etc. and its alloy.
S250, peel off the carrier substrate and obtain chip-packaging structure, and cut the chip-packaging structure and obtain single
Chip-packaging structure.
Exemplary, a kind of stripping carrier substrate that Fig. 8 embodiment of the present invention two is provided obtains the signal of encapsulating structure
Figure, with reference to Fig. 8, peeling off carrier substrate 10 can be removed by the mode such as machinery, heating, chemistry, laser.Preferably, due to can
Chip 20 is pasted onto on carrier substrate 10 by tack coat, therefore can shine in the way of using ultraviolet heating or laser
Tack coat is penetrated, occurs tack coat aging, adhesive property declines, such that it is able to be shelled carrier substrate 10 with comparalive ease
From.
The encapsulating structure comprising multiple chips 20 is obtained after peeling off carrier substrate 10, to the encapsulation comprising multiple chips 20
Structure is cut, and obtains single chip encapsulating structure, as shown in Figure 9.Optionally, it is possible to use cutting tool is to comprising multiple
The encapsulating structure of chip 20 is cut, and obtains multiple single chip encapsulating structures, for example can be using glass cutter to bag
Encapsulating structure containing multiple chips 20 is cut, and obtains single chip encapsulating structure, it is also possible to using the method for cut
Encapsulating structure comprising multiple chips 20 is cut, single chip encapsulating structure is obtained, it is preferred that can cut using laser
The method cut obtains single chip encapsulating structure, using laser to cutting comprising the encapsulating structure of multiple chips 20, can be with
Ensure cutting precision.
The method for packing for being fanned out to cake core that the embodiment of the present invention two is provided, forms comprising at least two during plastic packaging
The plastic packaging layer of bulge-structure, before carrier substrate is peeled off removes bulge-structure, obtains the plastic packaging layer above chip than relatively thin core
Chip package, when carrier substrate is peeled off, as the plastic packaging layer above chip is than relatively thin, even if can produce in stripping process
Larger temperature change, but as plastic packaging layer is than relatively thin, small volume, and then plastic packaging layer can be reduced because temperature change is produced
Deformation quantity, reduce due to plastic packaging layer it is different from chip CTE caused by residual stress, it is to avoid warping phenomenon generation.
Optionally, the embodiment of the present invention also provides a kind of encapsulating structure for being fanned out to cake core, with continued reference to Fig. 9, the present invention
The encapsulating structure for being fanned out to cake core that embodiment is provided can include：Chip 20, plastic packaging layer 30, connection circuit 40 and connection weldering
Ball 50, the encapsulating structure for being fanned out to cake core provided in an embodiment of the present invention can adopt being fanned out to for any embodiment of the present invention offer
The method for packing encapsulation of cake core is obtained, and the encapsulating structure for being fanned out to cake core provided in an embodiment of the present invention, warping phenomenon are little.
Note, above are only presently preferred embodiments of the present invention and institute's application technology principle.It will be appreciated by those skilled in the art that
The invention is not restricted to specific embodiment described here, can carry out for a person skilled in the art various obvious changes,
Readjust and substitute without departing from protection scope of the present invention.Therefore, although the present invention is carried out by above example
It is described in further detail, but the present invention is not limited only to above example, without departing from the inventive concept, also
More other Equivalent embodiments can be included, and the scope of the present invention is determined by scope of the appended claims.
Claims (10)
1. a kind of method for packing for being fanned out to cake core, it is characterised in that include：
One carrier substrate is provided, and chip is attached on the carrier substrate；
Plastic packaging layer is formed away from the side of the carrier substrate in the chip, the plastic packaging layer coats the chip, and described
Plastic packaging layer includes at least two bulge-structures.
2. method for packing according to claim 1, it is characterised in that the thickness of the chip is with the chip upper surface extremely
The ratio range of the vertical dimension of the bulge-structure upper surface is 0.2-5.
3. method for packing according to claim 1, it is characterised in that the chip away from the carrier substrate side
After forming plastic packaging layer, also include：
Side away from the carrier substrate on the plastic packaging layer forms connection circuit, and the connection circuit passes through the plastic packaging
Opening on layer is electrically connected with the chip；
Peel off the carrier substrate and obtain chip-packaging structure, and cut the chip-packaging structure and obtain single chip encapsulation knot
Structure.
4. method for packing according to claim 3, it is characterised in that the connection circuit is attached most importance to wiring layer, in the modeling
Before side on sealing away from the carrier substrate forms connection circuit, also include：
The bulge-structure of the plastic packaging layer is removed, the smooth plastic packaging layer of upper surface is obtained.
5. method for packing according to claim 1, it is characterised in that the chip away from the carrier substrate side
Plastic packaging layer is formed, including：
Plastic packaging layer is formed away from the side of the carrier substrate in the chip using plastic packaging membrane cavity.
6. method for packing according to claim 5, it is characterised in that using plastic packaging membrane cavity in the chip away from the load
The side of structure base board forms plastic packaging layer, including：
Capsulation material is injected in the plastic packaging membrane cavity and forms plastic packaging layer, the plastic packaging membrane cavity includes at least two groove knots
Structure, the capsulation material are correspondingly formed the bulge-structure of the plastic packaging layer in the groove structure.
7. method for packing according to claim 1, it is characterised in that at least two bulge-structures are arranged in a crossed manner.
8. method for packing according to claim 1, it is characterised in that when the plastic packaging layer includes a plurality of bulge-structure,
The bulge-structure is shaped as " well " shape.
9. encapsulating structure according to claim 8, it is characterised in that each described chip and at least one bulge-structure pair
Should arrange.
10. a kind of encapsulating structure for being fanned out to cake core, it is characterised in that using the encapsulation side described in any one of claim 1-9
Method encapsulation is obtained.
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| CN201611248036.7A CN106531647B (en) | 2016-12-29 | 2016-12-29 | A kind of encapsulating structure being fanned out to cake core and its packaging method |
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Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108960006A (en) * | 2017-05-19 | 2018-12-07 | 致伸科技股份有限公司 | Fingerprint identification module and preparation method thereof |
| CN109994462A (en) * | 2019-03-29 | 2019-07-09 | 上海天马微电子有限公司 | Chip-packaging structure and its packaging method |
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Application publication date: 20170322 Assignee: Huajin semiconductor (Jiashan) Co.,Ltd. Assignor: National Center for Advanced Packaging Co.,Ltd. Contract record no.: X2021980017402 Denomination of invention: A packaging structure of fan out chip and its packaging method Granted publication date: 20190809 License type: Exclusive License Record date: 20220111 |
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