CN104103528A - Fan out type square piece level semiconductor three dimension chip packaging technology - Google Patents
Fan out type square piece level semiconductor three dimension chip packaging technology Download PDFInfo
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- CN104103528A CN104103528A CN201410351678.4A CN201410351678A CN104103528A CN 104103528 A CN104103528 A CN 104103528A CN 201410351678 A CN201410351678 A CN 201410351678A CN 104103528 A CN104103528 A CN 104103528A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
The invention provides a fan out type square piece level semiconductor three dimension chip packaging technology. The fan out type square piece level semiconductor three dimension chip packaging technology effectively guarantees that working size is maximized, improves production capacity, reduces fabricating cost, and eliminates effects of factors of warping and the like during the manufacture process. The fan out type square piece level semiconductor three dimension chip packaging technology includes the following steps: manufacturing alignment marks on the obverse side and the reverse side of a bearing piece; sticking temporary bonding materials to the obverse side and the reverse side of the bearing piece; sticking chips to the obverse side and the reverse side of the bearing piece; coating the obverse side and the reverse side of the bearing piece with first type insulating resin; opening windows on the first type insulating resin so as to form through holes; depositing a seed layer, coating the seed layer with optical resist, enabling a figure to appear on the optical resist, and forming an electroplating circuit in the figure area which appears on the optical resist; removing the electroplating circuit and a portion of the seed layer, which is located on the periphery of the bottom of the electroplating circuit; coating the chips with second type insulating resin, and opening windows on the second type insulating resin, corresponding to the chips; removing the bearing piece and using heat to strip the temporary bonding materials, and adding protection layers on the chips so as to obtain a product; cutting the product into a plurality of chips through a cutting technology.
Description
Technical field
The present invention relates to the technical field of microelectronic packaging process, be specifically related to a kind of fan-out-type square piece level semiconductor chip package process.
Background technology
Along with the trend of electronic product multifunction and miniaturization, high density microelectronic mounting technology becomes gradually main flow on electronic product of new generation.In order to coordinate the development of the development of electronic product of new generation, especially smart mobile phone, palmtop PC, the product such as super, the future development such as the size of chip is higher to density, speed is faster, size is less, cost is lower.Fan-out-type square piece level encapsulation technology (Fanout Panel Level Package, FOPLP) appearance, upgrade technique as fan-out-type Wafer level packaging (Fanout Wafer Level Package, FOWLP), has more vast potential for future development.
See Fig. 1, Japanese J-Devices company, in US 20110309503 A1 patents, has provided a kind of manufacture method of fan-out-type wafer-level packaging:
The patent main technique of J-Devices company is as follows:
The first step: at wafer rear laminating adhesive glue 2(Die Attach Film) after, be divided into one single chip 3;
Second step: be placed with chip 3 on carrying tablet 1;
The 3rd step: apply the first insulating resin 4, and output window 5 on resin, the pad on exposed chip;
The 4th step: by the method for graphic plating and photoetching, make reroute layer 6(Redistribution Layer, a RDL), the pad on chip is drawn;
The 5th step: make the second insulating barrier 7, and do the metal that opening exposes the layer that reroutes;
The 6th step: make soldered ball or salient point 8 on the second insulating barrier.
See Fig. 2, the manufacture method of a kind of Fan Out Panel Level Bga has been introduced in CN201210541846.7 patent by China day science and technology (Xi'an) Co., Ltd.
The method is similar to company of Infineon individual layer fan-out-type Wafer level packaging, is called again the spherical array of embedded wafer scale (Wafer-Level Ball Grid Array, eWLB) technology.Just carrying tablet 9 is changed into square by circle.
The weak point of above two kinds of technology is as follows:
(1). two companies technology only solved the chip-stacked technology of one side;
(2). the method for J-Devices company and company of Infineon, owing to being limited by the restriction (maximum wafer size is 300mm) of wafer size, cannot maximize processing dimension, is unfavorable for the lifting of production capacity and the reduction of cost of manufacture;
(3). the technology of company of Infineon and magnificent day science and technology (Xi'an) Co., Ltd produces the problems such as chip displacement, warpage in manufacturing process, be difficult to promote making yield.
Summary of the invention
For the problems referred to above, the invention provides a kind of fan-out-type square piece level semiconductor chip package process, effectively guaranteed processing dimension maximization, promote production capacity, reduced cost of manufacture, in manufacturing process, use double-sided symmetrical structure, offset due to problems such as warpage that performance difference between material causes, harmomegathus, reduced the difficulty that technique is made.
Its technical scheme is as follows:
A fan-out-type square piece level semiconductor chip package process, it comprises the following steps:
(1), on carrying tablet, the positive back side makes alignment mark;
(2), and the back side positive at carrying tablet covers ephemeral key condensation material;
(3), the pasting chip that is intervally arranged on the covering ephemeral key condensation material at and the back side positive at carrying tablet;
(4), at the positive backside coating first kind of carrying tablet insulating resin, first kind insulating resin covers chip;
(5), at first kind insulating resin uplifting window, form via, the pad of chip is exposed;
(6), on via and first kind insulating resin, deposit Seed Layer, on Seed Layer, apply photoresist, on photoresist, manifest figure, in the graph area manifesting at photoresist, form and electroplate circuit;
(7), remove the Seed Layer of photoresist and photoresist bottom, reservation plating circuit and the Seed Layer of electroplating circuit bottom;
(8), at carrying tablet front and back, apply respectively Equations of The Second Kind insulating resin, on Equations of The Second Kind insulating resin, corresponding chip is windowed to expose and is electroplated circuit formable layer pad;
(9), remove carrying tablet and ephemeral key condensation material, on chip, increase protective layer;
(10), by cutting technique, product is divided into a plurality of chips.
It is further characterized in that, in step (1), the material of carrying tablet can be one or more square pieces in silicon, silicon dioxide, Pyrex, glass with lower alkali content, alkali-free glass, metal, organic material or can heat and a kind of board device of temperature control, label creating method comprises laser marking, sandblast mark, exposure etching, silk screen printing, point one or more techniques in glue, the pattern of alignment mark can be circular, square, triangle, cross, M shape shape;
In step (2), one or more in the modes such as use roll extrusion, spraying, spin coating, hot pressing, vacuum pressing-combining, immersion, pressure laminating are positive and back side covering ephemeral key condensation material at carrying tablet, and ephemeral key condensation material is hot release liner or wafer ephemeral key rubber alloy;
In step (3), chip is arranged according to fixed intervals, and chip is single-chip or multi-chip, and chip is used just subsides mode to mount;
In step (4), coating processes is spin coating, spraying, roller coating, silk screen printing, roll extrusion, one or more techniques in vacuum pressing-combining, first kind insulating resin comprises photosensitive resin and non-photosensitive resin, photosensitive resin comprises welding resistance ink, the green paint of sensitization, dry film, photosensitive type increases layer material, BCB, PBO, one or more in PSPI, non-photosensitive resin comprises epoxy resin, polyimides, phenolic resins, acrylic resin, silica gel, cyanate resin, PVDF, and add one or more in the resin of filler, first kind insulating resin covers chip,
In step (5), at first kind insulating resin uplifting window, form via, the pad of chip is exposed.The method of windowing comprises one or more in the techniques such as photoetching development, laser drill, dry etching, sandblast, selective corrosion;
In step (6), by techniques such as sputter or electroless copper platings, on via 107 and first kind insulating resin, deposit one deck Seed Layer, sputter material is the alloy of one or more metals in Al, Au, Cr, Co, Ni, Cu, Mo, Ti, Ta, W, photoresist is liquid state or film-form, by using egative film to carry out contraposition exposure in mask aligner, through manifesting figure on the technique photoresists such as development, use electric plating method, in the graph area manifesting at photoresist, form and electroplate circuit;
In step (8), Equations of The Second Kind insulating resin is one or more in BBC, PBO, polyimides, dry film, welding resistance ink, epoxy resin, fluorine resin material;
In step (9); by the mode heating or tear bonder open, remove carrying tablet and ephemeral key condensation material; on chip, increase protective layer, protective layer is one or more in metal, organic substance, Heat Conduction Material, by electroplating, plant the mode of ball, printing, forms soldered ball at pad place.
Adopt in the above-mentioned technique that the present invention is, due to the Stack Technology of the present invention by a plurality of chips, can to obtain size less, with better function, and the semiconductor packing device that thickness is thinner adopts the method for two-sided making, can significantly enhance productivity, and reduces costs.
Accompanying drawing explanation
Fig. 1 is the existing fan-out-type wafer level packaging structure of the first schematic diagram;
Fig. 2 is the existing fan-out-type wafer level packaging structure of the second schematic diagram;
Fig. 3 is that the positive back side makes alignment mark schematic diagram on carrying tablet;
Fig. 4 is that carrying tablet front covers ephemeral key condensation material schematic diagram with the back side;
Fig. 5 for being intervally arranged pasting chip schematic diagram on the ephemeral key condensation material at the positive back side of carrying tablet;
Fig. 6 is at the positive backside coating first kind of carrying tablet insulating resin schematic diagram;
Fig. 7 is at first kind insulating resin uplifting window schematic diagram;
Fig. 8 is for depositing Seed Layer, apply photoresist, manifesting figure and form and electroplate conspectus;
Fig. 9 is for removing Some Species sublayer schematic diagram;
Figure 10 windows and forms pad schematic diagram for coating Equations of The Second Kind insulating resin, corresponding chip;
Figure 11 is for removing carrying tablet and ephemeral key condensation material, increasing protective layer schematic diagram;
Figure 12 is for cutting apart chip schematic diagram.
Embodiment
Below in conjunction with accompanying drawing, invention is described in detail, but present embodiment is not limited to the present invention, the conversion in the structure that those of ordinary skill in the art makes according to present embodiment, method or function, is all included in protection scope of the present invention.
A fan-out-type square piece level semiconductor chip package process, it comprises the following steps:
See Fig. 3, the positive back side of (1), carrying tablet 101 makes alignment mark.One or more square pieces in the compositions such as the material of carrying tablet 101 can silicon, silicon dioxide, Pyrex, glass with lower alkali content, alkali-free glass, metal, organic material can be also can heat and a kind of board device of temperature control.Label creating method comprises laser marking, sandblast mark, exposure etching, silk screen printing, the techniques such as some glue.The pattern of alignment mark 102 can be other shapes such as circular, square, triangle, cross, rice word.
See Fig. 4, one or more modes in (2), use roll extrusion, spraying, hot pressing, vacuum pressing-combining, immersion, pressure laminating etc. cover ephemeral key condensation material 103 (as hot release liner, wafer ephemeral key rubber alloy etc. at carrying tablet 101 fronts and the back side.
See Fig. 5, (3), at carrying tablet 101 positive back side pasting chips 104, chip 104 is arranged according to fixed intervals, and chip 104 can be that single-chip can be also multi-chip, and chip 104 is used just subsides mode to mount.
See Fig. 6, (4), at the positive backside coating of carrying tablet 101 (coating processes can be one or more in the techniques such as spin coating, spraying, roller coating, silk screen printing, roll extrusion, vacuum pressing-combining) first kind insulating resin 105, first kind insulating resin 105 mainly comprises photosensitive resin and non-photosensitive resin.Photosensitive resin comprises that welding resistance ink, the green paint of sensitization, dry film, photosensitive type increase one or more in layer material, BCB, PBO, PSPI etc.Non-photosensitive resin comprises epoxy resin, polyimides, phenolic resins, acrylic resin, silica gel, cyanate resin, PVDF and adds one or more in the resin etc. of filler.First kind insulating resin 105 covers chip 104.
See Fig. 7, (5), at first kind insulating resin 105 uplifting windows, form via 107, and the pad of chip 104 106 is exposed.The method of windowing comprises one or more techniques in photoetching development, laser drill, sandblast, selective corrosion etc.
See Fig. 8, (6), by techniques such as sputter (material can be the alloy of a kind of or above metal in Al, Au, Cr, Co, Ni, Cu, Mo, Ti, Ta, W etc.) or electroless copper platings, on via 107 and first kind insulating resin 105, deposit one deck Seed Layer 108.It can be liquid on Seed Layer 108, applying photoresist 109(photoresist, can be also film-form), by using egative film to carry out contraposition exposure in mask aligner, through manifesting figure on the technique photoresists 109 such as development.Use electric plating method, in the graph area manifesting at photoresist 109, form and electroplate circuit 110.
See Fig. 9, the Seed Layer 108 of (7), removal photoresist 109 and photoresist 109 bottoms, retains the Seed Layer 108 of electroplating circuit 110 and electroplating circuit 110 bottoms.
See Figure 10, (8), at carrying tablet 101 front and backs, apply respectively Equations of The Second Kind insulating resin 111, Equations of The Second Kind insulating resin 111 can be one or more in the materials such as BBC, PBO, polyimides, dry film, welding resistance ink, epoxy resin, fluorine resin, can be with identical or different with first kind insulating resin 105 compositions.At Equations of The Second Kind insulating resin 111 uplifting window exposed pads 112.
See Figure 11, (9), by the mode heating or tear bonder open, remove carrying tablet 101 and ephemeral key condensation material 103.On chip 104, increase layer protective layer 113, protective layer 113 can be one or more products in metal, organic substance, Heat Conduction Material etc.By electroplating, plant the modes such as ball, printing, at pad 112 places, form soldered ball 114.
See Figure 12, (10), tested after, by cutting technique, product is divided into a plurality of chips.
Feature of the present invention is
(1). user's machining process can increase substantially manufacture production capacity, reduces product cost.Square piece technique has larger production capacity compared with disk technique, lower cost.The disk size of main flow is the disk of 300mm diameter in the world at present, approximately 113 square inches; The square piece that the PCB substrate size of main flow is 500X600mm, approximately 480 square inches; LCD 4 is of a size of the square piece of 650X830mm with line substrate, approximately 836 square inches.As can be seen here, use the part technique of PCB substrate, processing dimension is 4.25 times of wafer; Use LCD 4 with the part technique of line, processing dimension is 7.4 times of wafer.The lifting of production capacity, can significantly reduce manufacturing cost.
(2). manufacture craft of the present invention has been done further improvement by square piece technique, adopts two-sided while manufacture craft, has further promoted manufacture production capacity, reduces product cost.
Adopt in the above-mentioned technique that the present invention is, due to the Stack Technology of the present invention by a plurality of chips, can to obtain size less, with better function, and the semiconductor packing device that thickness is thinner adopts the method for two-sided making, can significantly enhance productivity, and reduces costs.
Claims (9)
1. a fan-out-type square piece level semiconductor chip package process, is characterized in that: it comprises the following steps:
(1), on carrying tablet, the positive back side makes alignment mark;
(2), at the positive back side of carrying tablet and the back side, cover ephemeral key condensation material;
(3), the pasting chip that is intervally arranged on the ephemeral key condensation material at the positive back side of carrying tablet;
(4), at the positive backside coating first kind of carrying tablet insulating resin, first kind insulating resin covers chip;
(5), at first kind insulating resin uplifting window, form via, the pad of chip is exposed;
(6), on via and first kind insulating resin, deposit Seed Layer, on Seed Layer, apply photoresist, on photoresist, manifest figure, in the graph area manifesting at photoresist, form and electroplate circuit;
(7), remove the Seed Layer of photoresist and photoresist bottom, reservation plating circuit and the Seed Layer of electroplating circuit bottom;
(8), at carrying tablet front and back, apply respectively Equations of The Second Kind insulating resin, on Equations of The Second Kind insulating resin, corresponding chip is windowed to expose and is electroplated line layer and form pad;
(9), remove carrying tablet and ephemeral key condensation material, on chip, increase protective layer;
(10), by cutting technique, product is divided into a plurality of chips.
2. a kind of fan-out-type square piece level semiconductor chip package process according to claim 1, it is characterized in that: in step (1), the material of carrying tablet can be silicon, silicon dioxide, Pyrex, glass with lower alkali content, alkali-free glass, metal, one or more square pieces in organic material or can heat and a kind of board device of temperature control, label creating method comprises laser marking, sandblast mark, exposure etching, silk screen printing, one or more techniques in some glue, the pattern of alignment mark can be circular, square, triangle, cross, rice word.
3. a kind of fan-out-type square piece level semiconductor chip package process according to claim 1, it is characterized in that: in step (2), use one or more modes in roll extrusion, spraying, spin coating, hot pressing, vacuum pressing-combining, immersion, pressure laminating type to cover ephemeral key condensation material at carrying tablet front and the back side, ephemeral key condensation material is hot release liner or wafer ephemeral key rubber alloy.
4. a kind of fan-out-type square piece level semiconductor chip package process according to claim 1, is characterized in that: in step (3), chip is arranged according to fixed intervals, and chip is single-chip or multi-chip, and chip is used just subsides mode to mount.
5. a kind of fan-out-type square piece level semiconductor chip package process according to claim 1, it is characterized in that: in step (4), coating processes is spin coating, spraying, roller coating, silk screen printing, roll extrusion, one or more techniques in vacuum pressing-combining, first kind insulating resin comprises photosensitive resin and non-photosensitive resin, photosensitive resin comprises welding resistance ink, the green paint of sensitization, dry film, photosensitive type increases layer material, BCB, PBO, one or more in PSPI, non-photosensitive resin comprises epoxy resin, polyimides, phenolic resins, acrylic resin, silica gel, cyanate resin, PVDF, and add one or more in the resin of filler, first kind insulating resin covers chip.
6. a kind of fan-out-type square piece level semiconductor chip package process according to claim 1, it is characterized in that: in step (5), at first kind insulating resin uplifting window, form via, the pad of chip is exposed, and the method for windowing comprises one or more techniques in photoetching development, dry etching, laser drill, sandblast, selective corrosion.
7. a kind of fan-out-type square piece level semiconductor chip package process according to claim 1, it is characterized in that: in step (6), by techniques such as sputter or electroless copper platings, on via and first kind insulating resin, deposit one deck Seed Layer, sputter material is Al, Au, Cr, Co, Ni, Cu, Mo, Ti, Ta, the alloy of one or more metals in W, photoresist is liquid state or film-form, by using egative film to carry out contraposition exposure in mask aligner, through manifesting figure on developing process photoresist, use electric plating method, in the graph area manifesting at photoresist, form and electroplate circuit.
8. a kind of fan-out-type square piece level semiconductor chip package process according to claim 1, it is characterized in that: in step (8), Equations of The Second Kind insulating resin is one or more in BBC, PBO, polyimides, dry film, welding resistance ink, epoxy resin, fluorine resin material.
9. a kind of fan-out-type square piece level semiconductor chip package process according to claim 1; it is characterized in that: in step (9); by the mode heating or tear bonder open, remove carrying tablet and ephemeral key condensation material; on chip, increase protective layer; protective layer is one or more in metal, organic substance, Heat Conduction Material, by electroplating, plant the mode of ball, printing, forms soldered ball at pad place.
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| CN201410351678.4A CN104103528A (en) | 2014-07-22 | 2014-07-22 | Fan out type square piece level semiconductor three dimension chip packaging technology |
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| CN201410351678.4A CN104103528A (en) | 2014-07-22 | 2014-07-22 | Fan out type square piece level semiconductor three dimension chip packaging technology |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105225973A (en) * | 2015-11-05 | 2016-01-06 | 南通富士通微电子股份有限公司 | Method for packing |
| WO2017045422A1 (en) * | 2015-09-17 | 2017-03-23 | 中芯长电半导体（江阴）有限公司 | Manufacturing method for packaging structure and redistributable lead layer |
| CN106571343A (en) * | 2016-11-18 | 2017-04-19 | 三星半导体(中国)研究开发有限公司 | Wafer level fan-out type packaging member integrated with passive element and manufacturing method thereof |
| CN107123604A (en) * | 2017-06-01 | 2017-09-01 | 中芯长电半导体（江阴）有限公司 | A kind of method for packing of double-faced forming |
| CN109463007A (en) * | 2016-08-31 | 2019-03-12 | 琳得科株式会社 | The manufacturing method of semiconductor device |
| CN111207973A (en) * | 2020-01-14 | 2020-05-29 | 长江存储科技有限责任公司 | Unsealing method of chip |
| CN111599694A (en) * | 2019-12-30 | 2020-08-28 | 矽磐微电子(重庆)有限公司 | Semiconductor packaging method |
| CN113131890A (en) * | 2019-12-30 | 2021-07-16 | 中芯集成电路（宁波）有限公司 | Manufacturing method of packaging structure |
| US20230170307A1 (en) * | 2021-03-01 | 2023-06-01 | Peking University | Flexible hybrid electronic system processing method and flexible hybrid electronic system |
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Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2017045422A1 (en) * | 2015-09-17 | 2017-03-23 | 中芯长电半导体（江阴）有限公司 | Manufacturing method for packaging structure and redistributable lead layer |
| CN105225973A (en) * | 2015-11-05 | 2016-01-06 | 南通富士通微电子股份有限公司 | Method for packing |
| CN109463007A (en) * | 2016-08-31 | 2019-03-12 | 琳得科株式会社 | The manufacturing method of semiconductor device |
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| KR102487681B1 (en) | 2016-08-31 | 2023-01-11 | 린텍 가부시키가이샤 | Semiconductor device manufacturing method |
| CN106571343A (en) * | 2016-11-18 | 2017-04-19 | 三星半导体(中国)研究开发有限公司 | Wafer level fan-out type packaging member integrated with passive element and manufacturing method thereof |
| CN107123604A (en) * | 2017-06-01 | 2017-09-01 | 中芯长电半导体（江阴）有限公司 | A kind of method for packing of double-faced forming |
| CN111599694A (en) * | 2019-12-30 | 2020-08-28 | 矽磐微电子(重庆)有限公司 | Semiconductor packaging method |
| CN113131890A (en) * | 2019-12-30 | 2021-07-16 | 中芯集成电路（宁波）有限公司 | Manufacturing method of packaging structure |
| CN111207973A (en) * | 2020-01-14 | 2020-05-29 | 长江存储科技有限责任公司 | Unsealing method of chip |
| US20230170307A1 (en) * | 2021-03-01 | 2023-06-01 | Peking University | Flexible hybrid electronic system processing method and flexible hybrid electronic system |
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Application publication date: 20141015 |