CN103745936B - The manufacture method of fan-out square chip level package - Google Patents
The manufacture method of fan-out square chip level package Download PDFInfo
- Publication number
- CN103745936B CN103745936B CN201410045787.3A CN201410045787A CN103745936B CN 103745936 B CN103745936 B CN 103745936B CN 201410045787 A CN201410045787 A CN 201410045787A CN 103745936 B CN103745936 B CN 103745936B
- Authority
- CN
- China
- Prior art keywords
- photosensitive resin
- chip
- equations
- kind photosensitive
- fan
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
Abstract
The present invention provides the manufacture method of a kind of fan-out square chip level package, including: larger-size rectangle carrying tablet is provided, carrying tablet pastes adhesive glue；Chip is just being attached in adhesive glue；Coating Equations of The Second Kind photosensitive resin；The active graphical region of exposed chip on Equations of The Second Kind photosensitive resin；The active graphical region overlay that chip is exposed by coating first kind photosensitive resin；The via leading to chip bonding pad is formed in first kind photosensitive resin；Deposit one layer of Seed Layer, coat photoresist on the seed layer, the graphics field manifested on a photoresist is formed the electroplating line of electrical connection chip bonding pad；One layer of Equations of The Second Kind photosensitive resin of coating, manifests the metal pad on electroplating line on the Equations of The Second Kind photosensitive resin on upper strata again；Metal pad is formed soldered ball.This method can reduce manufacturing cost, and reduce manufacture difficulty in technical process and improve the surface uniformity of coated with resins.
Description
Technical field
The present invention relates to chip packaging method, the manufacture method of a kind of fan-out square chip level package.
Background technology
Along with electronic product multifunction and the trend of miniaturization, high density microelectronic mounting technology is increasingly becoming main flow on a new generation's electronic product.In order to coordinate the development of a new generation's electronic product, especially smart mobile phone, palm PC, the development of the product such as super, the size of chip is higher to density, speed faster, smaller, cost is lower etc., and direction is developed.Fan-out square chip level package technology (Fanout
Panel Level Package, FOPLP) appearance, as fan-out-type Wafer level packaging (Fanout
Wafer Level Package, FOWLP) upgrade technique, have broader development prospect.
J-Devices company of Japan, in US20110309503A1 patent, gives the manufacture method of a kind of fan-out-type wafer-level packaging, as shown in Figure 1.The patent main technique of J-Devices company is as follows:
The first step: use binding agent to form tack coat at certain intervals on substrate；
Second step: be placed with chip in adhesive glue；
3rd step: coat the first insulating resin, and output window on resin, the pad on exposed chip；
4th step: by the method for graphic plating Yu photoetching, makes and reroutes layer (Redistribution
Layer, RDL), the pad on chip is drawn；
5th step: make the second insulating barrier, and do opening and expose the metal rerouting layer；
6th step: face makes soldered ball or salient point over the second dielectric.
This technology is disadvantageous in that, coats the first insulating resin in the 3rd step of technique, owing to usual chip thickness is more than 50 microns, so the thickness of coating insulating resin is wayward, is unfavorable for the making of fine-line.And resin (such as PBO) price is higher individually, is unfavorable for cost control.
Summary of the invention
It is an object of the invention to provide the manufacture method of a kind of fan-out square chip level package, it is possible to reduce manufacturing cost, and in technical process, reduce manufacture difficulty and improve the surface uniformity of coated with resins.The technical solution used in the present invention is, the manufacture method of a kind of fan-out square chip level package, comprises the steps:
The first step, it is provided that carrying tablet, pastes adhesive glue on carrying tablet；
Second step, is just being attached to chip in adhesive glue；
3rd step, posts coating Equations of The Second Kind photosensitive resin in the side of chip on carrying tablet, and Equations of The Second Kind photosensitive resin includes that solder mask, photosensitive green paint, dry film or photosensitive type increase layer material, and chip is covered by Equations of The Second Kind photosensitive resin；
4th step, heating Equations of The Second Kind photosensitive resin makes its precuring, then removes the Equations of The Second Kind photosensitive resin in more than the active graphical region of chip front side, the active graphical region of exposed chip so that outside chip bonding pad is exposed to；
5th step, posting in the side of chip coating first kind photosensitive resin on carrying tablet, first kind photosensitive resin includes the high-res photosensitive resin for quasiconductor and chip package industry such as the Intervia material of BCB, PBO, PSPI, polyimides or Dow Chemical；The active graphical region overlay that chip is exposed by first kind photosensitive resin；
6th step, forms the via leading to chip bonding pad in first kind photosensitive resin；
7th step, deposits one layer of Seed Layer in via and on first kind photosensitive resin；Coat photoresist on the seed layer, then make the figure manifested on photoresist for making electroplating line, use electric plating method, the graphics field manifested is formed the electroplating line of electrical connection chip bonding pad；
8th step, removes the Seed Layer bottom photoresist and photoresist, retains the Seed Layer bottom electroplating line；Carrying tablet coats one layer of Equations of The Second Kind photosensitive resin again so that the Equations of The Second Kind photosensitive resin on upper strata covers electroplating line；
Then on the Equations of The Second Kind photosensitive resin on upper strata, manifest the metal pad on electroplating line；
9th step, forms soldered ball on metal pad.
Further, in the described first step, carrying tablet is rectangle, and material is glass, metallic plate or organic substrate.
Further, in described 3rd step, the technique of coating Equations of The Second Kind photosensitive resin includes spin coating, spraying, roller coating, silk screen printing, slot coated, inkjet printing, rolling or vacuum pressing-combining.
Further, in described 4th step, specifically by para-position exposure technology in exposure machine, make Equations of The Second Kind photosensitive resin react, use developer solution to be removed by Equations of The Second Kind photosensitive resin more than the active graphical region of chip front side.
Further, in described 5th step, the technique of coating first kind photosensitive resin includes spin coating, spraying, roller coating, silk screen printing, slot coated, inkjet printing, rolling or vacuum pressing-combining.
Further, in described 7th step, by splash-proofing sputtering metal or electroless copper plating technique, deposited seed layer in via and on first kind photosensitive resin.
Further, in described 9th step, by plant ball, print, electroplate or chemical plating process formed soldered ball.
It is an advantage of the current invention that:
1). the fan-out technique major part of high performance chips uses first kind photosensitive resin, and this resinoid includes BCB, PBO, PSPI(light-sensitive polyimide), the material such as polyimides.It is high that first kind photosensitive resin has resolution, is suitable for the features such as high frequency operation, and shortcoming is cost intensive.Equations of The Second Kind photosensitive resin mainly includes that solder mask, photosensitive green paint, dry film, photosensitive type increase the products such as layer (build-up) material.The price of Equations of The Second Kind photosensitive resin is far below first kind photosensitive resin, but resolution etc. require also to decrease.The present invention uses Equations of The Second Kind photosensitive resin to make circuit fan-out layer as the filler of chip chamber, first kind photosensitive resin, while ensureing packaging technology precision, reduces manufacturing cost.
2). use two step gluing modes, the uniformity of resin coating can be effectively improved.In the present invention, first by Equations of The Second Kind photosensitive resin, the groove between chip and chip is filled and led up.Fill and lead up rear resin top and can be controlled in less than 10 microns to the distance at chip top, the thickness after the comparable chip paster thickness more than 50 microns, the minimizing of difference in height is coated due to Equations of The Second Kind photosensitive resin after coating, the thickness making first kind photosensitive resin only need to slightly exceed Equations of The Second Kind photosensitive resin, manufacture difficulty is substantially reduced, and resin surface uniformity is greatly improved.
3). the relatively round blade technolgy of square piece technique has bigger production capacity, lower cost.The disk size of main flow is the disk of 300mm diameter the most in the world, about 113 square inches；The square piece of the PCB substrate of main flow a size of 500X600mm, about 480 square inches；The square piece that size is 650X830mm of LCD 4 band wire substrate, about 836 square inches.As can be seen here, using the some processes of PCB substrate, processing dimension is 4.25 times of wafer；Using the some processes of LCD 4 band wire, processing dimension is 7.4 times of wafer.The lifting of production capacity, can be greatly lowered manufacturing cost.
Accompanying drawing explanation
Fig. 1 is the manufacture method schematic diagram of a kind of fan-out-type wafer-level packaging of J-Devices company of Japan.
Fig. 2 is to paste adhesive glue schematic diagram on the carrying tablet of the present invention.
Fig. 3 is the adhering chip schematic diagram of the present invention.
Fig. 4 is the coating Equations of The Second Kind photosensitive resin schematic diagram of the present invention.
Fig. 5 A is the active graphical area schematic of exposed chip on Equations of The Second Kind photosensitive resin of the present invention.
Fig. 5 B is the one single chip of present invention sectional view after removing unnecessary Equations of The Second Kind photosensitive resin.
Fig. 5 C is the one single chip of present invention top view after removing unnecessary Equations of The Second Kind photosensitive resin.
Fig. 6 is the coating first kind photosensitive resin schematic diagram of the present invention.
Fig. 7 A is the making via schematic diagram of the present invention.
Fig. 7 B is that the via of the present invention is less than schematic diagram during chip bonding pad.
Fig. 7 C is that the via of the present invention is more than schematic diagram during chip bonding pad.
Fig. 8 is making Seed Layer and the electroplating line schematic diagram of the present invention.
Fig. 9 is the Equations of The Second Kind photosensitive resin of coating again of the present invention, then manifests the metal pad schematic diagram on electroplating line on the Equations of The Second Kind photosensitive resin on upper strata.
Figure 10 is the making soldered ball schematic diagram of the present invention.
Figure 11 is the flow chart of the present invention.
Detailed description of the invention
Below in conjunction with concrete drawings and Examples, the invention will be further described.
The manufacture method of fan-out square chip level package proposed by the invention, specifically includes following step:
The first step, as shown in Figure 2, it is provided that carrying tablet 101, pastes adhesive glue 102 on carrying tablet 101；
In this step, due to the side's of carrying out chip size package, the therefore carrying tablet of the rectangle that carrying tablet 101 preferred dimension is bigger, the material of carrying tablet 101 is glass, metallic plate or organic substrate；Specifically can pass through the technique such as silk screen printing or some glue, hot pressing, rolling, paste adhesive glue 102.
Second step, as it is shown on figure 3, be just attached to chip 103 in adhesive glue 102；
In this step, specifically just can be attached in adhesive glue 102 by chip 103 by chip mounter, i.e. fit with adhesive glue 102 in the back side of chip 103.
3rd step, as shown in Figure 4, posting coating Equations of The Second Kind photosensitive resin 104 in the side of chip 103 on carrying tablet 101, Equations of The Second Kind photosensitive resin 104 includes that solder mask, photosensitive green paint, dry film or photosensitive type increase layer material, and chip 103 is covered by Equations of The Second Kind photosensitive resin 104；
In this step, Equations of The Second Kind photosensitive resin 104 mainly includes that solder mask, photosensitive green paint, dry film or photosensitive type increase layer material (such as Hitachi's chemical conversion RAYTEC material of company, FZ series material, the AUS410 material etc. of sun ink company of Japan), although the resolution of Equations of The Second Kind photosensitive resin 104 is the highest, but price is far below first kind photosensitive resins such as BCB benzocyclobutene, PBO polyparaphenylene's benzo dioxazole, PSPI light-sensitive polyimide, polyimides.Coating processes can be the techniques such as spin coating, spraying, roller coating, silk screen printing, slot coated, inkjet printing, rolling, vacuum pressing-combining.
4th step, as shown in Fig. 5 A, Fig. 5 B, Fig. 5 C, removes the Equations of The Second Kind photosensitive resin 104 in more than the active graphical region in chip 103 front, the active graphical region of exposed chip 103 so that outside chip bonding pad 106 is exposed to；
Specifically, as shown in Figure 5A, after Equations of The Second Kind photosensitive resin 104 has coated, by techniques such as heating by its precuring.Then by techniques such as para-position exposures in exposure machine, make Equations of The Second Kind photosensitive resin 104 react, use developer solution to be removed by unwanted Equations of The Second Kind photosensitive resin 104, the active graphical region of exposed chip 103.
Fig. 5 B be one single chip 103 expose, developing process complete after profile.It can be seen that Equations of The Second Kind photosensitive resin 104 is through developing process, chip bonding pad 106 is exposed to outside, it is simple to the fan-out technique of follow-up circuit.(chip producer has made chip protection layer 105) that the chip 103 that chip protection layer 105 is to be packaged carries.
Fig. 5 C be one single chip 103 expose, developing process complete after top view, as can be seen from the figure, the region at chip 103 edge is covered by Equations of The Second Kind photosensitive resin 104, make the most of region (active graphical region) in the middle of chip expose, region middle in this section includes the chip bonding pad 106 of electrical requirements.Equations of The Second Kind photosensitive resin 104 covers the width at chip 103 edge, depends on the influence factor such as requirement of performance, the size of chip periphery inactive area and the product of the error of exposure aligning, Equations of The Second Kind photosensitive resin 104 itself.
5th step, as shown in Figure 6, posting in the side of chip 103 coating first kind photosensitive resin 107 on carrying tablet 101, first kind photosensitive resin 107 includes the high-res photosensitive resin for quasiconductor and chip package industry such as the Intervia material of BCB, PBO, PSPI, polyimides or Dow Chemical；The active graphical region overlay that chip 103 is exposed by first kind photosensitive resin 107.Coating processes can be the techniques such as spin coating, spraying, roller coating, silk screen printing, slot coated, inkjet printing, rolling, vacuum pressing-combining.
6th step, as shown in Fig. 7 A, Fig. 7 B, Fig. 7 C, forms the via 108 leading to chip bonding pad 106 in first kind photosensitive resin 107；
As shown in Figure 7 A, first kind photosensitive resin 107 through photoetching, develop, the technique such as solidification, form the via 108 leading to chip bonding pad 106 wherein；
Showing in Fig. 7 B, when chip bonding pad 106 size is bigger, it is simple to form the via 108 leading to chip bonding pad 106, the diameter of via 108 is less than the diameter of chip bonding pad 106.
Fig. 7 C shows, when chip bonding pad 106 size is smaller, in the range of chip bonding pad 106, forms via 108 relatively difficult, then consider that the bottom size of via 108 is more than the diameter of chip bonding pad 106 more than chip bonding pad 106, the diameter of via 108.
7th step, as shown in Figure 8, deposits one layer of Seed Layer 109 in via 108 and on first kind photosensitive resin 107；Seed Layer 109 coats photoresist 110, then makes the figure manifested on photoresist 110 for making electroplating line 111, use electric plating method, the graphics field manifested is formed the electroplating line 111 of electrical connection chip bonding pad 106；
In this step, the techniques such as splash-proofing sputtering metal (material can be Al, Au, Cr, Co, Ni, Cu, Mo, Ti, Ta, Ni-Cr, Co Ni, Co Cr, W etc.) or electroless copper plating can be passed through, deposited seed layer 109 in via 108 and on first kind photosensitive resin 107.Then can be liquid at Seed Layer 109 applied atop photoresist 110(photoresist, can also be film like), by using egative film to carry out para-position exposure in litho machine, make to manifest on photoresist 110 figure of making electroplating line 111 through techniques such as developments.Use electric plating method, the graphics field manifested formed electroplating line 111(and i.e. reroutes structure), electroplating line 111 needs to electrically connect chip bonding pad 106.
8th step, as it is shown in figure 9, remove the Seed Layer 109 bottom photoresist 110 and photoresist, retains the Seed Layer 109 bottom electroplating line 111；Carrying tablet 101 coats one layer of Equations of The Second Kind photosensitive resin 104 again so that the Equations of The Second Kind photosensitive resin 104 on upper strata covers electroplating line 111；
Then use egative film to carry out para-position exposure in litho machine, through techniques such as developments, the Equations of The Second Kind photosensitive resin 104 on upper strata manifests the metal pad 112 on electroplating line 111.The Equations of The Second Kind photosensitive resin 104 used in this step is identical with used in the 3rd step.
9th step, as shown in Figure 10, on metal pad 112 by plant ball, print, electroplate, the technique such as chemical plating forms soldered ball 113.
Claims (7)
1. the manufacture method of a fan-out square chip level package, it is characterised in that comprise the steps:
The first step, it is provided that carrying tablet (101), pastes adhesive glue (102) on carrying tablet (101)；
Second step, is just being attached to chip (103) in adhesive glue (102)；
3rd step, carrying tablet (101) posts and in the side of chip (103), coats Equations of The Second Kind photosensitive resin (104), Equations of The Second Kind photosensitive resin (104) includes solder mask, photosensitive green paint or dry film, and chip (103) is covered by Equations of The Second Kind photosensitive resin (104)；
4th step, removes the Equations of The Second Kind photosensitive resin (104) in more than the active graphical region in chip (103) front, the active graphical region of exposed chip (103) so that outside chip bonding pad (106) is exposed to；
5th step, posts on carrying tablet (101) and coats first kind photosensitive resin (107) in the side of chip (103), and first kind photosensitive resin (107) includes BCB, PBO or PSPI；The active graphical region overlay that chip (103) is exposed by first kind photosensitive resin (107)；
6th step, forms the via (108) leading to chip bonding pad (106) in first kind photosensitive resin (107)；
7th step, neutralizes first kind photosensitive resin (107) one layer of Seed Layer (109) of upper deposition at via (108)；Seed Layer (109) coats photoresist (110), then make to manifest on photoresist (110) figure for making electroplating line (111), use electric plating method, the graphics field manifested is formed the electroplating line (111) of electrical connection chip bonding pad (106)；
8th step, removes the Seed Layer (109) bottom photoresist (110) and photoresist, retains the Seed Layer (109) of electroplating line (111) bottom；Carrying tablet (101) coats one layer of Equations of The Second Kind photosensitive resin (104) again so that the Equations of The Second Kind photosensitive resin (104) on upper strata covers electroplating line (111)；
Then on the Equations of The Second Kind photosensitive resin (104) on upper strata, manifest the metal pad (112) on electroplating line (111)；
9th step, forms soldered ball (113) on metal pad (112).
2. the manufacture method of fan-out square chip level package as claimed in claim 1, it is characterised in that:
In the described first step, carrying tablet (101) is rectangle, and material is glass, metallic plate or organic substrate.
3. the manufacture method of fan-out square chip level package as claimed in claim 1, it is characterised in that:
In described 3rd step, the technique of coating Equations of The Second Kind photosensitive resin (104) includes spin coating, spraying, roller coating, silk screen printing, slot coated, inkjet printing, rolling or vacuum pressing-combining.
4. the manufacture method of fan-out square chip level package as claimed in claim 1, it is characterised in that:
In described 4th step, specifically by para-position exposure technology in exposure machine, make Equations of The Second Kind photosensitive resin (104) react, use developer solution to be removed by Equations of The Second Kind photosensitive resin (104) more than the active graphical region in chip (103) front.
5. the manufacture method of fan-out square chip level package as claimed in claim 1, it is characterised in that:
In described 5th step, the technique of coating first kind photosensitive resin (107) includes spin coating, spraying, roller coating, silk screen printing, slot coated, inkjet printing, rolling or vacuum pressing-combining.
6. the manufacture method of fan-out square chip level package as claimed in claim 1, it is characterised in that:
In described 7th step, by splash-proofing sputtering metal or electroless copper plating technique, neutralize the upper deposited seed layer (109) of first kind photosensitive resin (107) at via (108).
7. the manufacture method of fan-out square chip level package as claimed in claim 1, it is characterised in that:
In described 9th step, by plant ball, print, electroplate or chemical plating process formed soldered ball (113).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410045787.3A CN103745936B (en) | 2014-02-08 | 2014-02-08 | The manufacture method of fan-out square chip level package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410045787.3A CN103745936B (en) | 2014-02-08 | 2014-02-08 | The manufacture method of fan-out square chip level package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103745936A CN103745936A (en) | 2014-04-23 |
| CN103745936B true CN103745936B (en) | 2016-08-17 |
Family
ID=50502946
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410045787.3A Active CN103745936B (en) | 2014-02-08 | 2014-02-08 | The manufacture method of fan-out square chip level package |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103745936B (en) |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104103528A (en) * | 2014-07-22 | 2014-10-15 | 华进半导体封装先导技术研发中心有限公司 | Fan out type square piece level semiconductor three dimension chip packaging technology |
| CN105023888B (en) * | 2015-07-08 | 2018-01-16 | 华进半导体封装先导技术研发中心有限公司 | Plate level fan-out-type chip package device and preparation method thereof |
| CN104966677B (en) * | 2015-07-08 | 2018-03-16 | 华进半导体封装先导技术研发中心有限公司 | Fan-out-type chip package device and preparation method thereof |
| CN105206539A (en) * | 2015-09-01 | 2015-12-30 | 华进半导体封装先导技术研发中心有限公司 | Fan-out package preparation method |
| CN105161432A (en) * | 2015-09-17 | 2015-12-16 | 中芯长电半导体（江阴）有限公司 | Chip packaging method |
| CN105225973A (en) * | 2015-11-05 | 2016-01-06 | 南通富士通微电子股份有限公司 | Method for packing |
| CN105401189A (en) * | 2015-11-13 | 2016-03-16 | 华进半导体封装先导技术研发中心有限公司 | Method for improving electroplating uniformity of package substrate |
| CN108346587A (en) * | 2017-01-25 | 2018-07-31 | 新加坡有限公司 | Chip package device and packaging method |
| WO2018165819A1 (en) * | 2017-03-13 | 2018-09-20 | 深圳修远电子科技有限公司 | Circuit line connection method |
| WO2018165818A1 (en) * | 2017-03-13 | 2018-09-20 | 深圳修远电子科技有限公司 | Circuit fanning out method |
| CN111952201B (en) * | 2020-07-14 | 2022-02-18 | 珠海越亚半导体股份有限公司 | Manufacturing method of embedded packaging substrate |
| CN111863719B (en) * | 2020-07-28 | 2022-07-19 | 南通通富微电子有限公司 | Chip interconnection method |
| CN111863717B (en) * | 2020-07-28 | 2022-07-15 | 南通通富微电子有限公司 | Chip interconnection method |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1866504A (en) * | 2005-05-17 | 2006-11-22 | 矽品精密工业股份有限公司 | Semiconductor device and making method thereof |
| CN101320716A (en) * | 2007-06-08 | 2008-12-10 | 日本电气株式会社 | Semiconductor device and method for manufacturing same |
| CN101527266A (en) * | 2008-03-06 | 2009-09-09 | 钰桥半导体股份有限公司 | Manufacture method for layer-adding circuit board |
| CN102074551A (en) * | 2009-11-19 | 2011-05-25 | 日月光半导体制造股份有限公司 | Semiconductor device packages and manufacturing method thereof |
| CN202003990U (en) * | 2011-01-31 | 2011-10-05 | 江阴长电先进封装有限公司 | Low-cost chip fan-out structure |
| CN102214641A (en) * | 2010-04-02 | 2011-10-12 | 日月光半导体制造股份有限公司 | Wafer-level semiconductor device packages with stacking functionality |
| CN103383923A (en) * | 2012-03-08 | 2013-11-06 | 新科金朋有限公司 | Thin 3d fan-out embedded wafer level package (ewlb) for application processor and memory integration |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005039017A (en) * | 2003-07-18 | 2005-02-10 | Hitachi Ltd | Method for manufacturing semiconductor device and wiring board |
| JP5326281B2 (en) * | 2006-01-06 | 2013-10-30 | ルネサスエレクトロニクス株式会社 | Semiconductor mounting wiring board, manufacturing method thereof, and semiconductor package |
-
2014
- 2014-02-08 CN CN201410045787.3A patent/CN103745936B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1866504A (en) * | 2005-05-17 | 2006-11-22 | 矽品精密工业股份有限公司 | Semiconductor device and making method thereof |
| CN101320716A (en) * | 2007-06-08 | 2008-12-10 | 日本电气株式会社 | Semiconductor device and method for manufacturing same |
| CN101527266A (en) * | 2008-03-06 | 2009-09-09 | 钰桥半导体股份有限公司 | Manufacture method for layer-adding circuit board |
| CN102074551A (en) * | 2009-11-19 | 2011-05-25 | 日月光半导体制造股份有限公司 | Semiconductor device packages and manufacturing method thereof |
| CN102214641A (en) * | 2010-04-02 | 2011-10-12 | 日月光半导体制造股份有限公司 | Wafer-level semiconductor device packages with stacking functionality |
| CN202003990U (en) * | 2011-01-31 | 2011-10-05 | 江阴长电先进封装有限公司 | Low-cost chip fan-out structure |
| CN103383923A (en) * | 2012-03-08 | 2013-11-06 | 新科金朋有限公司 | Thin 3d fan-out embedded wafer level package (ewlb) for application processor and memory integration |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103745936A (en) | 2014-04-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103745936B (en) | The manufacture method of fan-out square chip level package | |
| CN105206592B (en) | The structure and production method of fan-out package | |
| CN103745937B (en) | The manufacture craft of fan-out wafer level package | |
| CN102339809B (en) | QFN (quad flat non-lead) package with multiple circles of pins and manufacturing method thereof | |
| US9362173B2 (en) | Method for chip package | |
| US20090218669A1 (en) | Multi-chip package structure and method of fabricating the same | |
| CN105047652A (en) | Semiconductor device packaging structure and manufacturing method thereof | |
| CN105244341A (en) | Semiconductor device FOWLP packaging structure and manufacturing method thereof | |
| CN104103528A (en) | Fan out type square piece level semiconductor three dimension chip packaging technology | |
| US20060252248A1 (en) | Method for fabricating electrically connecting structure of circuit board | |
| JP3972246B2 (en) | Wafer level chip size package and manufacturing method thereof | |
| CN103985647B (en) | Method for preparing copper cylinder salient points | |
| CN103745938B (en) | The manufacture method of fan-out wafer level package | |
| CN102034720A (en) | Chip packaging method | |
| TWI264253B (en) | Method for fabricating conductive connection structure of circuit board | |
| CN105140140A (en) | Novel wafer level tin solder micro bump manufacturing method | |
| CN102354689A (en) | Quad flat non-lead (QFN) package with leads arranged in plane array and manufacturing method | |
| TW201844065A (en) | Circuit board structure and method for fabricating the same | |
| CN103762183B (en) | Manufacturing technology for fan-out-type square chip level packaging | |
| CN210040131U (en) | Rewiring layer | |
| TW202036812A (en) | Semiconductor device packaging method and semiconductor device capable of improving the parameter stability of the packaged product and increasing the yield | |
| CN104103527B (en) | A kind of improved fan-out square chip level semiconductor die package technique | |
| KR20160001827A (en) | Method for manufacturing a circuit board | |
| JP6290987B2 (en) | Semiconductor package substrate and manufacturing method thereof | |
| CN104103526B (en) | A kind of improved fan-out square chip level 3 D semiconductor chip package process |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| EE01 | Entry into force of recordation of patent licensing contract | ||
| EE01 | Entry into force of recordation of patent licensing contract |
Application publication date: 20140423 Assignee: Huajin semiconductor (Jiashan) Co.,Ltd. Assignor: National Center for Advanced Packaging Co.,Ltd. Contract record no.: X2021980017402 Denomination of invention: Manufacturing method of fan out square chip level package Granted publication date: 20160817 License type: Exclusive License Record date: 20220111 |