CN106887393B - It is integrated with the packaging method of the encapsulating structure of power transmission chip - Google Patents
It is integrated with the packaging method of the encapsulating structure of power transmission chip Download PDFInfo
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- CN106887393B CN106887393B CN201710172468.2A CN201710172468A CN106887393B CN 106887393 B CN106887393 B CN 106887393B CN 201710172468 A CN201710172468 A CN 201710172468A CN 106887393 B CN106887393 B CN 106887393B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11803—Masterslice integrated circuits using field effect technology
- H01L27/11807—CMOS gate arrays
- H01L2027/11892—Noise prevention (crosstalk)
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
- H01L2224/82001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] involving a temporary auxiliary member not forming part of the bonding apparatus
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
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- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Abstract
The present invention provides a kind of packaging method for the encapsulating structure being integrated with power transmission chip, and the encapsulating structure includes with electrical chip and being connected to the power transmission chips of the electricity consumption beneath chips；The power transmission chip is used to the voltage of external power supply being converted into multiple voltages with needed for electrical chip, and provides a plurality of docking the power supply rail with electrical chip.The packaging method of the present invention will be integrated on active 2.5D intermediate plates with electrical chip 5 by dimpling block or other projection cube structures using the power transmission chip 3 as active 2.5D intermediate plates, obtain three-dimensional stacked chip structure.The power transmission system of whole system circuit board is realized by the power transmission chip, can eliminate the dead resistance on package substrate, to improve power transmission efficiency, is improved the response time of power control, and fidelity is improved.
Description
Technical field
The invention belongs to technical field of semiconductor encapsulation, are related to a kind of envelope for the encapsulating structure being integrated with power transmission chip
Dress method.
Background technology
All calculating and communication system are required for power transmission system.Power transmission system can turn the high voltage of power supply
Change many different low-voltages needed for discrete devices in system into.The efficiency of power transmission system determines the electricity converted downwards
Power is lost, and power transmission rail number determines the quantity of supported discrete voltage supply or device.
Current power transmission techniques are faced with following challenge：
One, as the contraction of process node, device voltage reduce, the efficiency of power transmission can decrease, and power is made to disappear
Consume bigger.
Two, more power transmission tracks are added to need to replicate more power transmission components, number of elements can be increased, increased
Large circuit board size, increases system bulk, cost and weight at the number of plies for increasing circuit board.
Three, it due to the limitation of the line-spacing of wiring layer, line width again, needs to increase package dimension.
Therefore, power transmission efficiency how is improved, increases the quantity available of different voltages track, it has also become art technology
Personnel's important technological problems urgently to be resolved hurrily.
Invention content
In view of the foregoing deficiencies of prior art, the purpose of the present invention is to provide one kind being integrated with power transmission chip
Encapsulating structure packaging method, the power transmission efficiency for solving existing power transmission system is low, different voltages track
The few problem of quantity available.
In order to achieve the above objects and other related objects, the present invention provides a kind of encapsulation knot being integrated with power transmission chip
The packaging method of structure, the encapsulating structure include with electrical chip and being connected to the power transmission chips of the electricity consumption beneath chips；
The power transmission chip is used to the voltage of external power supply being converted into multiple voltages with needed for electrical chip, and provides more
Item docks the power supply rail with electrical chip；The packaging method includes the following steps：
One carrier is provided, and forms adhesion layer on the carrier；
The active component of the power transmission chip and passive element are positioned on the adhesion layer, wherein described to have
Source element and passive element have the one side of pad upward；
Form the plastic packaging layer for covering the active component and passive element on the adhesion layer, and to the plastic packaging layer into
Row grinding, to expose the pad；
It is formed above and below multiple and runs through the through-hole of the plastic packaging layer, and conductive material is filled in the through-hole, obtain conduction
Column；
The wiring layer again of the power transmission chip is formed on the plastic packaging layer；The current-carrying part of the wiring layer again with
The conductive column and the pad connection, realize being electrically connected between the active component and passive element, and provide it is a plurality of right
Connect the power supply rail with electrical chip；
It is connect described with the wiring layer again with electrical chip by multiple first projection cube structures, realization is described to use electrical chip
With docking for a plurality of power supply rail；
The carrier and adhesion layer are removed, the conductive column lower surface is exposed；
Form multiple the second projection cube structures being connect with the conductive column.
Optionally, the voltage of the external power supply is higher than the voltage with needed for electrical chip.
Optionally, the active component includes controller and buck converter；The passive element include capacitance, inductance and
Resistance.
Optionally, it after wiring layer is connect again, is also wrapped described with described with electrical chip by multiple first projection cube structures
It includes and is filled up by underfill described with electrical chip and described between wiring layer the step of gap, and pass through capsulation material
By it is described with being wrapped up around electrical chip the step of.
Optionally, the wiring layer again include dielectric layer and at least one layer of metal connecting line being formed in the dielectric layer and
At least one layer of conductive plugs；The metal connecting line is realized and the active component, passive element and conductive column by the conductive plugs
Electrical connection, and when being formed with multiple layer metal line in the dielectric layer, pass through the conductive plugs between multiple layer metal line
Realize interlayer electrical connection.
Optionally, first projection cube structure includes dimpling block.
Optionally, second projection cube structure includes ball grid array soldered ball.
Optionally, described with electrical chip is application-specific integrated circuit.
Optionally, the method for forming the plastic packaging layer includes compression forming, transfer modling, fluid-tight molding, vacuum lamination, rotation
Any one or more in painting.
Optionally, the method for forming the through-hole includes laser boring, machine drilling, reactive ion etching, nano impression
In any one or more.
Optionally, the method for forming the conductive column includes one kind or more in plating, chemical plating, silk-screen, wire bonding
Kind.
As described above, the present invention provides a kind of new packaging methods, electrical chip will be used using three-dimensional chip Stack Technology
With power transmission integrated chip in an encapsulating structure, have the advantages that：
(1) active 2.5D intermediate plates are formed using existing active component and passive element, then by dimpling block or its
Electricity consumption integrated chip on active 2.5D intermediate plates, is obtained three-dimensional stacking structure by its projection cube structure；Wherein, described to use electrical chip
Can be application-specific integrated circuit (Application Specific Integrated Circuit, abbreviation ASIC).
(2) in three-dimensional stacking structure, active 2.5D intermediate plates as power transmission power chip, be closely integrated in
Below electrical chip, solves the problems, such as power transmission.
(3) power transmission system of whole system circuit board is realized by the power transmission chip, the power transmission core
Piece includes controller, buck converter (buck converter), capacitor (CAP (3T)), inductance (L (2T)) and resistance, from
And eliminate passive element all on system board.
(4) buck converter in the power transmission chip can generate thousands of low-voltage power transmission tracks
(power supply rail), these low-voltage power transmission tracks pass through dimpling block docking electrical chip.
(5) encapsulating structure of the invention includes the power transmission chip of passive element due to being integrated with, and can eliminate encapsulation
Dead resistance on substrate such as pcb board improves the response time of power control to improve power transmission efficiency.
(6) fidelity is improved by reducing pressure drop and noise, so as to improve the response time.Due to needing less set
Surplus is counted, better fidelity performance improvement can be obtained.
Description of the drawings
Fig. 1 is shown as the process flow chart of the packaging method of the encapsulating structure for being integrated with power transmission chip of the present invention.
The packaging method that Fig. 2 is shown as the encapsulating structure for being integrated with power transmission chip of the present invention provides showing for a carrier
It is intended to.
Fig. 3 is shown as the packaging method shape on the carrier of the encapsulating structure for being integrated with power transmission chip of the present invention
At the schematic diagram of adhesion layer.
Fig. 4 is shown as the packaging method of the encapsulating structure for being integrated with power transmission chip of the present invention by the power transmission
The active component of chip is positioned over the schematic diagram on the adhesion layer with passive element.
Fig. 5 is shown as the packaging method of the encapsulating structure for being integrated with power transmission chip of the present invention on the adhesion layer
Form the schematic diagram of plastic packaging layer.
Fig. 6 is shown as the packaging method of the encapsulating structure for being integrated with power transmission chip of the present invention in the plastic packaging layer
Form the schematic diagram of conductive column.
The packaging method that Fig. 7 is shown as the encapsulating structure for being integrated with power transmission chip of the present invention forms the power biography
The schematic diagram of the wiring layer again of defeated chip.
The packaging method that Fig. 8 is shown as the encapsulating structure for being integrated with power transmission chip of the present invention is convex by multiple first
Block structure is connect with the wiring layer again by described with electrical chip, and by underfill fill up the use electrical chip with it is described
The schematic diagram in gap between wiring layer.
The packaging method that Fig. 9 is shown as the encapsulating structure for being integrated with power transmission chip of the present invention will by capsulation material
It is described with the schematic diagram wrapped up around electrical chip.
The packaging method that Figure 10 is shown as the encapsulating structure for being integrated with power transmission chip of the present invention removes the carrier
And the schematic diagram of adhesion layer.
The packaging method that Figure 11 is shown as the encapsulating structure for being integrated with power transmission chip of the present invention forms multiple and institute
State the schematic diagram of the second projection cube structure of conductive column connection.
Component label instructions
S1~S8 steps
1 carrier
2 adhesion layers
3 power transmission chips
301 active components
302 passive elements
3021 capacitances
3022 inductance
303 pads
304 plastic packaging layers
305 conductive columns
306 wiring layers again
3061 dielectric layers
3062 metal connecting lines
3063 conductive plugs
4 first projection cube structures
5 use electrical chip
6 underfills
7 capsulation materials
8 second projection cube structures
Specific implementation mode
Illustrate that embodiments of the present invention, those skilled in the art can be by this specification below by way of specific specific example
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also be based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under the spirit of the present invention.
It please refers to Fig.1 to Figure 11.It should be noted that the diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of invention, package count when only display is with related component in the present invention rather than according to actual implementation in schema then
Mesh, shape and size are drawn, when actual implementation kenel, quantity and the ratio of each component can be a kind of random change, and its
Assembly layout kenel may also be increasingly complex.
The present invention provides a kind of packaging method for the encapsulating structure being integrated with power transmission chip.Please refer to Fig.1 1, it is described
Encapsulating structure includes with electrical chip 5 and the power transmission chip 3 being connected to below the electrical chip 5；The power transmission core
Piece 3 is used to the voltage of external power supply being converted into multiple voltages with needed for electrical chip 5, and provides a plurality of docking use
The power supply rail of electrical chip 5.The packaging method of the present invention is led to using the power transmission chip 3 as active 2.5D intermediate plates
Crossing dimpling block or other projection cube structures will be integrated on active 2.5D intermediate plates with electrical chip 5, obtain three-dimensional stacked chip structure.
The power transmission system of whole system circuit board is realized by the power transmission chip, can eliminate the parasitism electricity on package substrate
Resistance, to improve power transmission efficiency, improves the response time of power control, improves fidelity.
In the present embodiment, the power transmission chip 3 includes active component 301, passive element 302, plastic packaging layer 304, leads
Electric column 305 and again wiring layer 306.
Referring to Fig. 1, being shown as the technique of the packaging method of the encapsulating structure for being integrated with power transmission chip of the present invention
Flow chart includes the following steps：
S1：One carrier is provided, and forms adhesion layer on the carrier；
S2：The active component of the power transmission chip and passive element are positioned on the adhesion layer, wherein described
Active component and passive element have the one side of pad upward；
S3：The plastic packaging layer for covering the active component and passive element is formed on the adhesion layer, and to the plastic packaging
Layer is ground, to expose the pad；
S4：It is formed above and below multiple and runs through the through-hole of the plastic packaging layer, and conductive material is filled in the through-hole, led
Electric column；
S5：The wiring layer again of the power transmission chip is formed on the plastic packaging layer；The conductive part of the wiring layer again
Divide and connect with the conductive column and the pad, realizes being electrically connected between the active component and passive element, and provide more
Item docks the power supply rail with electrical chip；
S6：It is connect described with the wiring layer again with electrical chip by multiple first projection cube structures, realizes the electricity consumption
Chip is docked with a plurality of power supply rail；
S7：The carrier and adhesion layer are removed, the conductive column lower surface is exposed；
S8：Form multiple the second projection cube structures being connect with the conductive column.
Referring initially to Fig. 2 and Fig. 3, step S1 is executed：One carrier 1 is provided, and forms adhesion layer 2 on this carrier 1.
Specifically, the material of the carrier can selected from one or more in glass, silicon, silica, metal or ceramics,
Or other analogs.The carrier 1 can be plate, for example, have certain thickness glass circle tablet.
Specifically, the effect of the adhesion layer 2 is to be adhered fixed element placed thereon, the carrier 1 is subsequently removed
When, the adhesion layer 2 is also removed together.
As an example, the adhesion layer 2 can be UV adhesive tapes or hot material, wherein the UV adhesive tapes are in specific wavelength
Under illumination, adhesion strength can reduce so that carrier is easily peeled off.The hot material is under certain heating temperature, adhesion strength meeting
It reduces so that carrier is easily peeled off.Certainly, the adhesion layer 2 can also use the combination of UV glue and hot material.
Referring next to Fig. 4, step S2 is executed：By the active component 301 and passive element of the power transmission chip 3
302 are positioned on the adhesion layer 2, wherein the active component 301 and passive element 302 have the one of pad 303 to face
On.
In general, there is the active component 301 one side of pad 303 to be referred to as front, another side on the other side is referred to as
For the back side.For the passive element 302, and so.In the present embodiment, be by active component 301 and passive element 302 just
It is positioned on the adhesion layer 2, is fixed on the carrier to paste up.
Specifically, sticking bonding die film (Die Attach Film, letter in the chip back surface comprising multiple bare dies (Die) first
Write DFA), or bonding die film is not pasted, then scribing obtains multiple independent bare dies (the i.e. described active component 301 or passive element
302) bare die, is then picked up, is positioned on the adhesion layer 2, the bare die is made to be temporarily fixed on the carrier 1.Bonding die film
Can be UV films, using the illumination of specific wavelength/can reduce the adhesion strength of film to film heating after cut crystal so that
Chip is easy to remove from film.
Specifically, the effect of the power transmission chip 3 is that the voltage of external power supply is converted into 5 institute of electrical chip
The multiple voltages needed, and provide a plurality of docking the power supply rail with electrical chip 5.As an example, the electricity of the external power supply
Pressure is higher than the voltage with needed for electrical chip, is referred to as below high voltage by the voltage of external power supply, needed for title electrical chip
Voltage is low-voltage.
As an example, the active component 301 includes controller and buck converter；The passive element 302 includes electricity
Hold 3021, inductance 3021 and resistance (not shown).In the power transmission chip, buck converter can be transformed to high voltage
Thousands of low-voltage, these low-voltages can by the conductive column that is subsequently formed, wiring layer constitutes multiple power supply rails again, and
It is docked with top with electrical chip by the first projection cube structure being subsequently formed.
Then referring to Fig. 5, executing step S3：Formed on the adhesion layer 2 cover the active component 301 with it is passive
The plastic packaging layer 304 of element 302, and the plastic packaging layer is ground, to expose the pad 303, (thinning process is not schemed
Show).
Specifically, the method for forming the plastic packaging layer 304 includes compression forming, transfer modling, fluid-tight molding, vacuum layer
Any one or more in pressure, spin coating or other suitable methods.Capsulation material includes epoxylite, liquid-type thermosetting
The suitable materials such as property epoxy resin, plastics.
As an example, process of lapping may be used mechanical milling tech, surface with chemical polishing technology, etch process, its arbitrary group
Conjunction and/or similar technique.
Again referring to Fig. 6, executing step S4：Multiple through-holes for running through the plastic packaging layer 304 up and down are formed, and described logical
Conductive material is filled in hole, obtains conductive column 305.
Specifically, the through-hole (Through Active-interposer Via, abbreviation TAV) can be beaten by laser
Any one or more in hole, machine drilling, reactive ion etching, nano impression or other suitable methods making.Through-hole
Packing material can be solder or copper.TAV fillings can be by any one in plating, chemical plating, silk-screen, wire bonding or more
Kind or other suitable metal deposition process are formed.
Again referring to Fig. 7, executing step S5：Connecting up again for the power transmission chip 3 is formed on the plastic packaging layer 304
Layer 306；The current-carrying part of the wiring layer again 306 is connect with the conductive column 305 and the pad 303, is realized described active
Being electrically connected between element 301 and passive element 302, and provide a plurality of docking the power supply rail with electrical chip 5.
Connect specifically, the wiring layer again includes dielectric layer 3061 and at least one layer of metal being formed in the dielectric layer
Line 3062 and at least one layer of conductive plugs 3063；The metal connecting line 3062 by the conductive plugs 3063 realize with it is described active
The electrical connection of element 301, passive element 302 and conductive column 305, and work as in the dielectric layer 3061 and be formed with multiple layer metal line
When 3062, interlayer electrical connection is realized by the conductive plugs 3063 between multiple layer metal line 3062.
As an example, the material of the metal connecting line 3062 include one kind in Cu, Al, Ag, Au, Sn, Ni, Ti, Ta or
A variety of or other suitable conductive metallic materials.For example, the metal connecting line 3062 can be Cu lines, the seed of Cu lines is made
Layer can be Ti/Cu layers.The method for forming the metal connecting line 182 may include one be electrolysed in plating, chemical plating, silk-screen printing
Kind or a variety of or other suitable metal deposition process.Laser drill can be first passed through, machine drilling, reactive ion etching, received
Rice coining or other suitable boring methods form through-hole in the dielectric layer 3061, then fill metal in the through-hole again
Material can form the conductive plugs 3063；The material of the conductive plugs 3063 can be solder or Cu, and fill method can be
It is electrolysed plating, chemical plating, silk-screen printing, wire bonding or other suitable methods for filling conductive material in through-holes.
Again referring to Fig. 8, executing step S6：By multiple first projection cube structures 4 electrical chip 5 and the cloth again are used by described
Line layer connects, and realizes the docking with electrical chip 5 and a plurality of power supply rail.
Specifically, the including but not limited to application-specific integrated circuit naked core (ASIC Die) of electrical chip 5.Described first is convex
Dimpling block (mico-bump) or other suitable projection cube structures may be used in block structure 4.
As an example, the techniques such as ultrasonic bond, thermocompression bonding or common Reflow Soldering may be used uses electrical chip 5 by described
It is welded on the wiring layer 306 again via multiple first projection cube structures 4.
In the present embodiment, by multiple first projection cube structures by it is described with electrical chip with described after wiring layer is connect again,
Further include the steps that electrical chip 5 and the gap between wiring layer 306 are filled up by underfill.Underfill
Glue is exactly the justice of underfill in simple terms, usual definition be it is a kind of with chemical glue (main ingredient is epoxy resin) to chip
Underfill is carried out, using the cured form of heating, chip bottom gap large area (80% or more general covering) is filled up, from
And achieve the purpose that reinforcing, enhance the anti-dropping capability of encapsulating structure.
As an example, bottom filling method, which can be capillary, fills (capillary underfill) or molding filling
(Molding UnderFill, abbreviation MUF).Wherein, capillary filling is to make glue rapidly flow through chip bottom using capillarity
The minimum space in portion, capillary flow is 10um.This has also complied with minimum electrical between pad and solder ball in welding procedure
Characteristic requirements have ensured the electrical safety characteristic of welding procedure because glue is the gap not flowed through less than 4um.
Again referring to Fig. 9, further including the steps that being wrapped up described with 5 surrounding of electrical chip by capsulation material 7.
Again referring to Fig. 10, executing step S7：The carrier 1 and adhesion layer 2 are removed, is exposed under the conductive column 305
Surface.
Specifically, mechanical lapping, chemical polishing, etching, ultraviolet light stripping, one kind in mechanical stripping or more may be used
Kind removes the carrier 1；It preferably, can be by removing the adhesion layer 2 to remove the carrier 1 in the present embodiment.
1 is finally please referred to Fig.1, step S8 is executed：Form multiple the second projection cube structures 8 being connect with the conductive column.
As an example, second projection cube structure includes ball grid array (Ball Grid Array, BGA) soldered ball.
Specifically, the encapsulating structure can be combined by second projection cube structure with package substrate, the encapsulation base
Plate can be pcb board (Printed Circuit Board, printed circuit board) or other suitable packaging parts.External power supply electricity
Pressure can be applied on the power transmission chip by the package substrate, and be converted into using by the power transmission chip
Multiple voltages needed for electrical chip, these transformed voltages pass through a plurality of power supply rail in the power transmission chip in turn
It is applied to on electrical chip.The encapsulating structure of the present invention includes the power transmission chip of passive element due to being integrated with, and can disappear
Except the dead resistance on package substrate such as pcb board, to improve power transmission efficiency, improve the response time of power control,
Improve fidelity.
In conclusion the present invention provides a kind of new packaging methods, electrical chip will be used using three-dimensional chip Stack Technology
With power transmission integrated chip in an encapsulating structure, have the advantages that：(1) existing active component and nothing are used
Source element forms active 2.5D intermediate plates, then by dimpling block or other projection cube structures by electricity consumption integrated chip in active 2.5D
On intermediate plate, three-dimensional stacking structure is obtained；Wherein, described with electrical chip can be application-specific integrated circuit (Application
Specific Integrated Circuit, abbreviation ASIC).(2) in three-dimensional stacking structure, active 2.5D intermediate plates conduct
Power transmission power chip is closely integrated in electricity consumption beneath chips, solves the problems, such as power transmission.(3) whole system electricity
The power transmission system of road plate is realized that the power transmission chip includes controller, decompression transformation by the power transmission chip
Device (buck converter), capacitor (CAP (3T)), inductance (L (2T)) and resistance, it is all on system board to eliminate
Passive element.(4) buck converter in the power transmission chip can generate thousands of low-voltage power transmission tracks
(power supply rail), these low-voltage power transmission tracks pass through dimpling block docking electrical chip.(5) encapsulating structure of the invention by
In being integrated with the power transmission chip for including passive element, the dead resistance on package substrate such as pcb board can be eliminated, to
Power transmission efficiency is improved, the response time of power control is improved.(6) fidelity is improved by reducing pressure drop and noise
Degree, so as to improve the response time.Due to needing less design margin, better fidelity performance improvement can be obtained.Institute
With the present invention effectively overcomes various shortcoming in the prior art and has high industrial utilization.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe
The personage for knowing this technology can all carry out modifications and changes to above-described embodiment without violating the spirit and scope of the present invention.Cause
This, institute is complete without departing from the spirit and technical ideas disclosed in the present invention by those of ordinary skill in the art such as
At all equivalent modifications or change, should by the present invention claim be covered.
Claims (9)
1. a kind of packaging method for the encapsulating structure being integrated with power transmission chip, which is characterized in that the encapsulating structure includes
With electrical chip and it is connected to the power transmission chips of the electricity consumption beneath chips；The power transmission chip is used for external power supply
Voltage be converted into multiple voltages with needed for electrical chip, and provide a plurality of docking the power supply rail with electrical chip；
The packaging method includes the following steps：
One carrier is provided, and forms adhesion layer on the carrier；
The active component of the power transmission chip and passive element are positioned on the adhesion layer, wherein the active member
Part and passive element have the one side of pad upward；
The plastic packaging layer for covering the active component and passive element is formed on the adhesion layer, and the plastic packaging layer is ground
Mill, to expose the pad；
It is formed above and below multiple and runs through the through-hole of the plastic packaging layer, and conductive material is filled in the through-hole, obtain conductive column；
The wiring layer again of the power transmission chip is formed on the plastic packaging layer, the wiring layer again includes dielectric layer and formation
At least one layer of metal connecting line in the dielectric layer and at least one layer of conductive plugs；The metal connecting line passes through conductive plugs reality
It is now electrically connected with the active component, the pad of passive element and conductive column, and when being formed with multilayer gold in the dielectric layer
When belonging to line, interlayer electrical connection is realized by the conductive plugs, and a plurality of docking electricity consumption is provided between multiple layer metal line
The power supply rail of chip；
It is connect, is realized described with electrical chip and more with the wiring layer again with electrical chip by described by multiple first projection cube structures
The docking of power supply rail described in item；
The carrier and adhesion layer are removed, the conductive column lower surface is exposed；
Form multiple the second projection cube structures being connect with the conductive column.
2. the packaging method of the encapsulating structure according to claim 1 for being integrated with power transmission chip, it is characterised in that：Institute
The voltage for stating external power supply is higher than the voltage with needed for electrical chip.
3. the packaging method of the encapsulating structure according to claim 1 for being integrated with power transmission chip, it is characterised in that：Institute
It includes controller and buck converter to state active component；The passive element includes capacitance, inductance and resistance.
4. the packaging method of the encapsulating structure according to claim 1 for being integrated with power transmission chip, it is characterised in that：It is logical
Cross multiple first projection cube structures by it is described with electrical chip further include being filled out by underfill after wiring layer is connect again with described
Expire between the electricity consumption chip bottom and the wiring layer again the step of gap, and battery core is used by described by capsulation material
The step of being wrapped up around piece.
5. the packaging method of the encapsulating structure according to claim 1 for being integrated with power transmission chip, it is characterised in that：Institute
It includes dimpling block to state the first projection cube structure；Second projection cube structure includes ball grid array soldered ball.
6. the packaging method of the encapsulating structure according to claim 1 for being integrated with power transmission chip, it is characterised in that：Institute
It is application-specific integrated circuit to state with electrical chip.
7. the packaging method of the encapsulating structure according to claim 1 for being integrated with power transmission chip, it is characterised in that：Shape
Method at the plastic packaging layer include in compression forming, transfer modling, fluid-tight molding, vacuum lamination, spin coating any one or
It is a variety of.
8. the packaging method of the encapsulating structure according to claim 1 for being integrated with power transmission chip, it is characterised in that：Shape
Method at the through-hole include in laser boring, machine drilling, reactive ion etching, nano impression any one or it is more
Kind.
9. the packaging method of the encapsulating structure according to claim 1 for being integrated with power transmission chip, it is characterised in that：Shape
Method at the conductive column includes one or more in plating, chemical plating, silk-screen, wire bonding.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710172468.2A CN106887393B (en) | 2017-03-22 | 2017-03-22 | It is integrated with the packaging method of the encapsulating structure of power transmission chip |
| PCT/CN2017/095419 WO2018171100A1 (en) | 2017-03-22 | 2017-08-01 | Encapsulation method for encapsulation structure with integrated power transmission chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710172468.2A CN106887393B (en) | 2017-03-22 | 2017-03-22 | It is integrated with the packaging method of the encapsulating structure of power transmission chip |
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| CN106887393A CN106887393A (en) | 2017-06-23 |
| CN106887393B true CN106887393B (en) | 2018-10-19 |
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| WO (1) | WO2018171100A1 (en) |
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| CN106887393B (en) * | 2017-03-22 | 2018-10-19 | 中芯长电半导体（江阴）有限公司 | It is integrated with the packaging method of the encapsulating structure of power transmission chip |
| CN108133931B (en) * | 2018-01-29 | 2023-11-07 | 安徽安努奇科技有限公司 | Module structure and manufacturing method thereof |
| WO2019144574A1 (en) * | 2018-01-29 | 2019-08-01 | 安徽安努奇科技有限公司 | Module structure and manufacturing method therefor |
| US11315831B2 (en) | 2019-07-22 | 2022-04-26 | International Business Machines Corporation | Dual redistribution layer structure |
| CN114631179B (en) * | 2019-10-31 | 2023-09-22 | 华为技术有限公司 | Chip stacking and packaging structure, packaging method thereof and electronic equipment |
| WO2021174395A1 (en) * | 2020-03-02 | 2021-09-10 | 华为技术有限公司 | Encapsulation structure and method for manufacturing encapsulation structure |
| CN113990843B (en) * | 2021-10-25 | 2023-06-27 | 上海壁仞智能科技有限公司 | Chip set and manufacturing method thereof |
| CN116153795A (en) * | 2023-04-20 | 2023-05-23 | 广东赛昉科技有限公司 | Multi-chip packaging method |
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| CN1722412A (en) * | 2004-01-07 | 2006-01-18 | 三星电子株式会社 | Dimensional packaged circuit board and the encapsulation and the method thereof that comprise dimensional packaged circuit board |
| CN102157393A (en) * | 2011-03-22 | 2011-08-17 | 南通富士通微电子股份有限公司 | Fan-out high-density packaging method |
| CN102157456A (en) * | 2011-03-23 | 2011-08-17 | 南通富士通微电子股份有限公司 | Three-dimensional system level packaging method |
| CN102176418A (en) * | 2011-03-22 | 2011-09-07 | 南通富士通微电子股份有限公司 | Fan-out system in package (SIP) method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9679873B2 (en) * | 2015-06-18 | 2017-06-13 | Qualcomm Incorporated | Low profile integrated circuit (IC) package comprising a plurality of dies |
| CN106887393B (en) * | 2017-03-22 | 2018-10-19 | 中芯长电半导体（江阴）有限公司 | It is integrated with the packaging method of the encapsulating structure of power transmission chip |
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- 2017-03-22 CN CN201710172468.2A patent/CN106887393B/en active Active
- 2017-08-01 WO PCT/CN2017/095419 patent/WO2018171100A1/en active Application Filing
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1722412A (en) * | 2004-01-07 | 2006-01-18 | 三星电子株式会社 | Dimensional packaged circuit board and the encapsulation and the method thereof that comprise dimensional packaged circuit board |
| CN102157393A (en) * | 2011-03-22 | 2011-08-17 | 南通富士通微电子股份有限公司 | Fan-out high-density packaging method |
| CN102176418A (en) * | 2011-03-22 | 2011-09-07 | 南通富士通微电子股份有限公司 | Fan-out system in package (SIP) method |
| CN102157456A (en) * | 2011-03-23 | 2011-08-17 | 南通富士通微电子股份有限公司 | Three-dimensional system level packaging method |
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| CN106887393A (en) | 2017-06-23 |
| WO2018171100A1 (en) | 2018-09-27 |
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Address after: No.78 Changshan Avenue, Jiangyin City, Wuxi City, Jiangsu Province (place of business: No.9 Dongsheng West Road, Jiangyin City) Patentee after: Shenghejing micro semiconductor (Jiangyin) Co.,Ltd. Address before: No.78 Changshan Avenue, Jiangyin City, Wuxi City, Jiangsu Province Patentee before: SJ Semiconductor (Jiangyin) Corp. |