CN102157456A - Three-dimensional system level packaging method - Google Patents
Three-dimensional system level packaging method Download PDFInfo
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- CN102157456A CN102157456A CN2011100702782A CN201110070278A CN102157456A CN 102157456 A CN102157456 A CN 102157456A CN 2011100702782 A CN2011100702782 A CN 2011100702782A CN 201110070278 A CN201110070278 A CN 201110070278A CN 102157456 A CN102157456 A CN 102157456A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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Abstract
The invention relates to a three-dimensional system level packaging method, which comprises the following steps: providing a carrying board; forming a cementing layer on the carrying board; sticking a chip or a chip and a passive device on the cementing layer; forming a first material sealing layer, and exposing a bonding pad in the chip in a first chip layer or the bonding pads of the chip and the passive device; forming a first micro-through hole in the first material sealing layer; forming first longitudinal metal wiring in the first micro-through hole; forming a first wiring layer on the first material sealing layer; and forming a multi-layer chip layer on the first material sealing layer. Compared with the prior art, the three-dimensional system level packaging method can form a finally packaged product containing an integral system function rather than a single chip function, thereby reducing the interference factors of internal resistance of a system, inductance and the like. In addition, a more complex multi-layer interconnection structure can be formed, and the wafer level packaging with higher degree of integration can be realized.
Description
Technical field
The present invention relates to semiconductor technology, relate in particular to a kind of three dimension system level packaging methods.
Background technology
Wafer-level packaging (Wafer Level Packaging, WLP) technology is that the full wafer wafer is carried out cutting the technology that obtains single finished chip again after the packaging and testing, chip size and nude film after the encapsulation are in full accord.The crystal wafer chip dimension encapsulation technology has thoroughly been overturned conventional package such as ceramic leadless chip carrier (Ceramic Leadless Chip Carrier) and organic leadless chip carrier (Organic Leadless Chip Carrier) isotype, has complied with that market is light day by day, little, short to microelectronic product, thinning and low priceization requirement.It is highly microminiaturized that chip size after crystal wafer chip dimension encapsulation technology encapsulation has reached, chip cost along with chip size reduce significantly reduce with the increase of wafer size.The crystal wafer chip dimension encapsulation technology be IC can be designed, technology that wafer manufacturing, packaging and testing, substrate manufacturing integrate, be the focus and the developing tendency in future of current encapsulation field.
The encapsulation of fan-out wafer is a kind of of wafer-level packaging.For example, the Chinese invention patent application discloses a kind of wafer scale fan-out chip packaging method No. 200910031885.0, comprise following processing step: cover stripping film and thin film dielectrics layer I successively in the carrier disk surfaces, on thin film dielectrics layer I, form litho pattern opening I; Realize the metal electrode be connected with edge of substrate and wiring metal cabling again on figure opening I and surface thereof; At the surface of metal electrode that is connected with edge of substrate, the surface coverage thin film dielectrics layer II of wiring metal cabling surface and thin film dielectrics layer I again, and on thin film dielectrics layer II, form litho pattern opening II; Realize the metal electrode be connected with die terminals at litho pattern opening II; With flip-chip to metal electrode that die terminals is connected after carry out the injection moulding envelope bed of material and solidify, formation has the packaging body of the plastic packaging bed of material; The carrier disk is separated with the packaging body that has the plastic packaging bed of material with stripping film, form the plastic packaging disk; Plant ball and reflux, form solder bumps; The monolithic cutting forms final fan-out chip structure.
The final products of packaged manufacturing only have single chip functions according to the method described above.Realize complete systemic-function as need, need outside final products, add the peripheral circuit that includes various electric capacity, inductance or resistance etc.In addition, said method is not suitable for the manufacturing of the multilayer encapsulating structure with complicated circuit connection yet.
Summary of the invention
The technical problem that the present invention solves is: the three-dimensional systematic wafer encapsulation that how to realize having sandwich construction.
For solving the problems of the technologies described above, the invention provides the three dimension system level packaging methods, comprise step: provide support plate; On support plate, form cementing layer; To comprise chip or comprise chip and the relative one side of the function face of passive device first chip layer is affixed on the described cementing layer; The one side of support plate being posted first chip layer forms the first envelope bed of material, and exposes the pad of the first chip layer chips or the pad of chip and passive device; In the described first envelope bed of material, form first micro through hole; In first micro through hole, form the wiring of first longitudinal metal; On the described first envelope bed of material, form first wiring layer of described first chip layer of conducting and the wiring of first longitudinal metal; Form the multilayer chiop layer on the described first envelope bed of material, every layer of chip layer comprises the envelope bed of material of chip or chip and passive device, the described chipset of covering and passive device group and interconnects also conducting the longitudinal metal wiring and the wiring layer of layers of chips layer up and down.
Alternatively, forming in the multilayer chiop layer arbitrary layer step on the described first envelope bed of material specifically comprises: pile up this layer chip layer that comprises chip or chip and passive device on the last envelope bed of material; On the last envelope bed of material, form to cover this layer chip layer and expose the pad of this layer chip layer chips or this layer envelope bed of material of the pad of chip and passive device; On this layer envelope bed of material, form this layer micro through hole that is communicated with last wiring layer; In this layer micro through hole, form this layer longitudinal metal wiring that connects last wiring layer; On this layer envelope bed of material, form this layer wiring layer of the wiring of this layer of conducting longitudinal metal and this layer chip layer chips or chip and passive device.
Alternatively, also comprise step: in the end form first protective layer that part exposes last one deck wiring layer on one deck envelope bed of material; The metal that formation is communicated with described the 3rd wiring layer on described first protective layer is wiring layer again; On described first protective layer, form part and expose described metal second protective layer of wiring layer again; Described metal again the expose portion of wiring layer form the ball lower metal layer; On described ball lower metal layer, form the metal soldered ball.
Alternatively, also comprise step: in the end form first protective layer that part exposes last one deck wiring layer on one deck envelope bed of material; Expose portion at described last one deck wiring layer forms the ball lower metal layer; On described ball lower metal layer, form the metal soldered ball.
Alternatively, the material that forms described protective layer is a polyimides.
Alternatively, described passive device group comprises electric capacity, resistance and/or inductance.
Alternatively, the material of the envelope bed of material is an epoxy resin.
Alternatively, the envelope bed of material forms by metaideophone, compression or method of printing.
Alternatively, the chip in the chip layer is one or more identical or different chips.
Compared with prior art; the three dimension system level packaging methods that the present invention asks for protection; encapsulation in the lump again after chip and passive device integrated; can form and comprise the total system function but not the final encapsulating products of single chip functions; compare the encapsulation of existing systems level; the wafer level packaging of high integration has reduced disturbing factor such as resistance, inductance in the system especially, also more can comply with the compact trend requirement of semiconductor packages.
In addition, the three dimension system level packaging methods that the present invention asks for protection can form the stereo encapsulation structure of being made up of the multilayer chiop group, and the wiring layer between each layer connects by being formed on the micro through hole that respectively seals on the bed of material.Therefore can make than multiple level interconnect architecture more complicated in the prior art, realize the higher wafer level packaging of integrated level.
Description of drawings
Fig. 1 and Fig. 2 are three dimension system level packaging methods flow chart in the one embodiment of the invention;
Fig. 3 to Fig. 9 is an encapsulating structure schematic diagram in the flow process illustrated in figures 1 and 2.
Embodiment
A lot of details have been set forth in the following description so that fully understand the present invention.But the present invention can implement much to be different from alternate manner described here, and those skilled in the art can do similar popularization under the situation of intension of the present invention, so the present invention is not subjected to the restriction of following public concrete enforcement.
Secondly, the present invention utilizes schematic diagram to be described in detail, and when the embodiment of the invention was described in detail in detail, for ease of explanation, described schematic diagram was an example, and it should not limit the scope of protection of the invention at this.
Below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
As depicted in figs. 1 and 2, in one embodiment of the invention, provide the three dimension system level packaging methods, comprise step:
S101 provides support plate;
S102 forms cementing layer on support plate;
S103 is affixed on the opposite face of the function face of chip and passive device on the cementing layer, forms first chip layer;
S104, the one side of support plate being posted first chip layer forms the first envelope bed of material, and the pad of the first chip layer chips and the pad of passive device are exposed;
S105 forms first micro through hole on the first envelope bed of material, and the metallization of first micro through hole is filled, and forms the wiring of first longitudinal metal in the first envelope bed of material;
S106 forms first wiring layer that is connected with the wiring of first longitudinal metal on the first envelope bed of material;
S107 piles up second chip layer on the first envelope bed of material;
S108 forms the second envelope bed of material that covers second chip layer on the first envelope bed of material, and exposes the pad of the second chip layer chips;
S109 forms second micro through hole and the metallization of second micro through hole is filled second longitudinal metal wiring that formation is connected with first wiring layer in the second envelope bed of material on the second envelope bed of material;
S110 forms second wiring layer that is connected with the wiring of second longitudinal metal on the second envelope bed of material;
S111 piles up the 3rd chip layer on the second envelope bed of material;
S112 forms the 3rd envelope bed of material that covers the 3rd chip layer on the second envelope bed of material, and exposes the pad of the 3rd chip layer chips;
S113 forms the 3rd micro through hole and the metallization of the 3rd micro through hole is filled the 3rd longitudinal metal wiring that formation is connected with second wiring layer in the 3rd envelope bed of material on the 3rd envelope bed of material;
S114 forms the 3rd wiring layer that is connected with the wiring of the 3rd longitudinal metal on the 3rd envelope bed of material;
S115 forms first protective layer that part exposes the 3rd wiring layer on the 3rd envelope bed of material;
S116 forms wiring metal layer again on first protective layer, make between itself and barish the 3rd wiring layer interconnected;
S117 forms second protective layer that part exposes the wiring metal layer again on first protective layer;
S118 forms the ball lower metal layer at the expose portion of wiring metal layer again;
S119 forms the metal soldered ball on the ball lower metal layer.
In the present embodiment, at first execution in step S101 provides support plate 101.In the present embodiment, support plate 101 adopts the silicon compound material, can be provided with metallic circuit in this silicon compound to realize the circuit arrangement function to final products.Certainly, those skilled in the art understand, and support plate 101 also can adopt glass material so that better hardness and evenness to be provided according to the design needs.
Execution in step S102 forms cementing layer 102 on support plate 101 again, forms structure as shown in Figure 3.In this step, support plate 101 is the bases that are used for carrying follow-up first chip layer 103, also is the basis of follow-up each layer encapsulating structure of carrying certainly.The cementing layer 102 that forms on support plate 101 is to be used for first chip layer 103 is fixed on support plate 101.
The method that forms cementing layer 102 on support plate 101 can for example be by methods such as spin coating or printings cementing layer 102 to be coated on the support plate 101.Such method is well known to those skilled in the art in field of semiconductor manufacture, does not repeat them here.
After forming cementing layer 102 on the support plate 101, can execution in step S103, the relative one side of the function face of chip in first chip layer and passive device is affixed on the cementing layer 102, form structure as shown in Figure 4.
In the specific embodiment of the present invention, the function face of first chip layer 103, be meant first chip layer 103 in bonding pads and the surface, pad place of passive device.
In a preferred embodiment of the present invention, first chip layer 103 and the follow-up chip layer of mentioning that fit on the cementing layer 102 can comprise one or more identical or different chips, can also comprise one or more identical or different passive devices.These chips and passive device become the part of a system in package product separately, finish the one or more independent function that realizes in the system level function separately.
In a preferred embodiment of the present invention, the chip in first chip layer 103 and the combination of passive device design according to systemic-function.Therefore, around one or a core assembly sheet, have identical or different other one or a core assembly sheet, passive devices such as perhaps identical or different electric capacity, resistance or inductance; Similarly, around a passive device, has the passive device of identical or different other, perhaps one or more identical or different chips.
Execution in step S104 then, the one side of support plate being posted first chip layer 103 forms the first envelope bed of material 105, makes the pad of the bonding pads of first chip layer 103 and passive device exposed, promptly forms structure as shown in Figure 5.In the subsequent technique process, the first envelope bed of material 105 both can have been protected first chip layer 103, can be used as the supporting body of subsequent technique again.
In one embodiment of the invention, the material that forms the first envelope bed of material 105 is an epoxy resin.The good seal performance of this material, plastotype is easy, is the preferred materials that forms the first envelope bed of material 105.The method that forms the first envelope bed of material 105 can for example be metaideophone, compression or method of printing.The concrete steps of these methods are well known to those skilled in the art, do not repeat them here.
Execution in step S105 forms first micro through hole 106 on the first envelope bed of material 105 again.First micro through hole 106 is to form the interconnected passage of interlayer wiring.And, in the first envelope bed of material 105, form first longitudinal metal wiring 131 with the 106 metallization fillings of first micro through hole.
Execution in step S106 forms first wiring layer 121 on the first envelope bed of material 105 then, and this first wiring layer 121 is connected with first longitudinal metal wiring 131, promptly forms structure as shown in Figure 6.First wiring layer 121 forms the conducting of first chip layer 103 on the first envelope bed of material 105.
Execution in step S107 piles up second chip layer 107 on the first envelope bed of material 105 again.Here said piling up is meant second chip layer 107 is placed pre-position on the first envelope bed of material 105.Execution in step S108 forms the second envelope bed of material 108 that covers second chip layer 107 on the first envelope bed of material 105 then, and exposes the pad of second chip layer, 107 chips.The material that forms the second envelope bed of material 108 can be identical with the material that forms the first envelope bed of material 105, promptly adopts epoxy resin to form the second envelope bed of material 108.
Execution in step S109 forms second micro through hole 109 109 metallization of second micro through hole is filled on the second envelope bed of material 108 again.Second micro through hole 109 penetrates the second envelope bed of material 108.Similar with first micro through hole 106, second micro through hole 109 also is to form the interconnected passage of interlayer wiring.In the second envelope bed of material 108, form second longitudinal metal wiring 132 that is connected with first wiring layer 121 again.
Execution in step S110 then forms on the second envelope bed of material 108 with second longitudinal metal wiring 132 and is connected second wiring layer 122, i.e. formation structure as shown in Figure 7.Second wiring layer 122 forms the conducting of second chipset 107 on the second envelope bed of material 105, the part circuit that also has second wiring layer 122 simultaneously is communicated with the part circuit of first wiring layer 121 by second longitudinal metals wiring in second micro through hole 109 132.That is to say, the second envelope bed of material about in the of 108 the two layers of wiring layer realized interconnecting by second micro through hole 109, also promptly formed interconnecting of second chipset 107 and first chip layer 103.
Execution in step S111 piles up the 3rd chip layer 110 on the second envelope bed of material 108 again.The 3rd chip layer 110 can be a multifunction chip.
Execution in step S112 forms the 3rd envelope bed of material 111 that covers the 3rd chip layer 110 on the second envelope bed of material 108 then, and exposes the pad of the 3rd chip layer 110 chips.The material that forms the 3rd envelope bed of material 111 can be identical with the material that forms the first envelope bed of material 105 and the second envelope bed of material 108, promptly adopts epoxy resin to form the 3rd envelope bed of material 111.
Execution in step S113 forms the 3rd micro through hole 112 on the 3rd envelope bed of material 111 again, and 112 metallization of the 3rd micro through hole are filled.The 3rd micro through hole 112 penetrates the 3rd envelope bed of material 111.Similar with second micro through hole 109 with first micro through hole 106, the 3rd micro through hole 112 also is to form the interconnected passage of interlayer wiring.In the 3rd envelope bed of material 111, form the 3rd longitudinal metal wiring 133 that is connected with second wiring layer 122 again.
Execution in step S114 forms on the 3rd envelope bed of material 111 and the 3rd longitudinal metal wiring 133 the 3rd wiring layers 123 that are connected then, promptly forms structure as shown in Figure 8.The 3rd wiring layer 123 forms the conducting of the 3rd chipset 110 on the 3rd envelope bed of material 111, the part circuit that also has the 3rd wiring layer 123 simultaneously is communicated with the part circuit of second wiring layer 122 by the 3rd longitudinal metals wiring in the 3rd micro through hole 112 133.That is to say, the 3rd envelope bed of material about in the of 111 the two layers of wiring layer realized interconnecting by the 3rd micro through hole 112, also promptly formed interconnecting of the 3rd chipset 110 and second chipset 107.
Then execution in step S115 comprises to step S119 again: form first protective layer 113 that part exposes the 3rd wiring layer 123 on the 3rd envelope bed of material 111; Formation is communicated with metal wiring layer 124 again with the 3rd wiring layer 123 on first protective layer 113, makes the 3rd wiring layer 123 see through the metal interconnected and cabling of wiring layer 124 realization functional system again; On first protective layer 113, form part exposing metal second protective layer 114 of wiring layer 124 again; Metal again the expose portion of wiring layer 124 form ball lower metal layer 125; Form metal soldered ball 115 on ball lower metal layer 125 surfaces, form structure as shown in Figure 9 at last.The material that forms first protective layer 113 and second protective layer 114 can be a polyimides.Step S115 is identical with the corresponding steps of the method for existing fan-out wafer encapsulation to step S119, does not repeat them here.
In the above-described embodiments, before forming ball lower metal layer 125 and metal soldered ball 115, also be formed with metal wiring layer 124 again.Those skilled in the art understand, and wiring layer 124 is not necessarily again for metal.Metal wiring layer 124 again is needs of package design, but not the needs of packaging technology.Do not need metal to connect up again at 124 o'clock in package design, can directly in the end directly form ball lower metal layer 125 surface formation metal soldered balls 115 on the pad of the electrode of one deck chip or passive device.
In addition, in above-mentioned embodiment, in the second layer and the 3rd layer, only write out the chip part, but the present invention is not limited to this, in each layer, can comprises a plurality of chips and a plurality of other passive devices.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (9)
1. the three dimension system level packaging methods is characterized in that, comprises step:
Support plate is provided;
On support plate, form cementing layer;
To comprise chip or comprise chip and the relative one side of the function face of passive device first chip layer is affixed on the described cementing layer;
The one side of support plate being posted first chip layer forms the first envelope bed of material, and exposes the pad of the first chip layer chips or the pad of chip and passive device;
In the described first envelope bed of material, form first micro through hole;
In first micro through hole, form the wiring of first longitudinal metal;
On the described first envelope bed of material, form first wiring layer of described first chip layer of conducting and the wiring of first longitudinal metal;
Form the multilayer chiop layer on the described first envelope bed of material, every layer of chip layer comprises the envelope bed of material of chip or chip and passive device, the described chipset of covering and passive device group and interconnects also conducting the longitudinal metal wiring and the wiring layer of layers of chips layer up and down.
2. three dimension system level packaging methods as claimed in claim 1 is characterized in that, arbitrary layer step specifically comprises in the formation multilayer chiop layer on the described first envelope bed of material:
On the last envelope bed of material, pile up this layer chip layer that comprises chip or chip and passive device;
On the last envelope bed of material, form to cover this layer chip layer and expose the pad of this layer chip layer chips or this layer envelope bed of material of the pad of chip and passive device;
On this layer envelope bed of material, form this layer micro through hole that is communicated with last wiring layer;
In this layer micro through hole, form this layer longitudinal metal wiring that connects last wiring layer;
On this layer envelope bed of material, form this layer wiring layer of the wiring of this layer of conducting longitudinal metal and this layer chip layer chips or chip and passive device.
3. three dimension system level packaging methods as claimed in claim 1 is characterized in that, also comprises step:
In the end form first protective layer that part exposes last one deck wiring layer on one deck envelope bed of material;
The metal that formation is communicated with described the 3rd wiring layer on described first protective layer is wiring layer again;
On described first protective layer, form part and expose described metal second protective layer of wiring layer again;
Described metal again the expose portion of wiring layer form the ball lower metal layer;
On described ball lower metal layer, form the metal soldered ball.
4. three dimension system level packaging methods as claimed in claim 1 is characterized in that, also comprises step:
In the end form first protective layer that part exposes last one deck wiring layer on one deck envelope bed of material;
Expose portion at described last one deck wiring layer forms the ball lower metal layer;
On described ball lower metal layer, form the metal soldered ball.
5. as claim 3 or 4 described three dimension system level packaging methods, it is characterized in that: the material that forms described protective layer is a polyimides.
6. three dimension system level packaging methods as claimed in claim 1 is characterized in that: described passive device group comprises electric capacity, resistance and/or inductance.
7. three dimension system level packaging methods as claimed in claim 1 is characterized in that: the material of the envelope bed of material is an epoxy resin.
8. three dimension system level packaging methods as claimed in claim 1 is characterized in that: the envelope bed of material forms by metaideophone, compression or method of printing.
9. three dimension system level packaging methods as claimed in claim 1 is characterized in that: the chip in the chip layer is one or more identical or different chips.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110070278.2A CN102157456B (en) | 2011-03-23 | 2011-03-23 | Three-dimensional system level packaging method |
| PCT/CN2012/072772 WO2012126379A1 (en) | 2011-03-23 | 2012-03-22 | Three-dimensional system-level packaging methods and structures |
| US13/984,967 US9099448B2 (en) | 2011-03-23 | 2012-03-22 | Three-dimensional system-level packaging methods and structures |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012126379A1 (en) * | 2011-03-23 | 2012-09-27 | Nantong Fujitsu Microelectronics Co., Ltd. | Three-dimensional system-level packaging methods and structures |
| CN103715178A (en) * | 2012-10-08 | 2014-04-09 | 财团法人工业技术研究院 | Dual-phase metal interconnection structure and manufacturing method thereof |
| CN105023916A (en) * | 2014-04-22 | 2015-11-04 | 精材科技股份有限公司 | Chip package and method for manufacturing the same |
| CN106469706A (en) * | 2015-08-20 | 2017-03-01 | 矽品精密工业股份有限公司 | Electronic package and manufacturing method thereof |
| CN106887393A (en) * | 2017-03-22 | 2017-06-23 | 中芯长电半导体（江阴）有限公司 | It is integrated with the method for packing of the encapsulating structure of power transmission chip |
| CN109841601A (en) * | 2017-11-28 | 2019-06-04 | 长鑫存储技术有限公司 | A kind of chip stack stereo encapsulation structure and manufacturing method |
| CN114664771A (en) * | 2022-02-14 | 2022-06-24 | 致瞻科技(上海)有限公司 | Novel semiconductor capacitor packaging structure and packaging method thereof |
| WO2024174316A1 (en) * | 2023-02-24 | 2024-08-29 | 上海烨映微电子科技股份有限公司 | Capacitor packaging structure and preparation method therefor |
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| CN102157393A (en) * | 2011-03-22 | 2011-08-17 | 南通富士通微电子股份有限公司 | Fan-out high-density packaging method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2012126379A1 (en) * | 2011-03-23 | 2012-09-27 | Nantong Fujitsu Microelectronics Co., Ltd. | Three-dimensional system-level packaging methods and structures |
| CN103715178A (en) * | 2012-10-08 | 2014-04-09 | 财团法人工业技术研究院 | Dual-phase metal interconnection structure and manufacturing method thereof |
| CN103715178B (en) * | 2012-10-08 | 2018-04-10 | 财团法人工业技术研究院 | Dual-phase metal interconnection structure and manufacturing method thereof |
| CN105023916A (en) * | 2014-04-22 | 2015-11-04 | 精材科技股份有限公司 | Chip package and method for manufacturing the same |
| CN106469706A (en) * | 2015-08-20 | 2017-03-01 | 矽品精密工业股份有限公司 | Electronic package and manufacturing method thereof |
| CN106887393A (en) * | 2017-03-22 | 2017-06-23 | 中芯长电半导体（江阴）有限公司 | It is integrated with the method for packing of the encapsulating structure of power transmission chip |
| WO2018171100A1 (en) * | 2017-03-22 | 2018-09-27 | 中芯长电半导体（江阴）有限公司 | Encapsulation method for encapsulation structure with integrated power transmission chip |
| CN106887393B (en) * | 2017-03-22 | 2018-10-19 | 中芯长电半导体（江阴）有限公司 | It is integrated with the packaging method of the encapsulating structure of power transmission chip |
| CN109841601A (en) * | 2017-11-28 | 2019-06-04 | 长鑫存储技术有限公司 | A kind of chip stack stereo encapsulation structure and manufacturing method |
| CN114664771A (en) * | 2022-02-14 | 2022-06-24 | 致瞻科技(上海)有限公司 | Novel semiconductor capacitor packaging structure and packaging method thereof |
| WO2024174316A1 (en) * | 2023-02-24 | 2024-08-29 | 上海烨映微电子科技股份有限公司 | Capacitor packaging structure and preparation method therefor |
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| CN102157456B (en) | 2014-05-28 |
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Address after: Jiangsu province Nantong City Chongchuan road 226006 No. 288 Patentee after: Tongfu Microelectronics Co., Ltd. Address before: 226006 Jiangsu Province, Nantong City Chongchuan District Chongchuan Road No. 288 Patentee before: Fujitsu Microelectronics Co., Ltd., Nantong |