CN102169879B - Highly integrated wafer fan-out packaging structure - Google Patents
Highly integrated wafer fan-out packaging structure Download PDFInfo
- Publication number
- CN102169879B CN102169879B CN2011100322641A CN201110032264A CN102169879B CN 102169879 B CN102169879 B CN 102169879B CN 2011100322641 A CN2011100322641 A CN 2011100322641A CN 201110032264 A CN201110032264 A CN 201110032264A CN 102169879 B CN102169879 B CN 102169879B
- Authority
- CN
- China
- Prior art keywords
- chip
- passive device
- high integration
- encapsulating structure
- packed unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
- H01L2224/24195—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Abstract
The invention relates to a highly integrated wafer fan-out packaging structure, comprising a to-be-packaged unit, chips and a passive device, wherein the to-be-packaged unit has a function surface; a material-sealing layer is formed on a surface opposite to the function surface of the to-be-packaged unit; the material-sealing layer carries out packaging curing over the to-be-packaged unit; and a groove is arranged between the to-be-packaged units corresponding to the material-sealing layer surface. Compared with the prior art, the highly integrated wafer fan-out packaging structure of the invention firstly integrates chips and passive devices and then carries out packaging, and is a final packaged product having overall system function, instead of single chip function. Furthermore, in thestructure, the entire packaging of the material-sealing layer is decomposed into a plurality of to-be-packaged units, and the internal stress of the material-sealing layer is reduced via the groove between the to-be-packaged units, thereby avoiding warpage of material-sealing layer in the subsequent process of wafer packaging and improving the quality of finished wafer packaging product.
Description
Technical field
The present invention relates to semiconductor technology, relate in particular to a kind of high integration wafer fan-out encapsulating structure.
Background technology
Wafer-level packaging (Wafer Level Packaging, WLP) technology is that the full wafer wafer is carried out cutting the technology that obtains single finished chip again after the packaging and testing, chip size and nude film after the encapsulation are in full accord.The crystal wafer chip dimension encapsulation technology has thoroughly been overturned conventional package such as ceramic leadless chip carrier (Ceramic Leadless Chip Carrier) and organic leadless chip carrier (Organic LeadlessChip Carrier) isotype, has complied with that market is light day by day, little, short to microelectronic product, thinning and low priceization requirement.It is highly microminiaturized that chip size after crystal wafer chip dimension encapsulation technology encapsulation has reached, chip cost along with chip size reduce significantly reduce with the increase of wafer size.The crystal wafer chip dimension encapsulation technology be IC can be designed, technology that wafer manufacturing, packaging and testing, substrate manufacturing integrate, be focus and the developing tendency in future of current encapsulation field.
The encapsulation of fan-out wafer is a kind of of wafer-level packaging.For example, the Chinese invention patent application discloses a kind of wafer scale fan-out chip packaging method No. 200910031885.0, comprise following processing step: encapsulate stripping film and thin film dielectrics layer I successively in the carrier disk surfaces, form litho pattern opening I at thin film dielectrics layer I; Realize the metal electrode be connected with edge of substrate and wiring metal cabling again on figure opening I and surface thereof; At the surface of metal electrode that is connected with edge of substrate, the surface encapsulation thin film dielectrics layer II of wiring metal cabling surface and thin film dielectrics layer I again, and form litho pattern opening II at thin film dielectrics layer II; Realize the metal electrode be connected with die terminals at litho pattern opening II; With flip-chip to metal electrode that die terminals is connected after carry out the injection moulding envelope bed of material and solidify, formation has the packaging body of the plastic packaging bed of material; The carrier disk is separated with the packaging body that has the plastic packaging bed of material with stripping film, form the plastic packaging disk; Plant ball and reflux, form solder bumps; The monolithic cutting forms final fan-out chip structure.
The final products of packaged manufacturing only have single chip functions according to the method described above.Realize complete systemic-function as need, need outside final products, add the peripheral circuit that includes various electric capacity, inductance or resistance etc.
Summary of the invention
The technical problem that the present invention solves is: wafer fan-out encapsulating structure how to realize high integration.
For solving the problems of the technologies described above, the invention provides high integration wafer fan-out encapsulating structure, comprising:
Packed unit comprises chip and passive device, and described packed unit has the function face;
The another side relative with the function face of packed unit is formed with the envelope bed of material, and the described envelope bed of material carries out package curing to packed unit, and described envelope bed of material surface is corresponding to being provided with groove between the packed unit.
Alternatively, described function face refers to the surface, pad place of metal electrode and the passive device of packed unit chips.
Alternatively, the described envelope bed of material also be filled between described chip and the chip, between chip and the passive device and/or the space between passive device and the passive device.
Alternatively, described passive device comprises electric capacity, resistance and inductance.
Alternatively, the material of the described envelope bed of material is epoxy resin.
Alternatively, the described envelope bed of material is formed on described chip and the passive device by metaideophone, compression or method of printing.
Alternatively, described groove has many, and each bar groove seals around described packed unit.
Alternatively, the shape that surrounds of each bar groove comprises square, rectangle or circle.
Alternatively, keep same distance between each bar groove.
Alternatively, described groove becomes matrix to arrange.
Alternatively, the cross section of described groove comprises U-shaped, V-type or matrix.
Alternatively, described chip comprises a plurality of different chips.
Alternatively, the function face of described encapsulation unit is formed with metal interconnect structure.
Alternatively; described metal interconnect structure comprises: be positioned at metal wiring layer and ball lower metal layer again on the function face of chip and passive device successively; and being positioned at the metal soldered ball on ball lower metal layer surface, described ball lower metal layer and metal also are formed with diaphragm again between wiring layer.
Compared with prior art; the high integration wafer fan-out encapsulating structure that the present invention asks for protection; encapsulation in the lump again after chip and passive device integrated; for comprising the total system function but not the encapsulating structure of single chip functions; compare the existing systems class encapsulation structure; the wafer-level package structure of high integration has reduced disturbing factor such as resistance, inductance in the system especially, also more can comply with the compact trend requirement of semiconductor packages.In addition, a plurality of little packed unit are resolved in the full wafer encapsulation of the envelope bed of material, the groove that is arranged at simultaneously between the packed unit can reduce the internal stress of sealing the bed of material, can avoid sealing the bed of material and buckling deformation occur in the subsequent process of wafer encapsulation, has improved the quality of wafer encapsulation finished product.
Description of drawings
Fig. 1 is high integration wafer fan-out encapsulating structure generalized section in the one embodiment of the invention;
Fig. 2 is high integration wafer fan-out encapsulating structure schematic top plan view in the one embodiment of the invention;
Fig. 3 is the formation method flow diagram of high integration wafer fan-out encapsulating structure in the one embodiment of the invention;
Fig. 4 is the formation method flow diagram of high integration wafer fan-out encapsulating structure in the another embodiment of the present invention;
Fig. 5 to Figure 13 is encapsulating structure schematic diagram in the flow process shown in Figure 4.
Embodiment
A lot of details have been set forth in the following description so that fully understand the present invention.But the present invention can implement much to be different from alternate manner described here, and those skilled in the art can do similar popularization under the situation of intension of the present invention, so the present invention is not subjected to the restriction of following public concrete enforcement.
Secondly, the present invention utilizes schematic diagram to be described in detail, and when the embodiment of the invention was described in detail in detail, for ease of explanation, described schematic diagram was example, and it should not limit the scope of protection of the invention at this.
The encapsulating structure of prior art only has single chip functions.Realize complete systemic-function as need, need outside final products, add the peripheral circuit that includes various electric capacity, inductance or resistance etc.
For addressing the above problem, the invention provides a kind of high integration wafer fan-out encapsulating structure, comprising: packed unit, comprise chip and passive device, described packed unit has the function face;
The another side relative with the function face of packed unit is formed with the envelope bed of material, and the described envelope bed of material carries out package curing to packed unit, and described envelope bed of material surface is corresponding to being provided with groove between the packed unit.
Below in conjunction with accompanying drawing high integration wafer fan-out encapsulating structure of the present invention is described in detail.
As shown in Figure 1, high integration wafer fan-out encapsulating structure of the present invention comprises: the envelope bed of material 05, by the packed unit of some numbers of the described envelope bed of material 05 encapsulation, described packed unit comprises chip 03 and passive device 04.Wherein, chip 03 and passive device 04 function face are electrically connected with metal interconnect structure, and described function face refers to the surface, pad place of metal electrode and the passive device 04 of packed unit chips 03.
Described metal interconnect structure comprises metal wiring layer 06 and the ball lower metal layer 08 again on the function face that is positioned at chip 03 and passive device 04 successively; and being positioned at the metal soldered ball 09 on ball lower metal layer surface, described ball lower metal layer 08 and metal 06 of wiring layer more also are formed with diaphragm 07.
In a preferred embodiment of the present invention, described chip 03 can be a plurality of different chips, and these chips become the part of a system in package product separately, finishes the one or more independent function that realizes in the system level function separately.
In a preferred embodiment of the present invention, the combination of chip 03 and passive device 04 is that the systemic-function according to packed unit designs.Therefore, around a chip 03, identical or different other chip 03 may be arranged, perhaps identical or different passive devices 04 such as electric capacity, resistance or inductance; Similarly, around a passive device 04, the passive device 04 of identical or different other may be arranged, perhaps one or more identical or different chips 03.
Continuation is with reference to figure 1, and the described envelope bed of material 05 is for carrying out the encapsulation of the plastic packaging bed of material and solidifying to form to the packed unit that comprises chip 03 and passive device 04.In the subsequent technique process, the envelope bed of material 05 can be protected function face other surfaces in addition of chip 03 and passive device 04, can be used as the supporting body of subsequent technique again.
In one embodiment of the invention, the material of the described envelope bed of material 05 is epoxy resin.The good seal performance of this material, plastotype is easy, is the preferred materials that forms the envelope bed of material 05.Wherein, forming the method for sealing the bed of material 05 can for example be metaideophone, compression or method of printing.
Continuation as previously mentioned, around a chip 03, may have other chip 03 with reference to figure 1, and perhaps passive device 04; Around a passive device 04, the passive device 04 of identical or different other also may be arranged, perhaps one or more identical or different chips 03.Therefore, around chip 03 or passive device 04, have the space.For chip 03 and passive device 04 formed better protection, the envelope bed of material 05 also is filled between chip 03 and the chip 03, between chip 03 and the passive device 04 and/or space between passive device 04 and the passive device 04.
Because the thickness of chip 03 and passive device 04 also is not quite similar, possible chip 03 is thicker, and also possible passive device 04 is thicker.Therefore, the thickness of the envelope bed of material 05 should be greater than one thickness the thickest in each chip 03 and the passive device 04, in order to provide best protection to chip 03 and passive device 04.
Continuation simultaneously with reference to figure 2, is provided with groove 50 with reference to figure 1 between each packed unit of the envelope bed of material 05.These grooves 50 are by the design of the perforate of stencil web plate and the degree of depth, form after printing.After forming groove 50, the stress in can the balance envelope bed of material 05, thus avoid in the subsequent process of wafer encapsulation, buckling deformation occurring.
The cross section of groove 50 can carry out different designs according to the stress in the envelope bed of material 05 and the profile of packed device.In a preferred embodiment, the cross section of groove 50 comprises U-shaped, V-type or matrix.
The degree of depth of groove 50 is relevant with the design of stencil web plate.Groove 50 thickness that arrange according to stencil web plate designing institute can the active balance envelope bed of material 05 inside stress.
With reference to figure 1 and Fig. 2, in a preferred embodiment of the present invention, groove 50 has many simultaneously, and each bar groove 50 is around being sealed into ring by a packed unit.This circulus can effectively reduce the stress of the envelope bed of material 05 around chip 03 and passive device 04, thus the stress distribution of the further balance envelope bed of material 05 inside.The annular that each bar groove 50 surrounds comprises square, rectangle or circle.Can comprise multiple chips 03 in the packed unit that each annular groove 50 is drawn a circle to approve, also passive device 04 capable of being combined.Be that matrix is arranged between the packed unit, and groove 50 is arranged between packed unit, similar crisscross paths between fields are staggered.
The groove 50 of annular has multiple arrangement mode, can adapt to the different arrangements of chip 03 and passive device 04.In another preferred embodiment of the present invention, 50 one-tenth matrixes of the groove of a plurality of annulars are arranged.
High integration wafer fan-out encapsulating structure of the present invention, encapsulation in the lump again after chip 03 and passive device 04 integrated, for comprising the total system function but not the encapsulating structure of single chip functions, compare the existing systems class encapsulation structure, the wafer-level package structure of high integration has reduced disturbing factor such as resistance, inductance in the system especially, also more can comply with the compact trend requirement of semiconductor packages.In addition, a plurality of little packed unit are resolved in the full wafer encapsulation of the envelope bed of material, be arranged at groove 50 between the packed unit and can reduce the internal stress of the envelope bed of material, and then avoid sealing the bed of material and in the subsequent process of wafer encapsulation, buckling deformation occurs, improved the quality of wafer encapsulation finished product.
Be described in detail below in conjunction with the formation method of accompanying drawing to high integration wafer fan-out encapsulating structure of the present invention.
As shown in Figure 3, in one embodiment of the invention, provide the formation method of high integration wafer fan-out encapsulating structure, comprise step:
S101 forms cementing layer at support plate;
S102, the function face of the packed unit that will be made up of chip and passive device is affixed on the cementing layer;
S103, the one side of support plate being posted chip and passive device forms the envelope bed of material, carries out package curing, and described envelope bed of material surface is corresponding to being provided with groove between the packed unit;
S104 removes support plate and cementing layer.
As shown in Figure 4, in another embodiment of the present invention, provide the formation method of high integration wafer fan-out encapsulating structure, comprise step:
S201 forms cementing layer at support plate;
S202, the function face of the packed unit that will be made up of chip and passive device is affixed on the cementing layer;
S203, the one side of support plate being posted chip and passive device forms the envelope bed of material, carries out package curing, and described envelope bed of material surface is corresponding to being provided with groove between the packed unit;
S204 removes cementing layer;
S205 separates the function face of support plate with chip and passive device;
S206, the function face of cleaning chip and passive device;
S207 carries out metal at the exposed function face of chip and passive device and connects up;
S208 forms diaphragm on connect up again place surface of metal, and forms the opening that exposes metal covering at diaphragm;
S209, the metal covering in the diaphragm opening forms the ball lower metal layer;
S210 forms the metal soldered ball on ball lower metal layer surface.
In the present embodiment, at first execution in step S201 forms cementing layer 102 at support plate 101, forms structure as shown in Figure 5.
In this step, support plate 101 is the bases of carrying follow-up chip 103 and passive device 104.
In the present embodiment, support plate 101 adopts glass material, and better hardness and evenness can be provided, and reduces the inefficacy ratio of packaging.In addition, owing to support plate 101 can be stripped from subsequent step, and the support plate 101 of glass material is easily peeled off, resistance to corrosion is strong, can therefore can not reuse because of the change that physics and chemical property take place with contacting of cementing layer 102.Certainly, those skilled in the art understand, and support plate 101 for example adopts silicon compound also can realize purpose of the present invention.
The cementing layer 102 that forms at support plate 101 is for being fixed on support plate 101 by the packed unit that chip 103 and passive device 104 are formed.Cementing layer 102 available materials have multiple, and in preferred embodiment of the present invention, cementing layer 102 adopts UV glue.UV glue be a kind of can be to the aitiogenic glueing material of the UV-irradiation of special wavelength.UV glue according to UV-irradiation after the variation of viscosity can be divided into two kinds, a kind of is that UV solidifies glue, be to produce living radical or cation light trigger in the material or sensitising agent absorb ultraviolet light under ultraviolet irradiation after, trigger monomer polymerization, crosslinked and connect Zhi Huaxue reaction, it is solid-state that ultraviolet cured adhesive was converted into by liquid state in the several seconds, thereby the body surface that is in contact with it is bonding; Another kind be UV glue be not through when irradiation ultraviolet ray viscosity very high, caused viscosity to decline to a great extent or disappear and interrupt through the crosslinking chemical bond in the material after the UV-irradiation.The UV glue that the cementing layer 102 here adopts namely is the latter.
The method that forms cementing layer 102 at support plate 101 can for example be by methods such as spin coating or printings cementing layer 102 to be coated on the support plate 101.Such method is well known to those skilled in the art in field of semiconductor manufacture, does not repeat them here.
After support plate 101 forms cementing layers 102, can execution in step S202, the function face of the packed unit that will be made up of chip 103 and passive device 104 is affixed on the cementing layer 102 formation structure as shown in Figure 6.
In the specific embodiment of the present invention, the function face of the packed unit of being made up of chip 103 and passive device 104 refers to the surface, pad place of metal electrode and the passive device 104 of packed unit chips 103.
In a preferred embodiment of the present invention, the a plurality of chips 103 that fit on the cementing layer 102 can be a plurality of different chips, these chips become the part of a system in package product separately, finish the one or more independent function that realizes in the system level function separately.
In a preferred embodiment of the present invention, the combination of chip 103 and passive device 104 is that the systemic-function according to packed unit designs.Therefore, around a chip 103, identical or different other chip 103 may be arranged, perhaps identical or different passive devices 104 such as electric capacity, resistance or inductance; Similarly, around a passive device 104, the passive device 104 of identical or different other may be arranged, perhaps one or more identical or different chips 103.
Execution in step S203 carries out the encapsulation of the plastic packaging bed of material and curing with the support plate face that posts chip and passive device then, forms to have the packaging body that seals the bed of material 105, namely forms structure as shown in Figure 7.In the subsequent technique process, packaging body can be protected function face other surfaces in addition of chip 103 and passive device 104, can be used as the supporting body of subsequent technique again.
In one embodiment of the invention, forming the material that seals the bed of material 105 is epoxy resin.The good seal performance of this material, plastotype is easy, is the preferred materials that forms the envelope bed of material 105.The method that forms the envelope bed of material 105 can for example be metaideophone, compression or method of printing.The concrete steps of these methods are well known to those skilled in the art, do not repeat them here.
As previously mentioned, around a chip 103, other chip 103 may be arranged, perhaps passive device 104; Around a passive device 104, the passive device 104 of identical or different other also may be arranged, perhaps one or more identical or different chips 103.Therefore, around chip 103 or passive device 104, have the space.For chip 103 and passive device 104 formed better protection, the envelope bed of material 105 also is filled between chip 103 and the chip 103, between chip 103 and the passive device 104 and/or space between passive device 104 and the passive device 104.
Because the thickness of chip 103 and passive device 104 also is not quite similar, possible chip 103 is thicker, and also possible passive device 104 is thicker.Therefore, the thickness of the envelope bed of material 105 should be greater than one thickness the thickest in each chip 103 and the passive device 104, in order to provide best protection to chip 103 and passive device 104.
Because the thermal contraction ratio of 101 two kinds of materials of the envelope bed of material 105 and support plate is different, it is inhomogeneous to cause sealing the bed of material 105 internal stresss, and this can cause sealing the bed of material 105 and buckling deformation occur in the subsequent process of wafer encapsulation, and then has influence on the quality of encapsulation finished product.
Therefore, as shown in Figure 8, in the specific embodiment of the present invention, between each packed unit of the envelope bed of material 105, be provided with groove 150.These grooves 150 are by the design of the perforate of stencil web plate and the degree of depth, form after printing.After forming groove 150, the stress in can the balance envelope bed of material 105, thus avoid in the subsequent process of wafer encapsulation, buckling deformation occurring.
The cross section of groove 150 can carry out different designs according to the stress in the envelope bed of material 105 and the profile of packed device.In a preferred embodiment, the cross section of groove 150 comprises U-shaped, V-type or matrix.
The degree of depth of groove 150 is relevant with the design of stencil web plate.Groove 150 thickness that arrange according to stencil web plate designing institute can the active balance envelope bed of material 105 inside stress.
In a preferred embodiment of the present invention, groove 150 has many, and each bar groove 150 is around being sealed into ring by a packed unit.This circulus can effectively reduce the stress of the envelope bed of material 105 around chip 103 and passive device 104, thus the stress distribution of the further balance envelope bed of material 105 inside.The annular that each bar groove 150 surrounds comprises square, rectangle or circle.Can comprise multiple chips 103 in the packed unit that each annular groove 150 is drawn a circle to approve, also passive device 104 capable of being combined.Be that matrix is arranged between the packed unit, and groove 150 is arranged between packed unit, similar crisscross paths between fields are staggered.
The groove 150 of annular has multiple arrangement mode, can adapt to the different arrangements of chip 103 and passive device 104.In another preferred embodiment of the present invention, 150 one-tenth matrixes of the groove of a plurality of annulars are arranged.
Execution in step S204 removes cementing layer 102 again.Because cementing layer 102 is organic materials, can be dissolved in specific organic solvent.Therefore, the method that can adopt organic solvent to clean makes cementing layer 102 be dissolved in the organic solvent.
Execution in step S205 separates the function face of support plate 101 with chip 103 and passive device 104 then.That is to say, after execution in step S204, cementing layer 102 solvent has fallen, and perhaps is under the strippable molten condition, can easily the function face of support plate 101 from chip 103 and passive device 104 be stripped down, thereby expose the function face of chip 103 and passive device 104.
Execution in step S206 again, clean the function face of chip 103 and passive device 104, with cementing layer residual on the function face 102, form structure as shown in Figure 9, chip 103 and passive device 104 no longer are fixed together through support plate but have been fixed together by packaging body at this moment, and the metal electrode of chip and the pad of passive device also expose out simultaneously.
Extremely shown in Figure 13 as Figure 10, follow again execution in step S207 to step S210, comprise: carry out metal at the exposed function face of chip and passive device and connect up 106 again, the metal wire that makes the pad of the metal electrode of chip and passive device see through again cloth is realized the interconnected and cabling of functional system; Form diaphragm 107 on connect up again place surface of metal, and connect up 106 at the opening that diaphragm forms design again to expose metal; Metal in the diaphragm opening connects up and 106 forms ball lower metal layers 108; Form metal soldered ball 109 on ball lower metal layer 108 surfaces.Step S207 is identical with the method for existing fan-out wafer encapsulation to step S210, does not repeat them here.
Through above-mentioned steps, finish system in package substantially.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (12)
1. high integration wafer fan-out encapsulating structure is characterized in that, comprising:
Packed unit comprises chip and passive device, and described packed unit has the function face;
The another side relative with the function face of packed unit is formed with the envelope bed of material, and the described envelope bed of material carries out package curing to packed unit;
The function face of described packed unit is formed with metal interconnect structure, and the described envelope bed of material is as the supporting body of packed unit and metal interconnect structure;
Described envelope bed of material surface is corresponding to being provided with groove between the packed unit, and described groove seals into ring around packed unit, and described groove does not expose the metal interconnect structure between the adjacent packed unit.
2. high integration wafer fan-out encapsulating structure as claimed in claim 1, it is characterized in that: described function face refers to the surface, pad place of metal electrode and the passive device of packed unit chips.
3. high integration wafer fan-out encapsulating structure as claimed in claim 1 is characterized in that: the described envelope bed of material also is filled between described chip and the chip, between chip and the passive device and/or the space between passive device and the passive device.
4. high integration wafer fan-out encapsulating structure as claimed in claim 1, it is characterized in that: described passive device comprises electric capacity, resistance and inductance.
5. high integration wafer fan-out encapsulating structure as claimed in claim 1, it is characterized in that: the material of the described envelope bed of material is epoxy resin.
6. high integration wafer fan-out encapsulating structure as claimed in claim 1, it is characterized in that: the described envelope bed of material is formed on described chip and the passive device by metaideophone, compression or method of printing.
7. high integration wafer fan-out encapsulating structure as claimed in claim 1, it is characterized in that: described groove has many, and the shape that each bar groove surrounds comprises square, rectangle or circle.
8. high integration wafer fan-out encapsulating structure as claimed in claim 7 is characterized in that: keep same distance between each bar groove.
9. high integration wafer fan-out encapsulating structure as claimed in claim 8 is characterized in that: described groove becomes matrix to arrange.
10. high integration wafer fan-out encapsulating structure as claimed in claim 9 is characterized in that: the cross section of described groove comprises U-shaped, V-type or matrix.
11. high integration wafer fan-out encapsulating structure as claimed in claim 1, it is characterized in that: described chip comprises a plurality of different chips.
12. high integration wafer fan-out encapsulating structure as claimed in claim 1; it is characterized in that: described metal interconnect structure comprises: be positioned at metal wiring layer and ball lower metal layer again on the function face of chip and passive device successively; and being positioned at the metal soldered ball on ball lower metal layer surface, described ball lower metal layer and metal also are formed with diaphragm again between wiring layer.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011100322641A CN102169879B (en) | 2011-01-30 | 2011-01-30 | Highly integrated wafer fan-out packaging structure |
| PCT/CN2012/070629 WO2012100721A1 (en) | 2011-01-30 | 2012-01-20 | Packaging structure |
| US13/981,123 US9497862B2 (en) | 2011-01-30 | 2012-01-20 | Packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011100322641A CN102169879B (en) | 2011-01-30 | 2011-01-30 | Highly integrated wafer fan-out packaging structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102169879A CN102169879A (en) | 2011-08-31 |
| CN102169879B true CN102169879B (en) | 2013-10-02 |
Family
ID=44490969
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011100322641A Active CN102169879B (en) | 2011-01-30 | 2011-01-30 | Highly integrated wafer fan-out packaging structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102169879B (en) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9497862B2 (en) | 2011-01-30 | 2016-11-15 | Nantong Fujitsu Microelectronics Co., Ltd. | Packaging structure |
| CN103681560B (en) * | 2012-09-25 | 2016-12-21 | 西安永电电气有限责任公司 | A kind of grooving type IGBT module base plate and IGBT module |
| US9824989B2 (en) | 2014-01-17 | 2017-11-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fan-out package and methods of forming thereof |
| CN104538318B (en) * | 2014-12-24 | 2017-12-19 | 通富微电子股份有限公司 | A kind of Fanout type wafer level chip method for packing |
| CN105140211A (en) * | 2015-07-14 | 2015-12-09 | 华进半导体封装先导技术研发中心有限公司 | FAN-OUT packaging structure and packaging method thereof |
| CN105374731A (en) * | 2015-11-05 | 2016-03-02 | 南通富士通微电子股份有限公司 | Packaging method |
| CN106252303B (en) * | 2016-06-30 | 2019-02-05 | 苏州能讯高能半导体有限公司 | A kind of semiconductor devices and preparation method thereof |
| CN106531647B (en) * | 2016-12-29 | 2019-08-09 | 华进半导体封装先导技术研发中心有限公司 | A kind of encapsulating structure being fanned out to cake core and its packaging method |
| CN110120355A (en) * | 2019-05-27 | 2019-08-13 | 广东工业大学 | A method of reducing fan-out package warpage |
| CN112346298A (en) * | 2019-08-06 | 2021-02-09 | 上海量子绘景电子股份有限公司 | Large-size imprinting mold and preparation method thereof |
| CN117116776B (en) * | 2023-10-24 | 2024-01-23 | 甬矽电子(宁波)股份有限公司 | Fan-out type packaging structure, manufacturing method thereof and electronic equipment |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1707792A (en) * | 2004-06-08 | 2005-12-14 | 三洋电机株式会社 | Semiconductor module with high process accuracy, manufacturing method thereof, and semiconductor device therewith |
| JP2005347514A (en) * | 2004-06-03 | 2005-12-15 | Towa Corp | Method of molding multichip |
| CN101174601A (en) * | 2006-11-03 | 2008-05-07 | 台湾积体电路制造股份有限公司 | Semiconductor structure and method of manufacturing same |
| CN101425469A (en) * | 2007-10-30 | 2009-05-06 | 育霈科技股份有限公司 | Semi-conductor packaging method using large size panel |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0642343Y2 (en) * | 1987-01-09 | 1994-11-02 | ローム株式会社 | Semiconductor device |
| JPH01220463A (en) * | 1988-02-29 | 1989-09-04 | Seiko Epson Corp | Semiconductor device |
-
2011
- 2011-01-30 CN CN2011100322641A patent/CN102169879B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005347514A (en) * | 2004-06-03 | 2005-12-15 | Towa Corp | Method of molding multichip |
| CN1707792A (en) * | 2004-06-08 | 2005-12-14 | 三洋电机株式会社 | Semiconductor module with high process accuracy, manufacturing method thereof, and semiconductor device therewith |
| CN101174601A (en) * | 2006-11-03 | 2008-05-07 | 台湾积体电路制造股份有限公司 | Semiconductor structure and method of manufacturing same |
| CN101425469A (en) * | 2007-10-30 | 2009-05-06 | 育霈科技股份有限公司 | Semi-conductor packaging method using large size panel |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102169879A (en) | 2011-08-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102157400B (en) | Method for encapsulating high-integration wafer fan-out | |
| CN102169879B (en) | Highly integrated wafer fan-out packaging structure | |
| CN102163603B (en) | Packaging structure for system level fan-out wafer | |
| CN102157401B (en) | High-density SIP (system in package) method of chip | |
| CN104716103B (en) | Underfill pattern with gap | |
| US8729714B1 (en) | Flip-chip wafer level package and methods thereof | |
| CN102176418B (en) | Fan-out system-in-package (SIP) method | |
| CN102157393B (en) | Fan-out high-density packaging method | |
| KR101366455B1 (en) | Semiconductor devices, packaging methods and structures | |
| US20080164545A1 (en) | Mems microphone package and method thereof | |
| TW201628104A (en) | Fingerprint sensor package and method for fabricating the same | |
| TWI414027B (en) | Chip-sized package and fabrication method thereof | |
| CN102157456B (en) | Three-dimensional system level packaging method | |
| CN105374731A (en) | Packaging method | |
| TW201222740A (en) | Integrated circuit packaging system with dual side connection and method of manufacture thereof | |
| TWI421956B (en) | Chip-sized package and fabrication method thereof | |
| CN102176452B (en) | High-density chip system-in-package structure | |
| CN102169840A (en) | Encapsulation method of system level fan-out wafer | |
| WO2012100720A1 (en) | Packaging method | |
| WO2012100721A1 (en) | Packaging structure | |
| CN102122646A (en) | Wafer packaging device and chip packaging unit | |
| CN201994277U (en) | Wafer packaging structure | |
| CN102157501B (en) | Three-dimensional system level packaging structure | |
| CN102122624B (en) | Wafer packaging method | |
| US9324686B2 (en) | Semiconductor chips having improved solidity, semiconductor packages including the same and methods of fabricating the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C56 | Change in the name or address of the patentee | ||
| CP03 | Change of name, title or address |
Address after: Jiangsu province Nantong City Chongchuan road 226006 No. 288 Patentee after: Tongfu Microelectronics Co., Ltd. Address before: 226006 Jiangsu Province, Nantong City Chongchuan District Chongchuan Road No. 288 Patentee before: Fujitsu Microelectronics Co., Ltd., Nantong |
|
| EE01 | Entry into force of recordation of patent licensing contract | ||
| EE01 | Entry into force of recordation of patent licensing contract |
Application publication date: 20110831 Assignee: Suzhou Tong Fu Chaowei Semiconductor Co. Ltd. Assignor: Tongfu Microelectronics Co., Ltd. Contract record no.: 2017320010009 Denomination of invention: Highly integrated wafer fan-out packaging structure Granted publication date: 20131002 License type: Common License Record date: 20170308 |