CN117116776B - Fan-out type packaging structure, manufacturing method thereof and electronic equipment - Google Patents
Fan-out type packaging structure, manufacturing method thereof and electronic equipment Download PDFInfo
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- CN117116776B CN117116776B CN202311376963.7A CN202311376963A CN117116776B CN 117116776 B CN117116776 B CN 117116776B CN 202311376963 A CN202311376963 A CN 202311376963A CN 117116776 B CN117116776 B CN 117116776B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 48
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 39
- 238000010146 3D printing Methods 0.000 claims abstract description 18
- 239000010410 layer Substances 0.000 claims description 74
- 238000000034 method Methods 0.000 claims description 29
- 230000008569 process Effects 0.000 claims description 19
- 239000003292 glue Substances 0.000 claims description 18
- 239000002184 metal Substances 0.000 claims description 18
- 229910052751 metal Inorganic materials 0.000 claims description 18
- 230000017525 heat dissipation Effects 0.000 claims description 9
- 230000007704 transition Effects 0.000 claims description 8
- 238000001465 metallisation Methods 0.000 claims description 7
- 238000000227 grinding Methods 0.000 claims description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- 239000012790 adhesive layer Substances 0.000 claims description 3
- 239000010936 titanium Substances 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 238000004528 spin coating Methods 0.000 claims description 2
- 238000009826 distribution Methods 0.000 abstract description 4
- 239000004065 semiconductor Substances 0.000 abstract description 4
- 238000005516 engineering process Methods 0.000 abstract description 3
- 239000004033 plastic Substances 0.000 description 12
- 239000000463 material Substances 0.000 description 9
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 238000012858 packaging process Methods 0.000 description 6
- 238000005240 physical vapour deposition Methods 0.000 description 6
- 239000004642 Polyimide Substances 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 4
- 230000001070 adhesive effect Effects 0.000 description 4
- 238000000465 moulding Methods 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 229910000679 solder Inorganic materials 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 3
- 238000003825 pressing Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000006073 displacement reaction Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910007637 SnAg Inorganic materials 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- 229910001080 W alloy Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 description 1
- 238000009736 wetting Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/52—Mounting semiconductor bodies in containers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
Abstract
The application discloses a fan-out type packaging structure, a manufacturing method thereof and electronic equipment, and relates to the technical field of semiconductors. The manufacturing method comprises the steps of 3D printing a cavity structure on a substrate, wherein a first groove and a second groove are respectively formed in one side of the cavity structure facing the substrate and one side of the cavity structure facing away from the substrate; mounting a chip in the second groove, wherein one side of the chip with pins faces to the opening of the second groove; paving a rewiring layer on the cavity structure; ball placement on the rewiring layer; the cavity structure is separated from the substrate. The cavity structure of double-sided grooves can be manufactured by adopting a 3D printing technology, and the second grooves are used for accommodating and positioning chips, so that the chips are not easy to deviate. The cavity structure of the double-sided groove has higher symmetry in the thickness direction, so that the problem of warping caused by uneven stress distribution is not easy to occur after the double-sided groove is formed. The manufacturing method provided by the application can improve the yield of the product.
Description
Technical Field
The application relates to the technical field of semiconductors, in particular to a fan-out type packaging structure, a manufacturing method thereof and electronic equipment.
Background
With the rapid development of the semiconductor industry, the wafer-level fan-out type packaging structure is widely applied to the semiconductor industry. In the manufacturing process of the fan-out type packaging structure, the plastic packaging link is easy to warp due to the material characteristics, so that the follow-up processing process is not easy. In addition, the chip is easily influenced by pressure in the plastic packaging process to cause deflection, so that the yield is reduced.
Disclosure of Invention
The purpose of the application includes providing a fan-out type packaging structure, a manufacturing method thereof and electronic equipment, wherein the problem of warping of the packaging structure can be relieved, and the product yield is improved.
Embodiments of the present application may be implemented as follows:
in a first aspect, the present application provides a method for manufacturing a fan-out package structure, including:
3D printing on the substrate to form a cavity structure, wherein a first groove and a second groove are respectively formed on one side of the cavity structure facing the substrate and one side of the cavity structure facing away from the substrate;
mounting a chip in the second groove, wherein one side of the chip with pins faces to the opening of the second groove;
paving a rewiring layer on the cavity structure;
ball placement on the rewiring layer;
the cavity structure is separated from the substrate.
In an alternative embodiment, the first recess and the second recess are symmetrically arranged in the cavity structure.
In an alternative embodiment, the step of mounting the chip in the second recess includes:
adhering the chip to the bottom of the second groove by using an adhesive layer;
and filling glue between the chip and the side wall of the second groove through a glue dispensing process, and baking and curing.
In an alternative embodiment, the step of laying down a rewiring layer on the cavity structure comprises:
a first dielectric layer is coated on the cavity structure and the chip in a rotary mode, and a circuit groove is formed in the first dielectric layer;
and manufacturing a circuit in the circuit groove of the first dielectric layer, wherein the circuit is electrically connected with the pins of the chip.
In an alternative embodiment, the step of implanting balls on the rewiring layer comprises:
spin-coating a second dielectric layer on the first dielectric layer, and forming an open slot on the second dielectric layer;
and arranging a metal bump in the opening groove, electrically connecting the metal bump with the circuit, and manufacturing a tin ball on the metal bump.
In an alternative embodiment, the step of implanting balls on the rewiring layer further comprises:
a metallization transition layer is formed over the metal bump, the metallization transition layer comprising titanium.
In an alternative embodiment, after separating the cavity structure from the substrate, the method for manufacturing the fan-out package structure further includes:
and paving heat dissipation glue on one side of the cavity structure, which is away from the rewiring layer, and filling a part of heat dissipation glue into the first groove.
In an alternative embodiment, after the cavity structure is separated from the substrate, the method for manufacturing the fan-out package structure further includes:
the side of the cavity structure facing away from the rewiring layer is polished to eliminate the first recess.
In a second aspect, the present application provides a fan-out package structure, which is manufactured by the manufacturing method of any one of the foregoing embodiments.
In a third aspect, the present application provides an electronic device, including the fan-out package structure of the foregoing embodiment.
The beneficial effects of the embodiment of the application include, for example:
the manufacturing method of the fan-out type packaging structure comprises the steps of 3D printing a cavity structure on a substrate, wherein a first groove and a second groove are respectively formed in one side of the cavity structure facing the substrate and one side of the cavity structure facing away from the substrate; mounting a chip in the second groove, wherein one side of the chip with pins faces to the opening of the second groove; paving a rewiring layer on the cavity structure; ball placement on the rewiring layer; the cavity structure is separated from the substrate. The cavity structure of double-sided grooves can be manufactured by adopting a 3D printing technology, and the second grooves are used for accommodating and positioning chips, so that the chips are not easy to deviate. The cavity structure of the double-sided groove has higher symmetry in the thickness direction, so that the problem of warping caused by uneven stress distribution is not easy to occur after the double-sided groove is formed. The cavity structure of the double-sided groove is difficult to manufacture by the traditional plastic packaging process, and the 3D printing process can be realized. And compared with the traditional process, the 3D printing process forms the plastic package body in a mould pressing mode, so that warpage is less likely to occur due to the problem of uneven stress. The manufacturing method provided by the application can improve the yield of the product.
The fan-out type packaging structure is manufactured through the manufacturing method, and the electronic equipment provided by the application comprises the fan-out type packaging structure.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered limiting the scope, and that other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a method for fabricating a fan-out package structure according to an embodiment of the present application;
fig. 2 to 7 are schematic diagrams illustrating different stages in a manufacturing process of a fan-out package structure according to an embodiment of the present application;
FIG. 8 is a schematic diagram of a fan-out package structure according to another embodiment of the present application;
fig. 9 is a schematic diagram of a fan-out package structure according to another embodiment of the present application.
Icon: 100-fan-out package structure; 110-cavity structure; 111-a first groove; 112-a second groove; 120-chip; 121-pins; 130-rewiring layer; 131-a first dielectric layer; 132-line; 140-a second dielectric layer; 141-metal bumps; 150-tin balls; 160-heat-dissipating glue; 200-substrate.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, which are generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present application, as provided in the accompanying drawings, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.
In the description of the present application, it should be noted that, if the terms "upper," "lower," "inner," "outer," and the like indicate an azimuth or a positional relationship based on the azimuth or the positional relationship shown in the drawings, or the azimuth or the positional relationship in which the inventive product is conventionally put in use, it is merely for convenience of describing the present application and simplifying the description, and it is not indicated or implied that the apparatus or element referred to must have a specific azimuth, be configured and operated in a specific azimuth, and thus should not be construed as limiting the present application.
Furthermore, the terms "first," "second," and the like, if any, are used merely for distinguishing between descriptions and not for indicating or implying a relative importance.
It should be noted that, without conflict, features in embodiments of the present application may be combined with each other.
In the fan-out packaging process of the wafer in the related art, after plastic packaging, warpage is easy to generate due to material characteristics, a chip after plastic packaging is subsequently adhered to a substrate, the adhesion effect is poor, and the subsequent thermal processing of the subsequent processing is easy to generate stripping problems, so that packaging failure is caused. One of the reasons is that in the molding process of the plastic package, symmetry is poor in the thickness direction of the chip, wherein one side forms a cavity to wrap the chip, and the other side does not synchronously form a cavity, so that uneven stress is easily caused to generate warpage. Moreover, the traditional plastic package adopts mould pressing, and the plastic package material wraps the chip under a certain pressure, so that the chip is easily influenced by the pressure to cause deflection, and the yield is reduced. In addition, in the existing wafer fan-out package, the whole chip after plastic package is adhered to the substrate through temporary bonding and other modes, and then the bonding is required to be released, so that a rewiring layer is manufactured on the surface which is originally adhered to the substrate. This results in complicated packaging process and reduced production efficiency.
In order to improve the shortcomings of the manufacturing method of the fan-out type packaging structure in the related art, the embodiment of the application provides the fan-out type packaging structure, the manufacturing method and the electronic equipment, and the manufacturing method is used for forming the cavity structure of the double-sided groove through 3D printing so as to improve the warpage problem and improve the product yield.
Fig. 1 is a flowchart of a method for manufacturing a fan-out package structure according to an embodiment of the present application. Fig. 2 to 7 are schematic diagrams illustrating different stages in the manufacturing process of the fan-out package structure according to an embodiment of the present application. The method for manufacturing the fan-out package structure provided in the embodiment of the present application is a wafer level package, please refer to fig. 1 to 7, and includes:
step S100, 3D printing is carried out on a substrate to form a cavity structure, wherein a first groove and a second groove are respectively arranged on one side of the cavity structure facing the substrate and one side of the cavity structure facing away from the substrate.
As shown in fig. 2, a 3D printing process is used to form the cavity structure 110 on the substrate 200. In this embodiment, the cavity structure 110 functions similarly to a molding compound formed by molding a molding compound in a conventional packaging process, and is used to encapsulate the chip 120. The cavity structure 110 is manufactured by adopting a 3D printing process, so that a more complex structure (such as a double-sided groove structure in the embodiment) can be manufactured, and the warpage of the packaging structure and the displacement of the chip 120 caused by pressure in the traditional process can be avoided.
The first grooves 111 and the second grooves 112 are respectively disposed on two sides of the cavity structure 110, so that the cavity structure 110 has better symmetry, which is beneficial to reducing uneven stress distribution, thereby improving the warpage problem.
Optionally, the first grooves 111 and the second grooves 112 are symmetrically disposed on the cavity structure 110, so that stress imbalance caused by structural asymmetry can be reduced as much as possible, which is beneficial to reducing warpage.
Further, before 3D printing, a UV glue layer may be coated on the substrate 200, and the cavity structure 110 is formed on the UV glue layer. The UV glue layer may be cured by irradiation of ultraviolet light, including, but not limited to, adhesive glue, epoxy, and Polyimide (PI); the UV glue layer cured or thermally cured by ultraviolet light can be used as a separation layer of a subsequent package structure, so that the substrate 200 can be removed conveniently.
Alternatively, the substrate 200 may be made of glass, silicon oxide, or a metal material; the material of the cavity structure 110 may be glass, metal, or other organic material (such as polyimide). The specific process manner of 3D printing may refer to the prior art, and will not be described herein.
In this embodiment, when the cavity structure 110 is fabricated, a plurality of (two in this embodiment) first grooves 111 and second grooves 112 required for the fan-out package structure 100 may be fabricated at a time. That is, the manufacturing method of the fan-out package structure 100 provided in the embodiment of the present application may simultaneously manufacture a plurality of fan-out package structures 100, and finally may form a single fan-out package structure 100 by cutting, so that the production efficiency may be improved.
In step S200, a chip is mounted in the second groove, and a side of the chip having the pins faces the opening of the second groove.
As shown in fig. 3, the pins 121 of the chip 120 are mounted in the second recess 112 upwards. The chip 120 in this embodiment is a die (or wafer). Specifically, step S200 includes:
step S210, adhering the chip to the bottom of the second groove by utilizing an adhesive layer;
step S220, glue is filled between the chip and the side wall of the second groove through a glue dispensing process, and baking and curing are performed.
By providing glue between the second recess 112 and the chip 120 to fill the gap, the position of the chip 120 is stable, and the risk of displacement of the chip 120 is significantly reduced.
Step S300, laying a rewiring layer on the cavity structure.
As shown in fig. 4, a rewiring layer 130 overlies the cavity structure 110 and the chip 120, and pins 121 of the chip 120 are electrically connected to traces 132 in the rewiring layer 130, such that electrical signal transmission sites on the chip 120 are redistributed through the rewiring layer 130.
In this embodiment, step S300 may specifically include:
step S310, a first dielectric layer is coated on the cavity structure and the chip in a rotary mode, and a line groove is formed in the first dielectric layer.
Specifically, the first dielectric layer 131 may be formed by a physical vapor deposition Process (PVD) or a chemical vapor deposition process (CVD). The line grooves may be formed by means of exposure and development. The material of the first dielectric layer 131 may be silicon nitride, silicon oxynitride, polyimide or benzocyclobutene.
In step S320, a circuit is fabricated in the circuit slot of the first dielectric layer, and the circuit is electrically connected to the pins of the chip.
Optionally, the material of the circuit 132 is copper, and the circuit 132 may be formed by one of Physical Vapor Deposition (PVD), chemical Vapor Deposition (CVD), sputtering, electroplating, or electroless plating.
Step S400, implanting balls on the rewiring layer.
As shown in fig. 5, in an alternative embodiment, step S400 may specifically include:
in step S410, a second dielectric layer is spin-coated on the first dielectric layer, and an open slot is opened on the second dielectric layer.
In the present embodiment, the second dielectric layer 140 may be formed by a physical vapor deposition Process (PVD) or a chemical vapor deposition process (CVD), and the second dielectric layer 140 covers the first dielectric layer 131 and the wiring 132 thereon. The material of the second dielectric layer 140 may be the same as or different from that of the first dielectric layer 131. The bottom of the opening of the second dielectric layer 140 should extend onto the circuit 132, so that the metal bump 141 fabricated later can be electrically connected to the circuit 132.
In this embodiment, the open groove may be opened by a laser.
Step S420, a metal bump is arranged in the opening groove, the metal bump is electrically connected with the circuit, and a tin ball is manufactured on the metal bump.
In the present embodiment, the metal bump 141 is made of copper. Optionally, a metallization transition layer (UBM layer) is formed on metal bump 141 prior to fabricating solder ball 150 on metal bump 141, the metallization transition layer comprising titanium and/or titanium tungsten alloy. The metallized transition layer can promote solderability of solder ball 150, thereby improving product stability. The metallization transition layer (UBM) may have a multi-layer structure (such as an adhesion layer, a barrier layer, a wetting layer), and the specific structure and materials of the UBM layer may refer to the prior art, and will not be described herein.
Alternatively, the solder balls 150 may be formed on the metal bumps 141 by a steel screen printing method or other ball-mounting method. The material of the solder balls 150 may be SnAg, snAgCu, or the like.
Step S500, separating the cavity structure from the substrate.
After the ball placement is completed, the substrate 200 may be disconnected from the cavity structure 110 by irradiating ultraviolet light or otherwise, as shown in fig. 6.
Since the cavity structure 110 fabricated before is a plurality of fan-out package structures 100, dicing is performed after the ball placement is completed, so as to obtain individual fan-out package structures 100, as shown in fig. 7.
Fig. 8 is a schematic diagram of a fan-out package structure 100 according to another embodiment of the present application. As shown in fig. 8, optionally, after separating the cavity structure 110 from the substrate 200, the method for manufacturing the fan-out package structure 100 further includes laying a heat dissipation adhesive 160 on a side of the cavity structure 110 facing away from the rewiring layer 130, where a portion of the heat dissipation adhesive 160 fills the first groove 111.
By laying the heat dissipation glue 160, the heat dissipation performance of the fan-out package structure 100 can be improved. In addition, due to the existence of the first groove 111, the connection stability of the heat dissipation adhesive 160 and the cavity structure 110 can be improved.
Fig. 9 is a schematic diagram of a fan-out package structure 100 according to another embodiment of the present application. As shown in fig. 9, in this embodiment, after the cavity structure 110 is separated from the substrate 200, the method for manufacturing the fan-out package structure 100 further includes grinding a side of the cavity structure 110 facing away from the rewiring layer 130 to eliminate the first groove 111.
The elimination of the first grooves 111 by grinding can further reduce the thickness dimension of the fan-out package 100, which is advantageous for achieving miniaturization of the package and even the device. Meanwhile, by eliminating the first groove 111 through grinding, part of stress in the cavity structure 110 can be released, and the warping problem can be further improved.
The embodiment of the application also provides an electronic device, which comprises the fan-out type packaging structure 100 manufactured by the manufacturing method provided by the embodiment of the application.
In summary, the manufacturing method of the fan-out package structure 100 of the present application includes 3D printing the cavity structure 110 on the substrate 200, where the cavity structure 110 is provided with the first groove 111 and the second groove 112 on the side facing the substrate 200 and the side facing away from the substrate 200, respectively; mounting a chip 120 in the second groove 112, wherein the side of the chip 120 with the pins 121 faces to the opening of the second groove 112; laying a rewiring layer 130 on the cavity structure 110; ball placement on the rewiring layer 130; the cavity structure 110 is separated from the substrate 200. The cavity structure 110 with double-sided grooves can be manufactured by adopting a 3D printing technology, and the second groove 112 is used for accommodating and positioning the chip 120, so that the chip 120 is not easy to deviate. The cavity structure 110 of the double-sided groove has high symmetry in the thickness direction, so that the warpage problem is not easy to occur due to the problem of uneven stress distribution after the cavity structure is formed. The cavity structure 110 of the double-sided recess is difficult to manufacture by the conventional plastic packaging process, and the 3D printing process can be realized. And compared with the traditional process, the 3D printing process forms the plastic package body in a mould pressing mode, so that warpage is less likely to occur due to the problem of uneven stress. The manufacturing method provided by the application can improve the yield of the product.
The fan-out package structure 100 provided by the application is manufactured by the manufacturing method, and the electronic device provided by the application comprises the fan-out package structure 100.
The foregoing is merely specific embodiments of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions easily conceivable by those skilled in the art within the technical scope of the present application should be covered in the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (10)
1. The manufacturing method of the fan-out type packaging structure is characterized by comprising the following steps of:
3D printing a cavity structure on a substrate, wherein a first groove and a second groove are respectively formed in one side of the cavity structure facing the substrate and one side of the cavity structure facing away from the substrate;
mounting a chip in the second groove, wherein one side of the chip with pins faces to an opening of the second groove;
paving a rewiring layer on the cavity structure;
implanting balls on the rewiring layer;
the cavity structure is separated from the substrate.
2. The method of manufacturing a fan-out package structure according to claim 1, wherein the first recess and the second recess are symmetrically disposed on the cavity structure.
3. The method of manufacturing a fan-out package structure according to claim 1, wherein the step of mounting the chip in the second recess includes:
adhering the chip to the bottom of the second groove by using an adhesive layer;
and filling glue between the chip and the side wall of the second groove through a glue dispensing process, and baking and curing.
4. The method of fabricating a fan-out package structure of claim 1, wherein the step of laying down a rewiring layer on the cavity structure comprises:
a first dielectric layer is coated on the cavity structure and the chip in a rotary mode, and a circuit groove is formed in the first dielectric layer;
and manufacturing a circuit in the circuit groove of the first dielectric layer, wherein the circuit is electrically connected with the pins of the chip.
5. The method of fabricating a fan-out package structure of claim 4, wherein the step of implanting balls on the rewiring layer comprises:
spin-coating a second dielectric layer on the first dielectric layer, and forming an open slot on the second dielectric layer;
and arranging a metal bump in the opening groove, wherein the metal bump is electrically connected with the circuit, and a tin ball is manufactured on the metal bump.
6. The method of manufacturing a fan-out package structure of claim 5, wherein the step of implanting balls on the rewiring layer further comprises:
a metallization transition layer is formed on the metal bump, the metallization transition layer comprising titanium.
7. The method of manufacturing a fan-out package structure of claim 1, wherein after separating the cavity structure from the substrate, the method of manufacturing a fan-out package structure further comprises:
and paving heat dissipation glue on one side of the cavity structure, which is away from the rewiring layer, and filling a part of the heat dissipation glue into the first groove.
8. The method of manufacturing a fan-out package structure of claim 1, wherein after the cavity structure is separated from the substrate, the method of manufacturing a fan-out package structure further comprises:
and grinding one side of the cavity structure, which is away from the rewiring layer, so as to eliminate the first groove.
9. A fan-out package structure, characterized in that it is manufactured by the manufacturing method according to any of claims 1-8.
10. An electronic device comprising the fan-out package structure of claim 9.
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| CN102169879A (en) * | 2011-01-30 | 2011-08-31 | 南通富士通微电子股份有限公司 | Highly integrated wafer fan-out packaging structure |
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| CN110660675A (en) * | 2018-06-29 | 2020-01-07 | 台湾积体电路制造股份有限公司 | Semiconductor device and forming method |
| CN114823557A (en) * | 2022-04-06 | 2022-07-29 | 甬矽半导体(宁波)有限公司 | Fan-out type double-sided packaging structure and preparation method thereof |
| CN218918842U (en) * | 2022-10-09 | 2023-04-25 | 成都复锦功率半导体技术发展有限公司 | Fan-out type board level packaging structure capable of reducing warpage and electronic equipment |
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|---|---|---|---|---|
| JP2005332896A (en) * | 2004-05-19 | 2005-12-02 | Oki Electric Ind Co Ltd | Semiconductor device, manufacturing method thereof, chip size package, and manufacturing method thereof |
| US7556984B2 (en) * | 2005-06-17 | 2009-07-07 | Boardtek Electronics Corp. | Package structure of chip and the package method thereof |
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| CN102169879A (en) * | 2011-01-30 | 2011-08-31 | 南通富士通微电子股份有限公司 | Highly integrated wafer fan-out packaging structure |
| CN105225973A (en) * | 2015-11-05 | 2016-01-06 | 南通富士通微电子股份有限公司 | Method for packing |
| CN110660675A (en) * | 2018-06-29 | 2020-01-07 | 台湾积体电路制造股份有限公司 | Semiconductor device and forming method |
| CN114823557A (en) * | 2022-04-06 | 2022-07-29 | 甬矽半导体(宁波)有限公司 | Fan-out type double-sided packaging structure and preparation method thereof |
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| CN117116776A (en) | 2023-11-24 |
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