CN102122624B - Wafer packaging method - Google Patents
Wafer packaging method Download PDFInfo
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- CN102122624B CN102122624B CN2011100345855A CN201110034585A CN102122624B CN 102122624 B CN102122624 B CN 102122624B CN 2011100345855 A CN2011100345855 A CN 2011100345855A CN 201110034585 A CN201110034585 A CN 201110034585A CN 102122624 B CN102122624 B CN 102122624B
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- wafer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Packaging Frangible Articles (AREA)
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Abstract
The invention relates to a wafer packaging method. The method comprises the following steps: providing a transfer board, wherein, a packaging body is fixed on the transfer board and comprises a wafer and an encapsulating layer, and the functional surface of the wafer is exposed; forming a groove between chip units of the wafer, wherein, the groove passes through the wafer; filling the groove; forming a protective layer on the functional surface of the wafer, wherein, an electrical pad on the functional surface of the wafer is exposed; forming an electrical output terminal on the naked electrical pad; separating the transfer board; and cutting the wafer from the position of the groove so as to form a chip packaging unit. Compared with the prior art, the wafer packaging method provided by the invention has the advantages that firstly the groove is formed between the chip units of the wafer, and the encapsulating layer is filled in the groove, thus the encapsulating layer filled in the groove can effectively protect the wafer when the wafer is cut along the groove; and after completion of cutting operation, the protective layer can still protect the surfaces and periphery of the chip units.
Description
Technical field
The present invention relates to semiconductor technology, relate in particular to a kind of wafer packaging method.
Background technology
Wafer-level packaging (Wafer Level Packaging, WLP) technology is that the full wafer wafer is carried out cutting the technology that obtains the single finished product chip after the packaging and testing again, and chip size and nude film after the encapsulation are in full accord.The crystal wafer chip dimension encapsulation technology has thoroughly been overturned conventional package such as ceramic leadless chip carrier (Ceramic Leadless Chip Carrier) and organic leadless chip carrier (Organic LeadlessChip Carrier) isotype, has complied with that market is day by day light, little, short to microelectronic product, thinning and low priceization requirement.It is highly microminiaturized that chip size after crystal wafer chip dimension encapsulation technology encapsulation has reached, chip cost along with chip size reduce significantly reduce with the increase of wafer size.The crystal wafer chip dimension encapsulation technology be IC can be designed, technology that wafer manufacturing, packaging and testing, Substrate manufacture integrate, be the focus of current encapsulation field and the trend of future development.
Chinese invention patent application discloses a kind of wafer-level chip size package method 200910030160.X number, and the method comprising the steps of: fixing one deck glass that covers in the front of wafer is thinned to the setting dimensional thickness with wafer from grinding back surface; Wafer is carried out the isotropism wet etching; To wafer carry out anisotropic wet etch on wafer rear by the design forming groove; Wafer is carried out dry etching, press the design forming hole at the groove face of wafer rear, the hole exposes to wafer rear with the firing point of wafer frontside part; Wafer rear is electroplated the formation metal wire corresponding with firing point quantity by design, and metal wire connection firing point and wafer rear need be planted the place of soldered ball; Plant soldered ball by design in the place that wafer rear need be planted soldered ball; Wafer is cut into single packaged device.
From the description of said method step as can be known, in existing wafer stage chip encapsulation technology, behind the wafer level packaging chip unit cutting is come, around reaching, chip unit surface after the cutting is still exposed chip, be subject to easily the impact of extraneous humiture environment, and anti-mechanical impact ability, and then have influence on the reliability of product.
Summary of the invention
The technical problem that the present invention solves is: when wafer level packaging advances to cut and after the cutting, how for the surface of chip unit and around protection is provided.
For solving the problems of the technologies described above, the invention provides wafer packaging method, comprise step: the reprinting plate is provided, is fixed with packaging body on the described reprinting plate, described packaging body comprises wafer and the envelope bed of material, and the functional surfaces of described wafer exposes; Form groove between the chip unit of wafer, described groove runs through described wafer; Fill described groove; Functional surfaces at described wafer forms protective layer, and described protective layer exposes the electrical pad on the described wafer functional surfaces; Form electrical lead-out terminal at exposed electrical pad; Separate described reprinting plate; Cut described wafer from described groove, form chip packaging unit.
Optionally, the described groove of described filling specifically comprises: with the described groove of the Material Filling that forms the described envelope bed of material.
Alternatively, also comprise step: form again interconnection metal layer at described protective layer; Form the protective layer that exposes described electrical pad at described again interconnection metal layer.
Alternatively, described electrical lead-out terminal is solder ball or metal coupling.
Alternatively, described packaging body is fixed on the described reprinting plate by cementing layer.
Alternatively, the material that forms described cementing layer is UV glue.
Alternatively, the material of the described envelope bed of material is epoxy resin.
Alternatively, the material of described protective layer is polyimides.
Alternatively, the step that forms described packaging body comprises: form cementing layer at basic support plate; The functional surfaces of wafer is affixed on the described cementing layer; The one side of posting wafer on the basic support plate is formed the envelope bed of material, and the described envelope bed of material coats described wafer; Remove described basic support plate and cementing layer.
Compared with prior art, the wafer packaging method that the present invention asks for protection forms first groove between the chip unit of wafer, and fills the envelope bed of material in groove.Therefore, along the groove cutting crystal wafer time, the envelope bed of material of filling in the groove can provide effective protection to wafer.After cutting step was finished, the envelope bed of material still can and provide protection all around for the surface of chip unit.
Description of drawings
Fig. 1 is encapsulation method of system level fan-out wafer flow chart in the one embodiment of the invention;
Fig. 2 is encapsulation method of system level fan-out wafer flow chart in the another embodiment of the present invention;
Fig. 3 to Figure 12 is packaging body schematic diagram in the flow process shown in Figure 2.
Embodiment
A lot of details have been set forth in the following description so that fully understand the present invention.But the present invention can implement much to be different from alternate manner described here, and those skilled in the art can do similar popularization in the situation of intension of the present invention, so the present invention is not subjected to the restriction of following public implementation.
Secondly, the present invention utilizes schematic diagram to be described in detail, and when the embodiment of the invention was described in detail in detail, for ease of explanation, described schematic diagram was example, and it should not limit the scope of protection of the invention at this.
Below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
As shown in Figure 1, in one embodiment of the invention, provide wafer packaging method.The method comprising the steps of:
S101 provides the reprinting plate, reprints to be fixed with the packaging body that comprises wafer and the envelope bed of material on the plate, and the functional surfaces of described wafer exposes;
S102 forms groove between the chip unit of wafer;
S107 fills described groove;
Identical with the material of the aforementioned formation envelope bed of material in order to the material of filling described groove, and described functional surfaces exposes;
S103 forms protective layer at the functional surfaces of described wafer, and described protective layer exposes the electrical pad on the described wafer functional surfaces;
S104, the electrical pad exposed at the functional surfaces of wafer forms electrical lead-out terminal;
S105 peels off the reprinting plate, removes cementing layer;
S106 is cut apart wafer from groove, forms chip packaging unit.
As shown in Figure 2, in another embodiment of the present invention, provide wafer packaging method.The method comprising the steps of:
S201 forms cementing layer at basic support plate;
S202 is affixed on the functional surfaces of wafer on the cementing layer;
S203, the one side of basic support plate being posted wafer forms the envelope bed of material, forms packaging body;
S204 removes cementing layer, separates basic support plate;
S205 forms cementing layer at the reprinting plate;
S206 is fitted in packaging body on the cementing layer of reprinting plate, and makes the functional surfaces of wafer exposed;
S207 forms groove between the chip unit of wafer;
S212 fills described groove;
S208 forms protective layer at the functional surfaces of described wafer, and described protective layer exposes the electrical pad on the described wafer functional surfaces;
S209 forms electrical lead-out terminal at exposed electrical pad;
S210 peels off the reprinting plate, removes cementing layer;
S211 is cut apart wafer, forms chip packaging unit.
In the present embodiment, step S201 is the process that forms packaging body to step S204.Wherein, execution in step S201 forms cementing layer 102 at basic support plate 101, can form structure as shown in Figure 3.Employed basic support plate 101 is bases of carrying wafer 103 in subsequent step in this step.
In the present embodiment, basic support plate 101 can adopt glass material, in order to preferably hardness and evenness to be provided, reduces the inefficacy ratio of packaging.In addition, owing to basic support plate 101 can be stripped from subsequent step, and the basic support plate 101 of glass material is easily peeled off, resistance to corrosion is strong, can because of the change that the physics and chemistry performance occurs with contacting of cementing layer 102, therefore can not reuse.Certainly, those skilled in the art understand, and basic support plate 101 for example adopts silicon compound also can realize purpose of the present invention.
The cementing layer 102 that forms at basic support plate 101 is for wafer 103 is fixed on support plate 101.Cementing layer 102 available materials have multiple, and in an optional embodiment of the present invention, cementing layer 102 adopts UV glue.UV glue be a kind of can be to the aitiogenic glueing material of the UV-irradiation of special wavelength.UV glue according to UV-irradiation after the variation of viscosity can be divided into two kinds, a kind of is that UV solidifies glue, be that light trigger in the material or sensitising agent produce living radical or cation behind the absorbing ultraviolet light under ultraviolet irradiation, trigger monomer polymerization, crosslinked and connect Zhi Huaxue reaction, it is solid-state that ultraviolet cured adhesive was converted into by liquid state within the several seconds, thereby the body surface that is in contact with it is bonding; Another kind be UV glue be not through when irradiation ultraviolet ray viscosity very high, caused viscosity to decline to a great extent or disappear and interrupt through the crosslinking chemical bond in the material after the UV-irradiation.The UV glue that the cementing layer 102 here adopts namely is the latter.
The method that forms cementing layers 102 at basic support plate 101 can be such as being by methods such as spin coating or printings cementing layer 102 to be coated on the basic support plate 101.Such method is well known to those skilled in the art in field of semiconductor manufacture, does not repeat them here.
After basic support plate 101 forms cementing layers 102, can execution in step S202, the functional surfaces of wafer 103 is affixed on the cementing layer 102, form structure as shown in Figure 4.
In the specific embodiment of the present invention, the functional surfaces of wafer 103 refers to that electrical pad 104 places of chip on the wafer 103 are surperficial.
Then execution in step S203 posts the one side formation of wafer 103 with the packaging body of the envelope bed of material 105 at basic support plate 101, and packaging body coats wafer 103, namely forms structure as shown in Figure 5.In the subsequent technique process, the envelope bed of material 105 both can be protected wafer 103, can be used as again the supporting body of subsequent technique.
In one embodiment of the invention, forming the material that seals the bed of material 105 is epoxy resin.The good seal performance of this material, plastotype is easy, is the preferred materials that forms the envelope bed of material 105.The method that forms the envelope bed of material 105 can for example be the method for metaideophone, compression or printing.The concrete steps of these methods are well known to those skilled in the art, do not repeat them here.
Execution in step S204 will peel off from basic support plate 101 with the packaging body of wafer 103 again, and remove cementing layer 102, form structure as shown in Figure 6.After separating basic support plate 101, cementing layer residual on the functional surfaces 102 can also be cleaned up.The electrical pad of chip also exposes out on the functional surfaces of wafer 103 at this moment.
To step 204, namely formed the packaging body that comprises wafer 103 and the envelope bed of material 105 at execution of step S201.
Then execution in step S205 reprinting plate 106 formation cementing layers 107, namely forms structure as shown in Figure 7.Employed reprinting plate 106 also is the basis of carrying wafer 103 in subsequent step in this step.The reprinting plate 106 here also can adopt glass material, in order to preferably hardness and evenness to be provided, reduces the inefficacy ratio of packaging, can certainly adopt for example silicon compound.Because identical to the characteristic demand to basic support plate 101 among the characteristic demand of employed reprinting plate 106 and the step S201 in step S205, and the complete separation in abovementioned steps of basic support plate 101 therefore can be with isolated basic support plate 101 in the abovementioned steps as reprinting plate 106 in step S205.The cementing layer 107 that forms at reprinting plate 106 is to reprint plate 106 for aforementioned packaging body is fixed on.The cementing layer 107 here also can be selected the UV glue identical with cementing layer 102.
And then execution in step S206, will be fitted in the packaging body of wafer 103 on the cementing layer 107 of reprinting plate 106, make the functional surfaces of wafer 103 exposed, form structure as shown in Figure 8.This step namely is to reprint the fixedly formed packaging body of abovementioned steps of plate 106.
Then execution in step S207 forms the groove 108 that runs through wafer 103 between the chip unit of wafer 103, forms structure as shown in Figure 9.Groove 108 is actually precut to wafer 103, is the early-stage preparations to last cutting and separating chip unit.
Then execution in step S212 fills described groove 108, and is identical with the material of the aforementioned formation envelope bed of material 105 in order to the material of filling described groove 108.Wafer 103 after filling, described functional surfaces exposes.
Execution in step S208 again, as shown in figure 10, selectivity forms protective layer 109 to expose the electrical pad 104 of chip unit on the functional surfaces of wafer 103.As previously mentioned, before this step forms protective layer 109, allow form the Material Filling groove 108 that seals the bed of material 105.Therefore follow-up during along groove 108 cutting crystal wafer 103; the envelope bed of material 105 that presets among the envelope bed of material 105 in the groove 108 and Fig. 3 can provide to the side of chip unit effective protection, and the side that the envelope bed of materials 105 in the groove 108 are avoided chip unit is exposed and be subject to the impact of external environment afterwards in cutting.In an optional embodiment of the present invention, the material that forms protective layer 109 is polyimides.
In one embodiment of the invention, the protective layer 109 that forms in above-mentioned steps again behind step S208 forms again interconnection metal layer, makes the electrical pad 104 of chip unit borrow interconnection metal layer to be shifted again.And can on described again interconnection metal layer, again form protective layer and optionally cover described again interconnection metal layer, to expose the electrical pad 104 after the transfer.Described again interconnection metal layer and described protective layer are arranged in sandwich mode, and multilayer can be set.That is to say, arrange the described again interconnection metal layer of one deck on the described protective layer of one deck, and then arrange the described protective layer of one deck.Above-mentioned steps can be carried out as required repeatedly, and above-mentioned steps is optional step, selects subsequent step to continue or the electrical pad after transfer continues at the original electrical pad 104 of chip unit according to the design needs.If subsequent step continues at the original electrical pad 104 of chip unit, then directly enter into step S209.
Then execution in step S209 forms electrical lead-out terminal 110 at exposed electrical pad 104.This electrical lead-out terminal 110 is solder ball or metal coupling, and the method is known by the technical field of semiconductors personnel, does not repeat them here.Execution in step S210 peels off and reprints plate 106 again, removes cementing layer 107, forms structure as shown in figure 11.
Execution in step S211 again from groove 108 cutting crystal wafers 103, forms structure as shown in figure 12 at last.In existing wafer stage chip encapsulation technology, behind the wafer level packaging chip unit 103a cutting is come, be still exposed chip around the chip unit 103a surface after the cutting reaches, be subject to easily the impact of extraneous humiture environment, and anti-mechanical impact ability, and then have influence on the reliability of product.As previously mentioned; between the chip unit 103a of wafer 103, form first groove 108; and at the groove 108 interior filling envelope bed of materials 105; the described envelope bed of material 105 has coated the back side and the side of chip unit 103a; functional surfaces at chip unit 103a forms protective layer 109; the electrical pad 104 that described protective layer 109 exposes on described wafer 103 functional surfaces; at last again along groove 108 cutting crystal wafers 103; can make chip unit 103a around protection all arranged; thereby avoid the exposed integrity problem that brings of prior art chips, increased simultaneously the mechanical strength of chip unit 103a.
Although the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can make various changes or modifications, so protection scope of the present invention should be as the criterion with the claim limited range.
Claims (9)
1. wafer packaging method is characterized in that, comprises step:
The reprinting plate is provided, is fixed with packaging body on the described reprinting plate, described packaging body comprises wafer and the envelope bed of material, and the functional surfaces of described wafer exposes;
Form groove between the chip unit of wafer, described groove runs through described wafer;
Fill described groove;
Functional surfaces at described wafer forms protective layer, and described protective layer exposes the electrical pad on the described wafer functional surfaces;
Form electrical lead-out terminal at exposed electrical pad;
Separate described reprinting plate;
Cut described wafer from described groove, form chip packaging unit.
2. wafer packaging method as claimed in claim 1 is characterized in that, the described groove of described filling specifically comprises: with the described groove of the Material Filling that forms the described envelope bed of material.
3. wafer packaging method as claimed in claim 1 is characterized in that, before forming described electrical lead-out terminal, also comprises step:
Form again interconnection metal layer at described protective layer;
Form the protective layer that exposes described electrical pad at described again interconnection metal layer.
4. wafer packaging method as claimed in claim 1, it is characterized in that: described electrical lead-out terminal is solder ball or metal coupling.
5. wafer packaging method as claimed in claim 1, it is characterized in that: described packaging body is fixed on the described reprinting plate by cementing layer.
6. wafer packaging method as claimed in claim 5, it is characterized in that: the material that forms described cementing layer is UV glue.
7. wafer packaging method as claimed in claim 1, it is characterized in that: the material of the described envelope bed of material is epoxy resin.
8. wafer packaging method as claimed in claim 1, it is characterized in that: the material of described protective layer is polyimides.
9. wafer packaging method as claimed in claim 1 is characterized in that, the step that forms described packaging body comprises:
Form cementing layer at basic support plate;
The functional surfaces of wafer is affixed on the described cementing layer;
The one side of posting wafer on the basic support plate is formed the envelope bed of material, and the described envelope bed of material coats described wafer;
Remove described basic support plate and cementing layer.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2011100345855A CN102122624B (en) | 2011-02-01 | 2011-02-01 | Wafer packaging method |
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| CN2011100345855A CN102122624B (en) | 2011-02-01 | 2011-02-01 | Wafer packaging method |
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| CN102122624A CN102122624A (en) | 2011-07-13 |
| CN102122624B true CN102122624B (en) | 2013-02-13 |
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102244061A (en) | 2011-07-18 | 2011-11-16 | 江阴长电先进封装有限公司 | Low-k chip package structure |
| CN104835808A (en) | 2015-03-16 | 2015-08-12 | 苏州晶方半导体科技股份有限公司 | Chip packaging method and chip packaging structure |
| CN105390403B (en) * | 2015-10-13 | 2017-10-20 | 中国电子科技集团公司第五十四研究所 | A kind of substrate cavity fill method in LTCC thick films electric hybrid board manufacture |
| CN110970361B (en) * | 2018-09-28 | 2021-11-16 | 典琦科技股份有限公司 | Method for manufacturing chip package |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101026107A (en) * | 2006-02-24 | 2007-08-29 | 日月光半导体制造股份有限公司 | Wafer level package bump manufacturing method |
| WO2008096943A1 (en) * | 2007-02-09 | 2008-08-14 | Ls Mtron, Ltd. | Multifunctional die attachment film and semiconductor packaging method using the same |
| CN101388367A (en) * | 2007-09-13 | 2009-03-18 | 海华科技股份有限公司 | Wafer stage package method and package construction |
| US7745261B2 (en) * | 2008-02-26 | 2010-06-29 | Shanghai Kaihong Technology Co., Ltd. | Chip scale package fabrication methods |
-
2011
- 2011-02-01 CN CN2011100345855A patent/CN102122624B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101026107A (en) * | 2006-02-24 | 2007-08-29 | 日月光半导体制造股份有限公司 | Wafer level package bump manufacturing method |
| WO2008096943A1 (en) * | 2007-02-09 | 2008-08-14 | Ls Mtron, Ltd. | Multifunctional die attachment film and semiconductor packaging method using the same |
| CN101388367A (en) * | 2007-09-13 | 2009-03-18 | 海华科技股份有限公司 | Wafer stage package method and package construction |
| US7745261B2 (en) * | 2008-02-26 | 2010-06-29 | Shanghai Kaihong Technology Co., Ltd. | Chip scale package fabrication methods |
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Address after: Jiangsu province Nantong City Chongchuan road 226006 No. 288 Patentee after: Tongfu Microelectronics Co., Ltd. Address before: 226006 Jiangsu Province, Nantong City Chongchuan District Chongchuan Road No. 288 Patentee before: Fujitsu Microelectronics Co., Ltd., Nantong |